I2C bus verification method and verification system

Abstract

The present invention discloses a verification method for an I2C bus applied to the verification system, comprising the following steps: a. importing a timing parameter table that complies with the I2C bus specification; b. adjusting the duty cycle of the SCL signal output by the I2C bus verification environment according to the test setting; c. adding timing to the SDA signal output by the I2C bus verification environment, and detecting the timing difference of the SDA signal in the test case; d. comparing the timing difference with the timing parameter table. Accordingly, the present invention also discloses an I2C bus verification system. The I2C bus verification method and verification system of the present invention can dynamically adjust the duty cycle of the clock signal, meet a wider range of application tests, and greatly improve the reliability of verification.

Description

Technical Field

[0001] The present invention relates to the field of bus interface technology verification, and more particularly to an I2C bus verification method and verification system. Background Art

[0002] The I2C bus is a two-wire serial protocol. In the traditional verification process, the stimulus is often generated based on the SCL (I2C bus clock signal) clock edge generated by the host to determine when to send or sample the SDA (I2C bus data signal) data signal, thereby realizing protocol communication. However, in real-world situations, the timing is often not so ideal. The SDA data signal and the SCL clock signal have setup and hold times. When the I2C bus is in different operating modes (standard-mode), fast-mode, or high-speed mode (hs-mode), the corresponding timing parameters that comply with the I2C bus specification (THEI2C-BUS SPECIFICATION) are shown in Tables 1 and 2:

[0003]

[0004] Table 1

[0005]

[0006] Table 2

[0007] Table 1 shows the timing parameters in high-speed mode that comply with the I2C bus specification, and Table 2 shows the timing parameters in standard mode and fast mode that comply with the I2C bus specification.

[0008] As shown in Tables 1 and 2, the timing parameters for the I2C bus vary depending on its operating mode: standard mode, fast mode, or high-speed mode (hs-mode). Therefore, the reusability of the verification environment is limited. Traditional methods do not automatically detect timing. Timing issues are a concern during gate-level simulation (post-simulation), but traditional methods lack the ability to detect them in different modes. In practice, jitter and varying duty cycles of the SCL clock signal can also affect protocol communication.

[0009] In the current verification process, timing parameters are set in a single, unchangeable format. Manual parameter modification is required when operating I2C in different modes (standard-mode, fast-mode, or hs-mode). These changes affect the signal driver output, effectively rebuilding the environment. There's also no timing check module, and timing verification is typically focused on during gate-level simulation (post-simulation). Setup and hold times are not considered during pre-simulation. Furthermore, the SCL signal duty cycle is uncontrollable, making it impossible to simulate real-world SCL clock jitter. This is because many SCL signal designs use a 50% duty cycle, and without explicit regulations, this rarely occurs. Designers often overlook SCL clock jitter during pre-simulation, but this doesn't mean it has no impact on the actual chip. Sometimes, a chip may have no timing violations but still malfunction at a certain duty cycle limit, impacting the overall chip's operational stability.

[0010] Therefore, it is necessary to provide an I2C bus verification method and verification system that can achieve reusability of the verification environment of the I2C bus in various modes, automation of timing detection, and controllability of the SCL signal duty cycle. Summary of the Invention

[0011] The object of the present invention is to provide an I2C bus verification method and verification system. The I2C bus verification method and verification system of the present invention can dynamically adjust the duty cycle of the clock signal, meet a wider range of application tests, and greatly improve the reliability of verification.

[0012] To achieve the above objectives, the present invention provides an I2C bus verification system, which is arranged between an I2C bus verification environment and a test case, and a timing parameter table that complies with the I2C bus specification is provided in the verification system, which includes:

[0013] An SCL signal output module receives the SCL signal output by the I2C bus verification environment, performs timing adjustment, and outputs the adjusted SCL signal to the case to be tested;

[0014] An SDA signal adapter module receives the SDA signal output by the I2C bus verification environment, adds timing to the received SDA signal, and outputs the SDA signal with increased timing to the case to be tested. During the test, the SDA signal of the case to be tested is input into the I2C bus verification environment through the SDA signal adapter module;

[0015] The timing detection module is used to detect whether the timing of the SCL signal output by the SCL signal output module to the case to be tested and the timing of the SDA signal transmitted between the SDA signal adapter module and the case to be tested meet the specification requirements of the I2C bus.

[0016] Preferably, the SCL signal output module adjusts the duty cycle of the SCL signal.

[0017] Preferably, the SDA signal switching module increases the timing of the received SDA signal according to the minimum timing requirement in the specification of the I2C bus.

[0018] Correspondingly, the present invention also provides an I2C bus verification method applied to the verification system, which includes the following steps: a. importing a timing parameter table that complies with the I2C bus specification; b. adjusting the duty cycle of the SCL signal output by the I2C bus verification environment according to the test settings; c. adding timing to the SDA signal output by the I2C bus verification environment, and detecting the timing difference of the SDA signal in the case to be tested; d. comparing the timing difference with the timing parameter table.

[0019] Preferably, the step a further comprises adjusting the time unit of the imported timing parameters to a unified time unit.

[0020] Preferably, the step b includes:

[0021] According to the period of the SCL signal output by the I2C bus verification environment, the high-level duration T1 and the low-level duration T2 are calculated. Both T1 and T2 are greater than the corresponding time parameters in the I2C bus specification.

[0022] Preferably, the step c also includes: outputting an SCL signal to the case to be tested, after the falling edge of the SDA signal output by the I2C bus verification environment ends, driving SCL to a low level after the waiting time reaches the high level holding time, and maintaining it for T2 nanoseconds, and then driving SCL to a high level and maintaining it for T1 nanoseconds.

[0023] Preferably, increasing the timing of the SDA signal output by the I2C bus verification environment specifically includes increasing the timing of the received SDA signal according to the minimum timing requirement in the I2C bus specification.

[0024] Preferably, the timing difference of the SDA signal in the test case is detected by recording the current simulation time at the falling edge and rising edge of each SDA and SCL signal, and the timing difference is the time recorded at the falling edge / rising edge of SDA minus the time of the rising edge / falling edge of SCL.

[0025] Preferably, in step d, the timing difference is compared with the timing parameter table, and if the current timing difference is smaller than the corresponding parameter in the timing parameter table, the corresponding violation information and time point are printed.

[0026] Compared with the prior art, the I2C bus verification method and verification system of the present invention can realize the functions of optional I2C working mode, adjustable clock duty cycle, and automatic timing detection without modifying the original I2C verification environment. The I2C bus verification system is equivalent to an interface, the two ends of which are respectively connected to the verification environment and the case to be tested. Timing parameters are added to the signal input to the verification environment inside the interface, and then output to the case to be tested. The timing of the signal input to the case to be tested is automatically checked and output to the verification environment, which greatly improves the reliability of the verification; at the same time, the duty cycle of the SCL clock can be changed in the interface according to the test requirements and output to the case to be tested. Different I2C working modes can be realized by simply changing the timing parameter value in the interface in different modes, which greatly improves the reusability of the verification environment.

[0027] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a structural block diagram of the I2C bus verification system of the present invention.

[0029] Figure 2 Flowchart of the I2C bus verification method of the present invention.

[0030] Figure 3 This is a timing diagram of the SDA signal and the SCL signal in the I2C bus verification method and verification system of the present invention. DETAILED DESCRIPTION

[0031] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which like reference numerals represent like elements. As described above, the present invention provides an I2C bus verification method and system. The I2C bus verification method and system of the present invention can dynamically adjust the duty cycle of a clock signal, thereby meeting a wider range of application tests and significantly improving verification reliability.

[0032] Please refer to Figure 1 , Figure 1This is a block diagram of the structure of the I2C bus verification system of the present invention. As shown in the figure, the I2C bus verification system of the present invention is set between the I2C bus verification environment and the case to be tested, and a timing parameter table that complies with the I2C bus specification is set in the verification system. The timing parameter table is shown in Table 1 and Table 2, which corresponds to the minimum timing that each parameter of the I2C bus must meet in different working modes (standard mode, fast mode or high-speed mode) to ensure that communication can proceed normally. The I2C bus verification system includes: an SCL signal output module, an SDA signal switching module and a timing detection module. Specifically:

[0033] An SCL signal output module receives the SCL signal output by the I2C bus verification environment and performs timing adjustment, and outputs the adjusted SCL signal to the case to be tested; wherein, the timing adjustment of the SCL signal specifically refers to adjusting the duty cycle of the SCL signal; the SCL signal is emitted by the I2C bus verification environment, its direction is determined, and its clock frequency is also determined, so the period of the SCL signal clock can be calculated in the verification system of the I2C bus, and according to the duty cycle setting (the clock duty cycle of the SCL signal can be directly defined and modified in the verification system of the I2C bus, and the duty cycle can be set according to the specific circumstances of the verification), the high level duration T1 and the low level duration T2 are calculated, wherein T1 and T2 are both calculated in nanoseconds; in addition, in the present invention, in order to facilitate coordinated and unified calculations, the units of other time parameters are adjusted to nanoseconds for calculation.

[0034] An SDA signal adapter module receives the SDA signal output by the I2C bus verification environment, adds timing to the received SDA signal, and outputs the SDA signal with the added timing to the test case. During testing, the SDA signal of the test case is input into the I2C bus verification environment through the SDA signal adapter module. Since a timing parameter table that complies with the I2C bus specification is provided within the verification system, and the timing corresponding to the timing parameter table is the minimum timing that meets the specification, in the present invention, the SDA signal adapter module adds timing to the received SDA signal according to the minimum timing requirements of the I2C bus specification, so that the I2C bus verification environment and the test case can communicate normally through the SDA signal adapter module.

[0035] A timing detection module is used to detect whether the timing of the SCL signal output by the SCL signal output module to the case to be tested and the timing of the SDA signal transmitted between the SDA signal adapter module and the case to be tested meet the specification requirements of the I2C bus; wherein, detecting the timing of the SCL signal output by the SCL signal output module to the case to be tested is mainly used to determine whether the duty cycle adjustment of the SCL signal meets the specification requirements of the I2C bus. If not, it needs to be readjusted or an error report is output; and detecting the timing of the SDA signal transmitted between the SDA signal adapter module and the case to be tested is mainly to detect the SDA signal of the test case before the SDA signal is input into the I2C bus verification environment to determine whether it meets the I2C bus specification, so that normal detection can be performed. If it does not meet the I2C bus specification, an error report is output and the SDA signal is stopped from continuing to be input into the I2C bus verification environment; therefore, the detection efficiency and detection accuracy are improved.

[0036] In addition, the present invention also provides an I2C bus verification method, which is implemented based on the above-mentioned I2C bus verification system. Figure 2 and Figure 3 The I2C bus verification method of the present invention comprises the following steps:

[0037] Step S101: Importing a timing parameter table that complies with the I2C bus specification. In this step, the imported timing parameter table that complies with the I2C bus specification is the parameters listed in Tables 1 and 2, which correspond to the minimum timings that each parameter must meet in different operating modes of the I2C bus (standard mode, fast mode, or high-speed mode). As can be seen from Tables 1 and 2, when the I2C bus is in different operating modes, its corresponding timing parameters are also different. In the present invention, the timing parameter tables corresponding to the three operating modes of the I2C bus are imported, so that the operating mode can be flexibly selected according to specific circumstances during the subsequent verification process. Therefore, different I2C bus operating modes can be achieved by simply changing the timing parameter values ​​in the verification system under different modes, greatly improving the reusability of the I2C bus verification environment. Furthermore, this step also includes adjusting the time units of the imported timing parameters to a unified time unit to facilitate unified calculation and reduce calculation errors. In a preferred embodiment of the present invention, the units of each time parameter are adjusted to nanoseconds for calculation, but this is of course not limited to this method.

[0038] Step S102, adjusting the duty cycle of the SCL signal output by the I2C bus verification environment according to the test settings; in this step, the clock duty cycle of the SCL signal can be directly defined and modified in the I2C bus verification system, and the duty cycle can be set according to the specific circumstances of the verification. Specifically, in this step, the high-level duration T1 and the low-level duration T2 are calculated according to the period of the SCL signal output by the I2C-bus verification environment, and both T1 and T2 are greater than the corresponding time parameters in the I2C-bus specification; since the SCL signals are all sent by the I2C-bus verification environment, the direction is determined and its clock frequency can also be determined, so the clock period can be calculated in the I2C-bus verification environment, and then the high-level duration T1 nanoseconds and the low-level duration T2 nanoseconds are calculated according to the set duty cycle; however, T1 must be greater than or equal to tHIGH (high-level hold time) in the I2C-bus specification, and T2 must be greater than or equal to tLOW (low-level hold time) in the I2C-bus specification, and tHIGH and tHIGH are both minimum standards, and less than this will result in a timing violation.

[0039] Step S103, adding timing to the SDA signal output by the I2C bus verification environment, detecting the timing difference of the SDA signal in the case to be tested; in this step, specifically, the SCL signal output to the case to be tested, after the falling edge of the SDA signal output by the I2C bus verification environment ends, the waiting time reaches the high level holding time, and then the SCL is driven to a low level and maintained for T2 nanoseconds, and then the SCL is driven to a high level and maintained for T1 nanoseconds, T2 must be greater than or equal to tHIGH, so as to achieve the set duty cycle; and for the SDA signal output by the I2C bus verification environment, After the falling edge of the SCL signal output to the case to be tested ends, wait for tHD_DAT (see Table 1 and Table 2 for details) nanoseconds, then drive the SDA signal output to the case to be tested to an indeterminate state, maintain T2-tHD_DAT-tSU_DAT (data setup time) nanoseconds, and then drive it to its original state (directly transfer the SDA signal output by the I2C bus verification environment to the case to be tested); this completes the addition of timing to the SDA signal, because when driving out of the indeterminate state, if the design does not meet the requirements, the indeterminate state will be sampled, causing simulation errors. In addition, in this step, the timing of the received SDA signal is increased according to the minimum timing requirements in the I2C bus specification. Because the minimum timing requirements in the I2C bus specification are met, all data communications can proceed normally and there will be no communication failures. To detect the timing difference of the SDA signal in the test case, specifically, record the current simulation time at the falling edge and rising edge of each SDA and SCL signal, and subtract the time of the SCL rising edge / falling edge from the time of the SDA falling edge / rising edge to obtain the timing difference.

[0040] Step S104, compare the timing difference with the timing parameter table; in this step, if the current timing difference is less than the corresponding parameter in the timing parameter table, the corresponding violation information and time point are printed. That is, if the current timing difference is greater than or equal to the corresponding parameter in the timing parameter table, it indicates that the SDA signal of the case to be tested matches the I2C bus verification environment through timing adjustment and the test operation can be carried out normally. Otherwise, the corresponding violation information and time point are printed to prompt corresponding modifications or adjustments.

[0041] Furthermore, please refer to Table 1, Table 2 and Figure 3 This section describes the process of detecting timing discrepancies in the SDA signal in the test case and comparing it with the timing parameter table: When the SDA signal falls, the SCL signal is determined to be high. The time difference is calculated by subtracting the SCL rising edge from the time of the SDA falling edge. If this time difference is less than tSU_STA, a timing issue exists. The corresponding violation information and time point are printed. Similarly, when SDA is low, the difference between the SDA falling edge time point and the SCL falling edge time point is used to determine whether tHD_STA is violated. If so, the corresponding violation information and time point are printed. The tLOW violation is determined by subtracting the SCL falling edge time from the SCL rising edge time. If so, the corresponding violation information and time point are printed. The tHIGH violation is determined by subtracting the SCL rising edge time from the SCL falling edge time. If so, the corresponding violation information and time point are printed. During the rising or falling edge of SDA, if SCL is low and the time of the SDA change is greater than the time of the SCL falling edge, the tHD_DAT violation is determined by subtracting the SCL falling edge from the SDA change time. If a violation occurs, the corresponding violation information and time point are printed. If the SCL rising edge time point is greater than the SDA change time point, and the SCL rising edge time point minus the SDA change time point is less than tSU_DAT, a timing violation is reported and the specific time point is printed. When SCL is high, if the SDA rising edge time point is greater than the SCL rising edge time point, and the value obtained by subtracting the SDA rising edge from the SCL rising edge is less than tSU_STO, a timing violation is reported and the timing violation information and the relevant time point are printed. If SCL is high and the SDA falling edge time point is greater than the SDA rising edge time point, and the value obtained by subtracting the SDA falling edge from the SCL rising edge is less than tBUF, a timing violation is reported and the corresponding violation information and time point are printed. For details on the above parameters, see Tables 1 and 2. tf and tr in Tables 1 and 2 are negligible due to their small values ​​(not configured in this solution). Cb, VnL, and VnH are irrelevant to timing and are not described for their configuration. In summary, all timing violations have been detected.

[0042] To sum up, the verification system of the I2C bus of the present invention is a data signal interface, which can connect the verification environment and the design to be tested. Timing parameters can be added to the signal output by the verification environment inside the interface, and different parameter values ​​can be added according to different working modes, and then output to the design to be tested. After the signal output by the design to be tested enters the interface, the interface will perform timing detection on the signal according to different working modes. When the requirements are not met, an error will be reported and the simulation will be terminated; in addition, the duty cycle of the clock signal can be dynamically adjusted in the interface to meet a wider range of test conditions; thereby, the three working modes of I2C can be realized under the same verification environment, without the need to build a new verification environment, saving time; in addition, the timing detection of the output signal of the design to be tested can greatly improve the reliability of verification.

[0043] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.

Claims

1. An I2C bus verification system, characterized in that: The verification system is arranged between the I2C bus verification environment and the test case, and a timing parameter table that complies with the I2C bus specification is provided in the verification system, which includes: An SCL signal output module receives the SCL signal output by the I2C bus verification environment, performs timing adjustment, and outputs the adjusted SCL signal to the case to be tested; An SDA signal adapter module receives the SDA signal output by the I2C bus verification environment, adds timing to the received SDA signal, and outputs the SDA signal with increased timing to the case to be tested. During testing, the SDA signal of the case to be tested is input into the I2C bus verification environment through the SDA signal adapter module; The timing detection module is used to detect whether the timing of the SCL signal output by the SCL signal output module to the case to be tested and the timing of the SDA signal transmitted between the SDA signal adapter module and the case to be tested meet the specification requirements of the I2C bus.

2. The I2C bus verification system according to claim 1, wherein: The SCL signal output module adjusts the duty cycle of the SCL signal.

3. The I2C bus verification system according to claim 1, wherein: The SDA signal transfer module increases the timing of the received SDA signal according to the minimum timing requirements in the I2C bus specification.

4. A verification method for an I2C bus applied to the verification system according to claim 1, characterized in that: The steps include: a. Import the timing parameter table that complies with the I2C bus specification; b. Adjust the duty cycle of the SCL signal output by the I2C bus verification environment according to the test settings; c. Add timing to the SDA signal output by the I2C bus verification environment and detect the timing difference of the SDA signal in the case to be tested; d. Compare the timing difference with the timing parameter table.

5. The I2C bus verification method according to claim 4, wherein: The step a specifically includes adjusting the time unit of the imported timing parameters to a unified time unit.

6. The I2C bus verification method according to claim 5, wherein: The step b comprises: According to the period of the SCL signal output by the I2C bus verification environment, the high-level duration T1 and the low-level duration T2 are calculated. Both T1 and T2 are greater than the corresponding time parameters in the I2C bus specification.

7. The I2C bus verification method according to claim 6, wherein: The step c also includes: outputting an SCL signal to the case to be tested, after the falling edge of the SDA signal output by the I2C bus verification environment ends, driving the SCL to a low level after the waiting time reaches the high level hold time, and maintaining it for T2 nanoseconds, and then driving the SCL to a high level and maintaining it for T1 nanoseconds.

8. The I2C bus verification method according to claim 4, wherein: Adding timing to the SDA signal output by the I2C bus verification environment specifically includes adding timing to the received SDA signal according to the minimum timing requirements in the I2C bus specification.

9. The I2C bus verification method according to claim 4, wherein: To detect the timing difference of the SDA signal in the test case, specifically, record the current simulation time at the falling edge and rising edge of each SDA and SCL signal, and subtract the time of the SCL rising edge / falling edge from the time of the SDA falling edge / rising edge to obtain the timing difference.

10. The I2C bus verification method according to claim 9, wherein: In the step d, the timing difference is compared with the timing parameter table. If the current timing difference is smaller than the corresponding parameter in the timing parameter table, the corresponding violation information and time point are printed.

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