3D NAND flash memory reference voltage optimization adjustment method, system and medium

Abstract

The present invention discloses a 3D NAND flash memory reference voltage optimization and adjustment method, system and medium, the method includes the following steps: S1: randomly select a NAND flash memory block and add PEC noise, retention noise and Read noise in sequence, and perform PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block after adding noise; S2: establish a reference voltage adjustment model using PEC-Ret threshold voltage and PEC-Ret-Read threshold voltage; S3: calculate a reference voltage offset value using the reference voltage adjustment model, and read data from the NAND flash memory block using the reference voltage offset value. The present invention integrates multi-dimensional noise and noise coupling when constructing a reference voltage adjustment model, and uses the optimal reference voltage to establish a reference voltage adjustment model, adopts model fitting of different orders and adds corresponding constraints, the present invention improves the accuracy of reference voltage adjustment, and is suitable for different types of flash memories.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and more specifically, to a 3D NAND flash memory reference voltage optimization adjustment method, system and medium. Background Art

[0002] 3D NAND flash memory technology is the mainstream storage technology in the Internet + Big Data era, with the characteristics of fast read and write speed and high storage density. The current 3D NAND flash memory stacking layer has reached 176 layers. With the continuous increase in storage density, the data stored in 3D NAND flash memory is more prone to errors, especially after multiple erasing, long-term storage and other noise influences, the storage reliability will be greatly affected.

[0003] Since 3D NAND flash memory will inevitably face external noise interference from PEC noise, Data Retention and Read Disturb, 3D NAND flash memory needs to adjust the reference voltage during use to reduce the occurrence of read errors and improve the reliability of 3D NAND flash memory. Figure 1 As shown, after the threshold voltage distribution is shifted, when the original read reference voltage is used to read data, the probability of the two states being misjudged will be greatly increased because the optimal decision point of the overlapping distribution (i.e., the intersection of the two distributions, which minimizes the integral interval of the misjudgment probability) is not selected.

[0004] The current 3D NAND flash controller uses passive adjustment for read reference voltage, that is, it will only shift the reference voltage when the error condition is so severe that the controller's error control code (ECC) cannot be successfully decoded. This method is often called Read Retry (RRT). Assuming that the threshold voltage shift is serious, a large number of RRT operations will cause the NAND flash memory to have a large read delay. The flow chart is as follows Figure 2 As shown, as long as the ECC decoding fails, the controller will request an RRT operation to positively or negatively bias the reference voltage until the ECC decoding succeeds.

[0005] In order to reduce the read latency of 3D NAND flash memory, the current read reference voltage adjustment strategy is increasingly using a dynamic adjustment method, that is, when the controller senses the presence of noise in the 3D NAND flash memory, it will spontaneously adjust the read reference voltage. This spontaneous adjustment method requires the controller to know prior information, that is, it is necessary to measure the changes in the threshold voltage channel of the actual 3D NAND flash memory under different noise conditions, calculate the optimal reference voltage (Vopt) under different noise conditions to obtain the offset value, and then apply it to the adjustment. This step often requires the actual measurement of the 3D NAND flash memory channel and modeling. The current mainstream dynamic adjustment method implementation flow chart is as follows Figure 3 shown.

[0006] The existing threshold voltage model only considers the parameters of PEC and Data Retention. The read reference voltage adjustment accuracy of 3D NAND flash memory is not enough, and it does not take into account the interference caused by external noise such as Read Disturb and internal noise such as Layer Variation. At the same time, most of the existing PEC and Data Retention adjustment models do not take into account the physical characteristics caused by the wear of 3D NAND flash memory by PEC, which causes the noise of Data Retention and Read Disturb to change accordingly, that is, the coupling of PEC noise with other noises. The current model only measures, fits, and calculates various noises separately, and rarely considers the situation of noise coupling. Current 3D NAND flash memory products have been widely used in Internet data server centers. These servers have trillions of data read requests every day. The 3D NAND flash memory threshold voltage model that only considers PEC and Data Retention has limited optimization capabilities for 3D NAND flash memory with heavy read requests. 3D NAND flash memory with heavy read requests will be subject to stronger Read Disturb interference. A 3D NAND flash memory threshold voltage model that considers Read Disturb is urgently needed in the design of 3D NAND flash memory controllers on the market. At the same time, the existing solutions do not consider the noise coupling of 3D NAND flash memory much, and the flash memory threshold voltage model considers a relatively single scenario, which is not accurate enough and needs to be further improved.

[0007] In addition, the existing models are based on the threshold voltage models of 3D FG NAND flash memory or 3D CT NAND flash memory. There are differences in the measurement and modeling processes of various solutions for different types of 3D NAND flash memory. There is no solution on the market that uses the same method to measure and model two types of 3D NAND flash memory. The adjustment method design of the controller of 3D NAND flash memory products on the actual market is not comprehensive enough.

[0008] The prior art discloses a method, system and 3D flash memory for adjusting the threshold voltage in a 3D flash memory, and relates to the field of flash memory data reading technology. The technical key points of the adjustment method include reserving a portion of storage elements in a flash memory block as verification storage elements; writing specified verification data on the verification storage elements; reading the verification data on the verification storage elements as read-out data; comparing the verification data with the read-out data to obtain a detection set of storage elements; selecting a problematic threshold voltage from seven threshold voltages based on the comparison detection set; and modifying the problematic threshold voltage based on the calculation detection set. This solution does not take into account multi-dimensional noise and noise coupling. Summary of the invention

[0009] The present invention provides a 3D NAND flash memory reference voltage optimization adjustment method, system and medium to overcome the defects of the above-mentioned existing 3D NAND flash memory reference voltage adjustment that does not fully consider noise, does not consider noise coupling, and cannot be applied to different types of flash memories.

[0010] The primary purpose of the present invention is to solve the above technical problems. The technical solution of the present invention is as follows:

[0011] A first aspect of the present invention provides a 3D NAND flash memory reference voltage optimization and adjustment method, comprising the following steps:

[0012] S1: Randomly select a NAND flash memory block and add PEC noise, Retention noise, and Read noise in sequence. Perform PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block after adding noise to obtain the corresponding optimal reference voltage.

[0013] S2: Establish a reference voltage adjustment model using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage;

[0014] S3: Calculate a reference voltage offset value using a reference voltage adjustment model, and read data from the NAND flash memory block using the reference voltage offset value.

[0015] Furthermore, the random selection of NAND flash memory blocks and the sequential addition of PEC noise, Retention noise, and Read noise are performed, and the PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection are performed on the NAND flash memory blocks after the noise is added to obtain the corresponding optimal reference voltage. The specific steps are as follows:

[0016] A NAND flash memory block is randomly selected and PEC noise and Retention noise are added in sequence to obtain a flash memory block which is recorded as a first flash memory block, and Read noise is added to the first flash memory block which is recorded as a second flash memory block;

[0017] Detecting the PEC-Ret threshold voltage count of the first flash memory block, fitting the PEC-Ret threshold voltage distribution using the PEC-Ret threshold voltage count, solving the intersection of adjacent storage states in the PEC-Ret threshold voltage distribution, and obtaining the PEC-Ret optimal reference voltage;

[0018] The PEC-Ret-Read threshold voltage count of the second flash memory block is detected, the PEC-Ret-Read threshold voltage distribution is fitted using the PEC-Ret-Read threshold voltage count, the intersection of adjacent storage states in the PEC-Ret-Read threshold voltage distribution is solved, and the PEC-Ret-Read optimal reference voltage is obtained.

[0019] Furthermore, the specific steps of establishing a reference voltage adjustment model using the PEC-Ret threshold voltage and the PEC-Ret-Read threshold voltage are as follows:

[0020] Input the PEC-Ret optimal reference voltage, PEC and Ret into the first mathematical model for fitting, and output coefficients a, b, c, f and i, where a is a constant, b represents the PEC noise coefficient, c represents the noise coefficient of the logarithm of the Data Retention time, f represents the coupling coefficient of the PEC and the logarithm of the Data Retention time, i represents the coupling coefficient of the PEC and the logarithm of the Data Retention time, the PEC represents the number of flash memory erases and Ret represents the Data Retetnion time;

[0021] Input the PEC-Ret-Read optimal reference voltage PEC, Read, and the known coefficient b and coefficient a about PEC into the second mathematical model for fitting, and output coefficients d and g, where d represents the Read Disturb noise coefficient, and g represents the PEC and Read Disturb noise coupling coefficient;

[0022] Input the PEC-Ret optimal reference voltage PEC, Layer, known coefficients about PEC and coefficient a into the third mathematical model for fitting, and output coefficients e and h, where e represents the Layer Variation noise coefficient, h represents the coupling coefficient of PEC and LayerVariation noise, and Layer represents the number of flash memory layers;

[0023] The obtained coefficient ai is input into the original mathematical model to obtain the final reference voltage regulation model.

[0024] Furthermore, the first mathematical model expression is:

[0025] V opt1 =a+b*PEC+c*logR et.+f*PEClog Ret+i*log 2 Ret

[0026] Among them, V opt1 It is the optimal reference voltage under PEC-Retention noise.

[0027] Furthermore, the second mathematical model expression is:

[0028] V opt2 =a+b*PEC+d*Read+g*PEC*Read

[0029] Among them, V opt2 It is the optimal reference voltage under PEC-Read noise

[0030] Furthermore, the third mathematical model expression is:

[0031] V opt3 =a+b*PEC+e*Layer+h*PEC*Layer

[0032] Among them, V opt3 It is the optimal reference voltage under PEC-Layer noise

[0033] Furthermore, the mathematical expression of the original model is:

[0034] V opt =a+b*PEC+c*logRet.+d*Read+e*Layer+f*PEC*logRet.+g*PEC*Read+h*PEC*Layer+i*log 2 Ret

[0035] Among them, V opt It is the optimal reference voltage under PEC-Retention-Read-Layer noise.

[0036] A second aspect of the present invention provides a 3D NAND flash memory reference voltage optimization and adjustment system, the system comprising: a memory, a processor, the memory comprising a 3D NAND flash memory reference voltage optimization and adjustment method program, the 3D NAND flash memory reference voltage optimization and adjustment method program being executed by the processor to implement the following steps:

[0037] S1: Randomly select a NAND flash memory block and add PEC noise, Retention noise, and Read noise in sequence. Perform PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block after adding noise to obtain the corresponding optimal reference voltage.

[0038] S2: Establish a reference voltage adjustment model using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage;

[0039] S3: Calculate a reference voltage offset value using a reference voltage adjustment model, read data from the NAND flash memory block using the reference voltage offset value and the default reference voltage respectively, and compare bit error rates of the two data reading methods.

[0040] Furthermore, the random selection of NAND flash memory blocks and the sequential addition of PEC noise, Retention noise, and Read noise are performed, and the PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection are performed on the NAND flash memory blocks after the noise is added to obtain the corresponding optimal reference voltage. The specific steps are as follows:

[0041] A NAND flash memory block is randomly selected and PEC noise and Retention noise are added in sequence to obtain a flash memory block which is recorded as a first flash memory block, and Read noise is added to the first flash memory block which is recorded as a second flash memory block;

[0042] Detecting the PEC-Ret threshold voltage count of the first flash memory block, fitting the PEC-Ret threshold voltage distribution using the PEC-Ret threshold voltage count, solving the intersection of adjacent storage states in the PEC-Ret threshold voltage distribution, and obtaining the PEC-Ret optimal reference voltage;

[0043] The PEC-Ret-Read threshold voltage count of the second flash memory block is detected, the PEC-Ret-Read threshold voltage distribution is fitted using the PEC-Ret-Read threshold voltage count, the intersection of adjacent storage states in the PEC-Ret-Read threshold voltage distribution is solved, and the PEC-Ret-Read optimal reference voltage is obtained.

[0044] A third aspect of the present invention provides a computer-readable storage medium, which includes a 3D NAND flash memory reference voltage optimization adjustment method program. When the 3D NAND flash memory reference voltage optimization adjustment method program is executed by a processor, the steps of the 3D NAND flash memory reference voltage optimization adjustment method are implemented.

[0045] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0046] The present invention integrates multi-dimensional noise and noise coupling when constructing a reference voltage regulation model. At the same time, when establishing the reference voltage regulation model using the optimal reference voltage, models of different orders are used for fitting and corresponding constraints are added. The present invention improves the accuracy of reference voltage regulation and is suitable for different types of flash memories. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Schematic diagram of two offset conditions of threshold voltage distribution of 3D NAND flash memory in the prior art.

[0048] Figure 2 The flowchart is a 3D NAND flash memory reference voltage adjustment strategy in the prior art.

[0049] Figure 3 A flow chart for dynamically adjusting the read reference voltage is provided.

[0050] Figure 4 This is a flow chart of a 3D NAND flash memory reference voltage optimization and adjustment method of the present invention.

[0051] Figure 5 This is a block diagram of the 3D NAND flash memory reference voltage optimization and adjustment system of the present invention.

[0052] Figure 6 This is a comparison chart of the data read error rates of two different types of 3D NAND flash memories in an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0054] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0055] Glossary:

[0056] PEC noise: During flash memory threshold voltage channel modeling, the voltage changes due to multiple PEC errors.

[0057] Retention noise: In flash memory threshold voltage channel modeling, the noise caused by voltage changes due to long-term data retention errors.

[0058] Read noise: In flash memory threshold voltage channel modeling, the noise caused by voltage changes due to read disturbance errors caused by multiple reads.

[0059] PEC-Ret threshold voltage detection: During the flash memory threshold voltage channel modeling process, the PEC error after multiple erases and the Data Retention error caused by long-term storage cause coupling noise.

[0060] PEC-Ret-Read threshold voltage detection: During the flash memory threshold voltage channel modeling process, the PEC error after multiple erases, the Data Retention error caused by long-term storage, and the Read Disturb error caused by multiple reads all combine to cause coupling noise.

[0061] Example 1

[0062] like Figure 4 As shown, the first aspect of the present invention provides a 3D NAND flash memory reference voltage optimization and adjustment method, comprising the following steps:

[0063] S1: Randomly select a NAND flash memory block and add PEC noise, Retention noise, and Read noise in sequence. Perform PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block after adding noise to obtain the corresponding optimal reference voltage.

[0064] S2: Establish a reference voltage adjustment model using the PEC-Re optimal reference voltage and the PEC-Ret-Read optimal reference voltage;

[0065] S3: Calculate a reference voltage offset value using a reference voltage adjustment model, and read data from the NAND flash memory block using the reference voltage offset value.

[0066] It should be noted that, in the present invention, noise is first added to a randomly selected NAND flash memory block, and then the PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection are performed on the NAND flash memory block with added noise to obtain threshold voltage counting points, and then Gaussian fitting is performed using the threshold voltage counting points to obtain a discrete distribution of the 3D NAND flash memory threshold voltage, and the intersection of adjacent storage states in the discrete distribution is solved to obtain the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage, and a reference voltage adjustment model is established using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage; finally, the reference voltage adjustment model is used to calculate the reference voltage offset value, and the reference voltage offset value is used to read data from the NAND flash memory block.

[0067] Furthermore, the random selection of NAND flash memory blocks and sequential addition of PEC noise, Retention noise, and Read noise, and the PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection are performed on the NAND flash memory blocks after the noise is added. The specific steps are as follows:

[0068] A NAND flash memory block is randomly selected and PEC noise and Retention noise are added in sequence to obtain a flash memory block which is recorded as a first flash memory block, and Read noise is added to the first flash memory block which is recorded as a second flash memory block;

[0069] Detecting the PEC-Ret threshold voltage count of the first flash memory block, fitting the PEC-Ret threshold voltage distribution using the PEC-Ret threshold voltage count, solving the intersection of adjacent storage states in the PEC-Ret threshold voltage distribution, and obtaining the PEC-Ret optimal reference voltage;

[0070] The PEC-Ret-Read threshold voltage count of the second flash memory block is detected, the PEC-Ret-Read threshold voltage distribution is fitted using the PEC-Ret-Read threshold voltage count, the intersection of adjacent storage states in the PEC-Ret-Read threshold voltage distribution is solved, and the PEC-Ret-Read optimal reference voltage is obtained.

[0071] It should be noted that, in a specific embodiment, the threshold voltage detection can be performed by using the reference voltage offset method, that is, reading the count points of the 3D NAND flash memory storage state under each offset, thereby obtaining a discrete distribution of the 3D NAND flash memory threshold voltage. First, the storage state count is read using the default reference voltage of each state, and then the reference voltage is set to offset in the positive direction, and the storage state count in the state is read. The count point of the state is calculated to be different from the count of the previous state, and the storage state count value falling in the interval can be obtained. In the specific implementation process, the flash memory block obtained by adding PEC noise and Retention noise is recorded as the first flash memory block, and the first flash memory block with Read noise is recorded as the second flash memory block;

[0072] The reference voltage offset method is used to count the PEC-Ret threshold voltage of the first flash memory block, and the PEC-Ret threshold voltage count is used for Gaussian fitting to obtain the PEC-Ret threshold voltage distribution, and the intersection of adjacent storage states in the PEC-Ret threshold voltage distribution is solved, and the horizontal coordinate corresponding to the intersection is the PEC-Ret optimal reference voltage;

[0073] The reference voltage offset method PEC-Ret-Read threshold voltage count is used for the second flash memory block, and Gaussian fitting is performed using the PEC-Ret-Read threshold voltage count to obtain the PEC-Ret-Read threshold voltage distribution. The intersection of adjacent storage states in the PEC-Ret-Read threshold voltage distribution is solved, and the horizontal coordinate of the intersection is the PEC-Ret-Read optimal reference voltage.

[0074] Furthermore, the specific steps of establishing a reference voltage adjustment model using the PEC-Ret threshold voltage and the PEC-Ret-Read threshold voltage are as follows:

[0075] Input the PEC-Ret optimal reference voltage, PEC and Ret into the first mathematical model for fitting, and output coefficients a, b, c, f and i, where a is a constant, b represents the PEC noise coefficient, c represents the noise coefficient of the logarithm of the Data Retention time, f represents the coupling coefficient of the PEC and the logarithm of the Data Retention time, i represents the coupling coefficient of the PEC and the logarithm of the Data Retention time, the PEC represents the number of flash memory erases and Ret represents the Data Retetnion time;

[0076] Input the PEC-Ret-Read optimal reference voltage PEC, Read, and the known coefficient b and coefficient a about PEC into the second mathematical model for fitting, and output coefficients d and g, where d represents the Read Disturb noise coefficient, and g represents the PEC and Read Disturb noise coupling coefficient;

[0077] The PEC-Ret optimal reference voltage PEC, Layer, known coefficients about PEC and coefficient a are input into the third mathematical model for fitting, and coefficients e and h are output, where e represents the Layer Variation noise coefficient, h represents the coupling coefficient of PEC and LayerVariation noise, and Layer represents the number of flash memory layers.

[0078] The obtained coefficient ai is input into the original mathematical model to obtain the final reference voltage regulation model.

[0079] Furthermore, the first mathematical model expression is:

[0080] V opt1 =a+b*PEC+c*logRet.+f*PEC*logRet.+i*log 2 Ret

[0081] Among them, V opt1 It is the optimal reference voltage under PEC-Retention noise.

[0082] Furthermore, the second mathematical model expression is:

[0083] V opt2 =a+b*PEC+d*Read+g*PEC*Read

[0084] Among them, V opt2 It is the optimal reference voltage under PEC-Read noise.

[0085] Furthermore, the third mathematical model expression is:

[0086] V opt3 =a+b*PEC+e*Layer+h*PEC*Layer

[0087] Among them, V opt3 It is the optimal reference voltage under PEC-Layer noise.

[0088] Furthermore, the mathematical expression of the original model is:

[0089] V opt =a+b*PEC+c*logRet.+d*Read+e*Layer+f*PEC*logRet.+g*PEC*Read+h*PEC*Layer+i*log 2 Ret

[0090] Among them, V opt It is the optimal reference voltage under PEC-Retention-Read-Layer noise.

[0091] It should be noted that the reference voltage regulation model proposed in the present invention is a model about multidimensional parameters. The model is established by fitting the actual measured value. At the same time, due to the complexity of multidimensional model fitting, distribution fitting can be used in model establishment, that is, first fitting the noise with a large influence, and then bringing the parameter into a constrained model to obtain the parameter, and then fitting the noise with a smaller influence. The mathematical representation of the original model proposed in the present invention obtains the value of each coefficient by step-by-step fitting.

[0092] First, the PEC-Ret optimal reference voltage Vopt (i.e., the optimal reference voltage obtained under PEC-Retention noise), PEC, and Ret are input into the first mathematical model for fitting, wherein the parameters in the model that are not related to PEC and Data Retention are all set to 0, and only the noise and coupling of PEC and Data Retention are considered. The fitting expression is:

[0093] V opt1 =a+b*PEC+c*log Ret.+f*PEClog Ret+i*log 2 Ret

[0094] The output coefficients are a, b, c, f and i. It should be noted that the above model is a linear regression model of PEC first order and Ret. second order. By selecting the second order model, compared with the traditional first order model, it can better fit the Early Loss phenomenon existing in today's 3D NAND flash memory.

[0095] The PEC-Ret-Read optimal reference voltage (the optimal reference voltage obtained under PEC-Retention-Read noise), PEC, Read, known coefficients about PEC and coefficient a are input into the second mathematical model for fitting. It should be noted that this fitting only considers the noise and coupling of PEC and Read. At this time, the model fitting selects the fixed data of Retention, so the coefficient about Ret is set to 0 at this time, and the fitting expression is:

[0096] V opt2 =a+b PEC+d *Read+g*PEC*Read

[0097] Output coefficients d and g, Read represents Read noise. It should be noted that the second mathematical model is a linear regression model of PEC first order and Read first order.

[0098] The PEC-Ret optimal reference voltage Vopt (i.e., the optimal reference voltage obtained under PEC-Retention noise), PEC, Layer, known coefficients about PEC, and coefficient a are input into the third mathematical model for fitting. Only the noise and coupling of PEC and Layer are considered. Since the model fitting at this time selects the fixed data of Retention, the coefficient about Ret. is set to 0 at this time. The fitting expression is:

[0099] V opt3 =a+b*PEC+e*Layer+h*PEC*Layer

[0100] Among them, the output coefficients e and h, it should be noted that the third mathematical model is a linear regression model of the first order of PEC and the first order of Layer.

[0101] The coefficients a to i obtained are input into the original mathematical model to obtain the final reference voltage regulation model. The fitting of this model takes into account the order of noise influence, first fitting the noise combination with the greatest influence, and then bringing in the next group of noise combinations for constrained fitting after obtaining the correlation coefficient, which improves the accuracy of the model.

[0102] Example 2

[0103] A second aspect of the present invention provides a 3D NAND flash memory reference voltage optimization and adjustment system, such as Figure 5 As shown, the system includes: a memory and a processor, wherein the memory includes a 3D NAND flash memory reference voltage optimization adjustment method program, and the 3D NAND flash memory reference voltage optimization adjustment method program is executed by the processor to implement the following steps:

[0104] S1: Randomly select a NAND flash memory block and add PEC noise, Retention noise, and Read noise in sequence. Perform PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block after adding noise to obtain the corresponding optimal reference voltage.

[0105] S2: Establish a reference voltage adjustment model using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage;

[0106] S3: Calculate a reference voltage offset value using a reference voltage adjustment model, and read data from the NAND flash memory block using the reference voltage offset value.

[0107] Furthermore, the random selection of NAND flash memory blocks and the sequential addition of PEC noise, Retention noise, and Read noise are performed, and the PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection are performed on the NAND flash memory blocks after the noise is added to obtain the corresponding optimal reference voltage. The specific steps are as follows:

[0108] A NAND flash memory block is randomly selected and PEC noise and Retention noise are added in sequence to obtain a flash memory block which is recorded as a first flash memory block, and Read noise is added to the first flash memory block which is recorded as a second flash memory block;

[0109] Detecting the PEC-Ret threshold voltage count of the first flash memory block, fitting the PEC-Ret threshold voltage distribution using the PEC-Ret threshold voltage count, solving the intersection of adjacent storage states in the PEC-Ret threshold voltage distribution, and obtaining the PEC-Ret optimal reference voltage;

[0110] The PEC-Ret-Read threshold voltage count of the second flash memory block is detected, the PEC-Ret-Read threshold voltage distribution is fitted using the PEC-Ret-Read threshold voltage count, the intersection of adjacent storage states in the PEC-Ret-Read threshold voltage distribution is solved, and the PEC-Ret-Read optimal reference voltage is obtained.

[0111] Example 3

[0112] A third aspect of the present invention provides a computer-readable storage medium, which includes a 3D NAND flash memory reference voltage optimization adjustment method program. When the 3D NAND flash memory reference voltage optimization adjustment method program is executed by a processor, the steps of the 3D NAND flash memory reference voltage optimization adjustment method are implemented.

[0113] Verification and analysis

[0114] This embodiment randomly reselects 3D NAND flash memory blocks, adds noise to the flash memory blocks, applies the optimal reference voltage and the default reference voltage to read data, compares the bit error rates of the two, and verifies that the optimal reference voltage calculated by the model improves the reliability of the 3D NAND flash memory. Since the current reference voltage of 3D NAND flash memory only supports block adjustment, and the trend of the inter-layer difference of the raw bit error rate (RBER) of 3D NAND flash memory is relatively linear, the Layer parameter of the equation will take the median of the 3D NAND flash memory storage into the calculation. The present invention uses a 64-layer 3D NAND flash memory, and the median is 32. The optimal reference voltage model reduces the raw bit error rate of 3D FG TLC NAND flash memory by 20% on average, and reduces the raw bit error rate of 3D CTTLC NAND flash memory by 30% on average, such as Figure 6 As shown, it is verified that the model of the present invention is effective. Figure 6 In the figure, the left side shows the comparison of the data error rate of 3D FG TLC NAND flash memory using the method of the present invention and using the default voltage for reading data, and the right side shows the comparison of the data error rate of 3D CT TLC NAND flash memory using the method of the present invention and using the default voltage for reading data.

[0115] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A 3D NAND flash memory reference voltage optimization and adjustment method, characterized in that: The following steps are involved: S1: Randomly select a NAND flash memory block and add PEC noise, Retention noise, and Read noise in sequence. Perform PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block after adding noise to obtain the corresponding optimal reference voltage. The specific steps are as follows: A NAND flash memory block is randomly selected and PEC noise and Retention noise are added in sequence to obtain a flash memory block which is recorded as a first flash memory block, and Read noise is added to the first flash memory block which is recorded as a second flash memory block; Detecting the PEC-Ret threshold voltage count of the first flash memory block, fitting the PEC-Ret threshold voltage distribution using the PEC-Ret threshold voltage count, solving the intersection of adjacent storage states in the PEC-Ret threshold voltage distribution, and obtaining the PEC-Ret optimal reference voltage; Detecting the PEC-Ret-Read threshold voltage count of the second flash memory block, fitting the PEC-Ret-Read threshold voltage distribution using the PEC-Ret-Read threshold voltage count, solving the intersection of adjacent storage states in the PEC-Ret-Read threshold voltage distribution, and obtaining the PEC-Ret-Read optimal reference voltage; S2: Use the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage to establish a reference voltage adjustment model. The specific steps are: The PEC-Ret optimal reference voltage, PEC and Ret are input into the first mathematical model for fitting, and the coefficients a, b, c, f and i are output. The expression of the first mathematical model is: V opt1 =a+b*PEC+c*logRet.+f*PEC*logRet+i*log 2 Ret Among them, V opt1 is the optimal reference voltage under PEC-Retention noise, a is a constant, b represents the PEC noise coefficient, c represents the noise coefficient of the logarithm of the Data Retention duration, f represents the coupling coefficient of the noise of the logarithm of the PEC and the Data Retention duration, i represents the coupling coefficient of the noise of the logarithm of the PEC and the Data Retention duration, PEC represents the number of flash memory erases and writes, and Ret represents the Data Retetnion duration; The PEC-Ret-Read optimal reference voltage, PEC, Read, known coefficients b and a about PEC are input into the second mathematical model for fitting, and coefficients d and g are output. The expression of the second mathematical model is: V opt2 =a+b*PEC+d*Read+g*PEC*Read Among them, V opt2 is the optimal reference voltage under PEC-Read noise, d represents the Read Disturb noise coefficient, and g represents the coupling coefficient of PEC and Read Disturb noise; The PEC-Ret optimal reference voltage, PEC, Layer, known coefficients b and a about PEC are input into the third mathematical model for fitting, and coefficients e and h are output. The expression of the third mathematical model is: V opt3 =a+b*PEC+e*Layer+h*PEC*Layer Among them, V opt3 is the optimal reference voltage under PEC-Layer noise, e represents the Layer Variation noise coefficient, h represents the coupling coefficient of PEC and Layer Variation noise, and Layer represents the number of flash memory layers; The coefficient ai is input into the original mathematical model to obtain the final reference voltage regulation model. The original mathematical model expression is: V opt =a+b*PEC+c*logRet+d*Read+e*Layer+f*PEC*logRet+g*PEC*Read+h*PEC*Layer+i*log 2 Ret Among them, V opt It is the optimal reference voltage under PEC-Retention-Read-Layer noise; S3: Calculate a reference voltage offset value using a reference voltage adjustment model, and read data from the NAND flash memory block using the reference voltage offset value.

2. A 3D NAND flash memory reference voltage optimization and adjustment system, characterized in that: The system includes: a memory and a processor, wherein the memory includes a 3D NAND flash memory reference voltage optimization adjustment method program, and when the 3D NAND flash memory reference voltage optimization adjustment method program is executed by the processor, the following steps are implemented: S1: Randomly select a NAND flash memory block and add PEC noise, Retention noise, and Read noise in sequence. Perform PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block after adding noise to obtain the corresponding optimal reference voltage. The specific steps are as follows: A NAND flash memory block is randomly selected and PEC noise and Retention noise are added in sequence to obtain a flash memory block which is recorded as a first flash memory block, and Read noise is added to the first flash memory block which is recorded as a second flash memory block; Detecting the PEC-Ret threshold voltage count of the first flash memory block, fitting the PEC-Ret threshold voltage distribution using the PEC-Ret threshold voltage count, solving the intersection of adjacent storage states in the PEC-Ret threshold voltage distribution, and obtaining the PEC-Ret optimal reference voltage; Detecting the PEC-Ret-Read threshold voltage count of the second flash memory block, fitting the PEC-Ret-Read threshold voltage distribution using the PEC-Ret-Read threshold voltage count, solving the intersection of adjacent storage states in the PEC-Ret-Read threshold voltage distribution, and obtaining the PEC-Ret-Read optimal reference voltage; S2: Use the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage to establish a reference voltage adjustment model. The specific steps are: The PEC-Ret optimal reference voltage, PEC and Ret are input into the first mathematical model for fitting, and the coefficients a, b, c, f and i are output. The expression of the first mathematical model is: V opt1 =a+b*PEC+c*logRet.+f*PEC*logRet+i*log 2 Ret Among them, V opt1 is the optimal reference voltage under PEC-Retention noise, a is a constant, b represents the PEC noise coefficient, c represents the noise coefficient of the logarithm of the Data Retention duration, f represents the coupling coefficient of the noise of the logarithm of the PEC and the Data Retention duration, i represents the coupling coefficient of the noise of the logarithm of the PEC and the Data Retention duration, PEC represents the number of flash memory erases and writes, and Ret represents the Data Retetnion duration; The PEC-Ret-Read optimal reference voltage, PEC, Read, known coefficients b and a about PEC are input into the second mathematical model for fitting, and coefficients d and g are output. The expression of the second mathematical model is: V opt2 =a+b*PEC+d*Read+g*PEC*Read Among them, V opt2 is the optimal reference voltage under PEC-Read noise, d represents the Read Disturb noise coefficient, and g represents the coupling coefficient of PEC and Read Disturb noise; The PEC-Ret optimal reference voltage, PEC, Layer, known coefficients b and a about PEC are input into the third mathematical model for fitting, and coefficients e and h are output. The expression of the third mathematical model is: V opt3 =a+b*PEC+e*Layer+h*PEC*Layer Among them, V opt3 is the optimal reference voltage under PEC-Layer noise, e represents the Layer Variation noise coefficient, h represents the coupling coefficient of PEC and Layer Variation noise, and Layer represents the number of flash memory layers; The coefficient ai is input into the original mathematical model to obtain the final reference voltage regulation model. The original mathematical model expression is: V opt =a+b*PEC+c*logRet+d*Read+e*Layer+f*PEC*logRet+g*PEC*Read+h*PEC*Layer+i*log 2 Ret Among them, V opt It is the optimal reference voltage under PEC-Retention-Read-Layer noise; S3: Calculate a reference voltage offset value using a reference voltage adjustment model, and read data from the NAND flash memory block using the reference voltage offset value.

3. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a 3D NAND flash memory reference voltage optimization adjustment method program. When the 3D NAND flash memory reference voltage optimization adjustment method program is executed by a processor, the steps of the 3D NAND flash memory reference voltage optimization adjustment method as claimed in claim 1 are implemented.

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