Ultrasonic wire bonding machine, semiconductor device packaging method and structure

Abstract

The present invention provides an ultrasonic wire bonding machine, a semiconductor device packaging method and a structure. The packaging method includes the steps of: placing a first chip and a second chip parallel to each other with a certain distance therebetween, and making the first solder joint of the first chip correspond to the second solder joint of the second chip vertically; placing a metal lead wire with a preset length in the lead channels at both ends of the ultrasonic wire bonding machine, and vertically placing it between the first chip and the second chip; ultrasonically bonding the two ends of the metal lead wire to the first solder joint of the first chip and the second solder joint of the second chip respectively. In the present invention, the chips are designed in a layout with the upper and lower opposite, and the metal lead wire is ultrasonically bonded in a direction perpendicular to the chip surface. Through such a design, even in the case of thermal stress generated by temperature change, there will be no shear stress in the cross-section direction of the lead wire, and it is not easy to generate fractures near the lead wire bonding position, which can effectively avoid the fatigue failure of the lead wire caused by repeated thermal stress, and contribute to improving the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and particularly to an ultrasonic wire bonding machine, a semiconductor device packaging method and a structure. Background Art

[0002] Wire bonding is a packaging technology that uses fine metal wires and utilizes heat, pressure, and ultrasonic energy to tightly bond the metal leads to the substrate pads, realizing electrical interconnection between the chip and the substrate and information communication between chips. Under ideal control conditions, electron sharing or atomic interdiffusion occurs between the lead and the substrate, thereby achieving atomic-level bonding between the two metals.

[0003] The existing wire bonding process is usually as follows: Two chips are placed at intervals on the same horizontal plane. First, the first end of the wire is welded to the wire bonding point A of the first chip 11, and then the end of the wire bonding machine pulls the wire to move to the second chip 12 and bonds with the solder joint of the second chip 12 through bonding. After that, the wedge cuts the wire to obtain the structure as shown in Figure 1 However, when the packaged chip is in use, the temperature usually rises, resulting in thermal deformation of part of the wire at the wire bonding point A. With the repeated temperature changes of the power chip, the wire deforms repeatedly between a and b as shown in Figure 2 Finally, the wire fatigue failure occurs, resulting in the fracture at the position indicated by the arrow as shown in Figure 3 leading to a decline in device performance or even complete failure. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an ultrasonic wire bonding machine, a semiconductor device packaging method and a structure, which are used to solve the problems in the prior art that when chips are placed at intervals on the same horizontal plane for wire bonding, when the packaged chip is in use, thermal deformation will occur at the wire bonding point due to temperature rise, and repeated temperature changes will ultimately lead to wire fatigue failure, resulting in a decline in device performance or even complete failure.

[0005] To achieve the above purpose and other related purposes, the present invention provides an ultrasonic wire bonding machine, which includes two oppositely arranged ends, and wire channels are vertically arranged corresponding to each other inside the two ends.

[0006] The present invention also provides a semiconductor device packaging method, including the steps of:

[0007] Placing the first chip and the second chip parallel to each other at intervals up and down, and making the first solder joint of the first chip and the second solder joint of the second chip correspond up and down;

[0008] Place a metal lead with a preset length into the lead channels at both ends of the ultrasonic wire bonding machine described in any of the above solutions, and place it vertically between the first chip and the second chip;

[0009] Ultrasonically bond both ends of the metal lead to the first solder joint of the first chip and the second solder joint of the second chip respectively.

[0010] Optionally, before ultrasonic bonding, it further includes the step of heating and softening the first solder joint and the second solder joint simultaneously, and the heating temperature is 200°C - 230°C.

[0011] Optionally, during the ultrasonic bonding process, the ultrasonic frequency is 100KHZ - 120KHZ, the force applied during bonding is 0.6N - 1.2N, and the ultrasonic bonding time is 200ms - 250ms.

[0012] Optionally, the metal lead includes one or more of gold wire, copper wire, and aluminum wire.

[0013] Optionally, after completing the ultrasonic bonding, it further includes the step of forming a protective layer on the surfaces of the first solder joint and the second solder joint.

[0014] More optionally, the protective layer includes any one of an anti-oxidation metal layer and a resin material layer.

[0015] Optionally, the preset length is 0.15mm - 2mm larger than the vertical distance between the first solder joint and the second solder joint.

[0016] The present invention also provides a semiconductor device packaging structure, which is prepared by using the semiconductor device packaging method described in any of the above solutions. The semiconductor device packaging structure includes a first chip and a second chip arranged parallel and spaced apart up and down. The first solder joint of the first chip and the second solder joint of the second chip are connected by a vertical metal lead.

[0017] Optionally, the semiconductor device packaging structure further includes a packaging shell, and the packaging shell covers the first chip and the second chip.

[0018] As described above, the ultrasonic wire bonding machine, the semiconductor device packaging method and structure of the present invention have the following beneficial effects:

[0019] In the present invention, the chips to be bonded are designed in an up-and-down relative layout, and the metal leads are ultrasonically bonded in a direction perpendicular to the chip surface. Through such a design, even in the case of thermal stress generated by temperature changes, there will be no shear stress in the cross-section direction of the leads, and it is not easy to generate fractures near the lead bonding points, which can effectively avoid fatigue failure of the leads caused by repeated thermal stress, and help improve the device reliability. Description of the Drawings

[0020] Figure 1 It is shown as a schematic structural diagram obtained by using the existing wire bonding technology.

[0021] Figure 2 It is shown as a schematic diagram of the deformation generated at the bonding position of the structure obtained by using the existing wire bonding technology.

[0022] Figure 3 It is shown as an electron microscope image of the wire breakage caused by the deformation of the structure encapsulated by using the existing wire bonding technology.

[0023] Figure 4 It is shown as a partial schematic diagram of the ultrasonic wire bonding machine provided by the present invention.

[0024] Figure 5 It is shown as a schematic diagram of the encapsulation process of the semiconductor device encapsulation method provided by the present invention.

[0025] Figure 6 It is shown as a schematic diagram of the semiconductor device encapsulation structure obtained by the semiconductor device encapsulation method according to the present invention.

[0026] Description of component labels

[0027] 21 First end

[0028] 22 Second end

[0029] 23 Metal lead

[0030] 24 First chip

[0031] 25 Second chip Detailed implementation manners

[0032] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0033] For convenience of description, spatial relation terms such as "under", "below", "lower than", "beneath", "above", "on" may be used herein to describe the relationship of one element or feature shown in the drawings with other elements or features. It will be understood that these spatial relation terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0034] In the context of the present application, the structure in which the first feature described is "above" the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0035] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex. To make the illustrations as concise as possible, not all structures are labeled in each drawing.

[0036] In traditional wire bonding methods, the chips to be bonded are placed on the same horizontal plane, then the wires are bonded to the surfaces of the chips, and then the wires are cut. In the process of using the chips encapsulated by this method, the wires will deform due to repeated temperature changes, and finally the wires will break, resulting in deterioration of device performance or even complete failure. In response to this, the inventors of the present application have proposed an improvement solution after long-term research.

[0037] To achieve the object of the present invention, as Figure 4As shown in the figure, the present invention first proposes an ultrasonic bonding wire bonder. The ultrasonic bonding wire bonder includes two end heads arranged opposite to each other, that is, the bonding surfaces (the surfaces in contact with the solder joints) of the two end heads are facing away from each other and are respectively facing different solder joints. For the convenience of description, in this specification, the two end heads are respectively defined as the first end head 21 and the second end head 22 ("first" and "second" are only for convenience of description and do not have substantial limiting meanings). Vertical lead channels corresponding to each other are provided in the two end heads. During use, the lead wire passes through the lead channels of the first end head 21 and the second end head 22 and is exposed on the surfaces of the two end heads. After moving to the corresponding positions, the first end head 21 and the second end head 22 successively contact the solder joints and generate friction with the solder joints through the bonding energy and ultrasonic vibration, so as to bond the lead wire to the solder joints of the chip. The first end head 21 and the second end head 22 can also be called ultrasonic vibration heads, that is, the energy provided by ultrasonic waves is used to make different materials (the lead wire and the solder joints of the chip) diffuse and fuse with each other. The difference between the ultrasonic bonding wire bonder provided in this embodiment and the existing ultrasonic bonding wire bonder is that the existing ultrasonic bonding wire bonder only has a single end head, while the ultrasonic bonding wire bonder provided in this embodiment has two end heads arranged opposite to each other. Therefore, the two ends of the lead wire can be vertically bonded to two chips arranged parallel and spaced apart up and down. Except for this difference, the other structures of the ultrasonic bonding wire bonder provided in this embodiment are basically the same as those in the prior art. Since the present invention does not involve the modification of other structures except the end heads, no detailed expansion will be made here.

[0038] As Figure 5 shown, the present invention also provides a semiconductor device packaging method, including the steps:

[0039] Place the first chip 24 and the second chip 25 parallel and spaced apart up and down, and make the first solder joint of the first chip 24 and the second solder joint of the second chip 25 correspond up and down; the first chip 24 and the second chip 25 can be any type of chip, and the packaging method of the present invention is particularly suitable for the packaging of power chips, and can well solve the problems such as lead wire deformation and even fracture caused by heat generation during the use of power chips. Therefore, the first chip 24 and the second chip 25 can be power chips. The number of the first chip 24 and the second chip 25 is not limited to one, and the number of the first solder joint and the second solder joint is not limited to one. The important thing is to place the chips to be bonded parallel and spaced apart up and down and make the solder joints to be bonded correspond up and down;

[0040] Place a metal lead 23 with a preset length in the lead channels at both ends of the ultrasonic wire bonder described in any of the above solutions, and ensure that the metal lead 23 protrudes from the surface of the ends (i.e., both ends of the metal lead 23 protrude from the ends), and place it vertically between the first chip 24 and the second chip 25; the preset length is slightly greater than the vertical distance between the first solder joint and the second solder joint. For example, the preset length is 0.15 mm - 2 mm greater than the vertical distance between the first solder joint and the second solder joint.

[0041] Ultrasonically bond the two ends of the metal lead 23 to the first solder joint of the first chip 24 and the second solder joint of the second chip 25 respectively. For example, one end of the metal lead 23 can be ultrasonically bonded to the first solder joint of the first chip 24 first, and then the other end of the metal lead 23 can be ultrasonically bonded to the second solder joint of the second chip 25, or vice versa.

[0042] In the present invention, the chips to be bonded are designed in an up-and-down relative layout, and the metal leads are ultrasonically bonded in a direction perpendicular to the chip surface. Through such a design, even in the case of thermal stress generated by temperature changes, there will be no shear stress in the cross-sectional direction of the leads, and fractures are not likely to occur near the lead bonding points, which can effectively avoid fatigue failure of the leads caused by repeated thermal stress, and help improve the reliability of the device.

[0043] To achieve a better bonding effect, in a preferred example, before ultrasonic bonding, it further includes the step of heating and softening the first solder joint and the second solder joint simultaneously. The heating process can be carried out in the ultrasonic bonding chamber. For example, after placing the first chip 24 and the second chip 25 parallel and spaced apart on the fixed substrate in the ultrasonic bonding chamber, introduce an inert gas such as nitrogen into the ultrasonic bonding chamber. Nitrogen can simultaneously play a role in cleaning and can be used as a protective gas during the ultrasonic bonding process to prevent oxidation of the solder pads and leads. Of course, in other examples, the solder joints can also be heated by heating the substrate for fixing the chips, and the ultrasonic bonding process can also be carried out under high vacuum, and no strict restrictions are imposed on this.

[0044] Since the chips are vertically spaced, the relevant process parameters of ultrasonic bonding need to be carefully designed to avoid adverse effects on the chips as much as possible. The inventor found through a large number of experiments that preferably, during the ultrasonic bonding process, the ultrasonic frequency is 100 KHZ - 120 KHZ, the force applied during bonding is 0.6 N - 1.2 N, and the ultrasonic bonding time is preferably 200 ms - 250 ms. For example, during the ultrasonic bonding process, the ultrasonic frequency is 100 KHZ, the force applied during bonding is 0.7 N, and the ultrasonic bonding time is 200 ms.

[0045] The semiconductor device packaging method provided in this embodiment is applicable to ultrasonic bonding of various leads, especially applicable to the bonding of gold wires, copper wires, and aluminum wires. The metal lead 23 can be a single metal, such as a gold wire, a copper wire, or an aluminum wire, or can simultaneously include the bonding of gold wires, copper wires, and aluminum wires.

[0046] After completing the ultrasonic bonding, in order to protect the bonding area, a protective layer (not shown) can also be formed on the surfaces of the first solder joint and the second solder joint. For example, an oxygen-free copper layer, a nickel layer, or other metal layers that can prevent oxidation of the bonding area can be formed. It can also be a non-metal layer such as a silica gel layer, an epoxy resin layer, and a polyimide layer. It can also simultaneously include these two material layers. For example, a protective layer of a non-metal material is formed on the surface of the anti-oxidation metal layer. Or an insulating material layer such as a polyimide layer or an epoxy resin layer can be formed in the circumferential direction of the entire metal lead 23 or between the first chip 24 and the second chip 25 as a protective layer.

[0047] After completing the lead bonding, usually the next step of packaging is also required. For example, the bonded first chip 24 and second chip 25 are packaged in a plastic packaging case.

[0048] As Figure 6 shown, the present invention also provides a semiconductor device packaging structure. The semiconductor device packaging structure is prepared by using the semiconductor device packaging method described in any of the above solutions. The semiconductor device packaging structure includes a first chip 24 and a second chip 25 that are arranged parallel and spaced apart up and down. The first solder joint of the first chip 24 and the second solder joint of the second chip 25 are connected by a vertical metal lead 23. And the semiconductor device packaging structure can also include a packaging case, and the packaging case covers the first chip 24 and the second chip 25.

[0049] For more introduction to the semiconductor device packaging structure, please refer to the foregoing content. For the sake of brevity, it will not be elaborated. In the semiconductor device packaging structure provided by the present invention, since the chips are vertically spaced and bonded and connected by vertical metal leads, the shear stress in the cross-sectional direction of the leads can be avoided in the case of thermal stress generated by temperature changes. It is not easy to generate fractures near the lead bonding area, and the fatigue failure of the leads caused by repeated thermal stress can be effectively avoided, which helps to improve the reliability of the device.

[0050] In summary, the present invention provides an ultrasonic wire bonding machine, a semiconductor device packaging method and a structure. The semiconductor device packaging method includes the steps of: placing a first chip and a second chip parallel to each other with a certain distance therebetween, and making the first solder joint of the first chip correspond to the second solder joint of the second chip vertically; placing a metal lead with a preset length in the lead channels at both ends of the ultrasonic wire bonding machine described in any of the above solutions, and vertically placing it between the first chip and the second chip; ultrasonically bonding both ends of the metal lead to the first solder joint of the first chip and the second solder joint of the second chip respectively. In the present invention, the chips to be bonded are designed in a layout where they face each other up and down, and the metal lead is ultrasonically bonded in a direction perpendicular to the chip surface. Through such a design, even in the case of thermal stress generated by temperature change, there will be no shear stress in the cross-sectional direction of the lead, and it is not easy for fractures to occur near the lead bonding point, which can effectively avoid the fatigue failure of the lead caused by repeated thermal stress, and help improve the device reliability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0051] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device packaging method, characterized in that: Including steps: Place the first chip and the second chip in parallel and spaced apart, with the first solder joint of the first chip and the second solder joint of the second chip corresponding to each other; A metal wire of a preset length is placed in the wire channels of the two ends of an ultrasonic bonding machine and vertically placed between the first chip and the second chip. The ultrasonic bonding machine includes two ends arranged opposite to each other, and the two ends are provided with corresponding wire channels vertically above and below. Two ends of the metal lead with a preset length are ultrasonically and vertically bonded to a first solder joint of the first chip and a second solder joint of the second chip in a direction perpendicular to the surfaces of the first chip and the second chip respectively.

2. The semiconductor device packaging method according to claim 1, wherein: Before ultrasonic bonding, the method further includes heating and softening the first solder joint and the second solder joint at the same time, with the heating temperature being 200° C. to 230° C.

3. The semiconductor device packaging method according to claim 1, wherein: During the ultrasonic bonding process, the ultrasonic frequency is 100KHZ-120KHZ, the force applied during bonding is 0.6N-1.2N, and the ultrasonic bonding time is 200ms-250ms.

4. The semiconductor device packaging method according to claim 1, wherein The metal lead wire includes one or more of a gold wire, a copper wire and an aluminum wire.

5. The semiconductor device packaging method according to claim 1, wherein After the ultrasonic bonding is completed, the method further includes forming a protective layer on the surfaces of the first welding spot and the second welding spot.

6. The semiconductor device packaging method according to claim 5, wherein, The protective layer includes any one of an anti-oxidation metal layer and a resin material layer.

7. The semiconductor device packaging method according to claim 1, wherein: The preset length is 0.15 mm to 2 mm greater than the vertical distance between the first welding point and the second welding point.

8. A semiconductor device packaging structure, characterized in that, The semiconductor device packaging structure is prepared using the semiconductor device packaging method described in any one of claims 1 to 7, and the semiconductor device packaging structure includes a first chip and a second chip arranged in parallel and spaced apart from each other, and the first solder point of the first chip and the second solder point of the second chip are connected by vertical metal leads.

9. The semiconductor device package structure according to claim 8, wherein, The semiconductor device packaging structure further includes a packaging shell, which covers the first chip and the second chip.

10. An ultrasonic bonding machine, characterized in that: The ultrasonic bonding machine is used to perform the semiconductor device packaging method according to any one of claims 1 to 7. The ultrasonic bonding machine includes two end heads arranged opposite to each other, and the two end heads are provided with corresponding lead channels vertically arranged in the upper and lower directions.

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