A method for forming a semiconductor structure and a method for fabricating a CMOS device

Abstract

This application discloses a method for forming a semiconductor structure and a method for fabricating a CMOS device. The method for forming the semiconductor structure includes: providing a substrate comprising a high-voltage device region and a low-voltage device region; the high-voltage device region comprising an isolation structure formed within the substrate, and a gate oxide layer and a mask layer formed on the substrate; the low-voltage device region comprising an isolation structure formed within the substrate, and a pad oxide layer and a mask layer formed on the substrate; forming a protective layer on the mask layer of the high-voltage device region; the protective layer comprising a polysilicon layer and a dielectric layer; etching back a portion of the isolation structure of the low-voltage device region using a Cetas etching process; and removing the protective layer of the high-voltage device region. The method provided in this application, by forming a protective layer on the high-voltage device region, avoids damage to the mask layer and gate oxide layer of the high-voltage device region when etching back the isolation structure of the low-voltage device region using a Cetas etching process, thereby ensuring the quality of the gate oxide layer of the high-voltage device region.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure and a method for fabricating a CMOS device. Background Technology

[0002] As the feature size of semiconductor integrated circuit devices continues to shrink, the thickness of the gate oxide layer also decreases proportionally. In semiconductor structures, it is often necessary to integrate devices with different operating voltages. High-voltage complementary metal-oxide-semiconductor (CMOS) devices have thicker gate oxide layers, while low-voltage CMOS devices have thinner gate oxide layers.

[0003] The gate oxide layer is a crucial structure in semiconductor devices; defects in the gate oxide layer can reduce the reliability of the semiconductor device. Therefore, improving the quality of the gate oxide layer in semiconductor devices is a pressing issue that needs to be addressed. Summary of the Invention

[0004] This application provides a method for forming a semiconductor structure and a method for fabricating a CMOS device.

[0005] In a first aspect, embodiments of this application provide a method for forming a semiconductor structure, the method comprising:

[0006] A substrate is provided that includes a high-voltage device region and a low-voltage device region; the high-voltage device region includes an isolation structure formed within the substrate, and a gate oxide layer and a mask layer formed on the substrate; the low-voltage device region includes an isolation structure formed within the substrate, and a pad oxide layer and a mask layer formed on the substrate.

[0007] A protective layer is formed on the mask layer in the high-voltage device region; the protective layer includes a polysilicon layer and a dielectric layer.

[0008] The isolation structure of the low-voltage device region was etched back using the Certas etching process.

[0009] Remove the protective layer from the high-voltage device area.

[0010] According to one embodiment of this application, the dielectric layer includes a silicon oxide layer and / or a silicon nitride layer.

[0011] According to one embodiment of this application, before re-etching the isolation structure of the low-voltage device region using the Certas etching process, the method further includes:

[0012] Remove the pad oxide layer and the mask layer from the low-voltage device region.

[0013] According to one embodiment of this application, forming a protective layer on the mask layer in the high-voltage device region includes:

[0014] A protective layer is formed on the mask layer;

[0015] A patterned photoresist layer is formed on the protective layer, and the patterned photoresist layer exposes the low-voltage device region;

[0016] The protective layer of the low-voltage device region is removed by etching through the patterned photoresist layer.

[0017] According to one embodiment of this application, the method of using Certas etching process to etch back and remove a portion of the isolation structure of the low-voltage device region includes:

[0018] The isolation structure of the low-voltage device region is etched back using the Certas etching process, and the dielectric layer of the high-voltage device region is removed.

[0019] According to one embodiment of this application, removing the protective layer of the high-voltage device region includes:

[0020] The polysilicon layer in the high-voltage device region is removed by etching gas;

[0021] The selectivity of the etching gas for the polycrystalline silicon layer is greater than the selectivity of the etching gas for the substrate.

[0022] According to one embodiment of this application, the etching gas includes hydrogen chloride gas.

[0023] According to one embodiment of this application, the selection ratio of the polycrystalline silicon layer to the substrate is greater than 20:1.

[0024] According to one embodiment of this application, after removing the protective layer of the high-voltage device region, the method further includes:

[0025] Remove the mask layer from the high-voltage device region to expose the gate oxide layer.

[0026] According to one embodiment of this application, the method further includes:

[0027] CMOS devices are formed in the high-voltage device region and the low-voltage device region, respectively.

[0028] According to one embodiment of this application, the low-voltage device region includes a first low-voltage device region and a second low-voltage device region; wherein the operating voltage of the CMOS device formed in the first low-voltage device region is higher than the operating voltage of the CMOS device formed in the second low-voltage device region.

[0029] Secondly, embodiments of this application provide a method for fabricating a CMOS device, including a method for forming a semiconductor structure as described in the first aspect of this application.

[0030] This application provides a method for forming a semiconductor structure and a method for fabricating a CMOS device. The method for forming the semiconductor structure includes: providing a substrate comprising a high-voltage device region and a low-voltage device region; the high-voltage device region comprising an isolation structure formed within the substrate, and a gate oxide layer and a mask layer formed on the substrate; the low-voltage device region comprising an isolation structure formed within the substrate, and a pad oxide layer and a mask layer formed on the substrate; forming a protective layer on the mask layer of the high-voltage device region; the protective layer comprising a polysilicon layer and a dielectric layer; etching back a portion of the isolation structure of the low-voltage device region using a Cetas etching process; and removing the protective layer of the high-voltage device region. The semiconductor structure formation method provided in this application avoids damage to the mask layer and gate oxide layer of the high-voltage device region when etching back a portion of the isolation structure of the low-voltage device region using a Cetas etching process by forming a protective layer on the mask layer of the high-voltage device region, thereby ensuring the quality of the gate oxide layer of the high-voltage device region. Attached Figure Description

[0031] Figures 1 to 10 This is a simplified cross-sectional schematic diagram of the semiconductor structure provided in an embodiment of this application;

[0032] Figure 11 This is an electron microscope image of the gate oxide layer in the relevant technical solution;

[0033] Figure 12 A flowchart illustrating a method for forming a semiconductor structure provided in this application embodiment;

[0034] The figure includes: 100 - substrate; 101a - first active region; 102a - second active region; 103a - third active region; 200 - low-voltage device region; 201 - first low-voltage device region; 202 - second low-voltage device region; 300 - high-voltage device region; 400 - isolation trench; 500 - isolation structure; 601 - gate oxide layer; 601a - upper surface of gate oxide layer; 602 - pad oxide layer; 602a - upper surface of pad oxide layer; 700 - mask layer; 800 - protective layer; 801 - polysilicon layer; 802 - dielectric layer; 900 - patterned photoresist layer. Detailed Implementation

[0035] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0042] As the feature size of semiconductor integrated circuit devices continues to shrink, the thickness of the gate oxide layer also decreases proportionally. In semiconductor structures, it is often necessary to integrate devices with different operating voltages; high-voltage CMOS devices require thicker gate oxide layers, while low-voltage CMOS devices require thinner gate oxide layers.

[0043] Figures 1 to 10 A simplified cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application is shown.

[0044] like Figure 1 As shown, a substrate 100 is provided, including a high-voltage device region 300 and a low-voltage device region 200. The substrate can be a single-element semiconductor material substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.; it can also be a composite semiconductor material substrate, such as a silicon-germanium substrate, etc.; or it can be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0045] Continue to refer to Figure 1 The substrate 100 includes a high-voltage device region 300 and a low-voltage device region 200. The operating voltage of the CMOS device formed in the high-voltage device region 300 is higher than that of the CMOS device formed in the low-voltage device region 200. For example, the operating voltage of the CMOS device formed in the high-voltage (HV) device region is greater than 10V, and the operating voltage of the CMOS device formed in the low-voltage (LV) device region is less than 10V.

[0046] Still referencing Figure 1 The low-voltage device region 200 may include a first low-voltage device region 201 and a second low-voltage device region 202, wherein the operating voltage of the CMOS device formed in the first low-voltage device region 201 is higher than the operating voltage of the CMOS device formed in the second low-voltage device region 202. For example, the operating voltages of the CMOS devices formed in both the first and second low-voltage device regions are less than 10V. Specifically, the operating voltage range of the CMOS device formed in the first low-voltage region can be 3–10V, and the operating voltage range of the CMOS device formed in the second low-voltage region can be 1–3V. In this case, the second low-voltage device region is also referred to as a low-low voltage (LLV) device region.

[0047] like Figure 1 As shown, a gate oxide layer 601 is formed on the substrate 100 corresponding to the high-voltage device region 300, and a pad oxide layer 602 is formed on the substrate 100 corresponding to the low-voltage device region 200. The upper surface 601a of the gate oxide layer is higher than the upper surface 602a of the pad oxide layer. The gate oxide (GOX) material can be, for example, silicon oxide. The gate oxide layer in the high-voltage device region has a larger thickness; specifically, the thickness of the gate oxide layer can even be greater than 1000 angstroms. For example, the thickness of the gate oxide layer corresponding to the high-voltage device region can be 1200 angstroms. The pad oxide layer material can also be, for example, silicon oxide. The thickness of the pad oxide layer corresponding to the low-voltage device region is smaller than that of the gate oxide layer. Specifically, the thickness of the pad oxide layer can range from 50 to 200 angstroms; for example, the thickness of the pad oxide layer in the low-voltage device region can be 150 angstroms. The pad oxide layer can serve as a transition and buffer layer between the subsequently formed mask layer and the substrate, protecting the active regions between the isolation structures from contamination during the etching process.

[0048] Still referencing Figure 1A mask layer 700 is formed on the gate oxide layer 601 and the pad oxide layer 602. After the mask layer 700 is formed, a chemical mechanical polishing (CMP) process can be used to planarize the surface of the mask layer 700. Figure 1 The mask layer 700 shown is the planarized mask layer 700. At this point, the thickness of the mask layer located in the high-voltage device region differs from the thickness of the mask layer located in the low-voltage device region; more specifically, the thickness of the mask layer located in the high-voltage device region is less than the thickness of the mask layer located in the low-voltage device region. The material of the mask layer can be, for example, silicon nitride. Here, silicon nitride, as the material of the mask layer, can both protect the active regions between the isolation structures and act as a polishing barrier material during subsequent polishing. The material of the mask layer can also be, for example, silicon oxynitride.

[0049] To form the aforementioned gate oxide layer, pad oxide layer, and mask layer, one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, can be used.

[0050] Subsequently, a photoresist layer can be coated on the surface of the mask layer. Figure 1 (Not shown) and perform photolithography processes such as exposure and development to form a photoresist pattern with openings that defines the location of the isolation trenches.

[0051] like Figure 2 As shown, an opening in the photoresist layer is used to etch a mask layer to form a mask layer with openings that define the location of isolation trenches. After removing the photoresist layer, the pad oxide layer 602 and the substrate 100 are etched through the mask layer 700 with openings to form an isolation trench 400 in the low-voltage device region 200. The gate oxide layer 601 and the substrate 100 are also etched through the mask layer 700 with openings to form an isolation trench 400 in the high-voltage device region 300. Alternatively, a plasma etching process can be used to etch the mask layer through the opening in the photoresist layer to form an open mask layer. Then, a fluorine-containing etching gas is used to etch the pad oxide layer and the substrate through the open mask layer, and the gate oxide layer and the substrate are also etched through the open mask layer to form the isolation trench.

[0052] Still referencing Figure 2 An oxide layer can be formed on the sidewalls and bottom of the isolation trench 400, respectively. Figure 2(Not shown). The oxide layer can be 150 angstroms thick and can be used to improve the interface properties between the substrate and the filling material of the isolation trench.

[0053] like Figure 3 As shown, isolation material is filled into the isolation trench 400 to form an isolation structure 500. The isolation material can be silicon oxide. Figure 3 Only three isolation structures are shown, located in the first low-voltage device region, the second low-voltage device region, and the high-voltage device region, respectively. These isolation structures are shallow trench isolation (STI).

[0054] like Figure 4 As shown, the CMP process can be used to planarize the upper surface of the isolation structure and expose the upper surface of the mask layer, that is, the upper surface of the isolation structure is flush with the upper surface of the mask layer.

[0055] like Figure 4 As shown, the area between the isolation structures is defined as the active area (AA), still referring to... Figure 4 The active region includes a first active region 101a, a second active region 102a, and a third active region 103a. The first active region 101a is located within the first low-voltage device region; the second active region 102a is located within the second low-voltage device region; and the third active region 103a is located within the high-voltage device region. The first active region 101a, the second active region 102a, and the third active region 103a are divided based on the device region in which the active region is located.

[0056] In the above technical solution, it is necessary to further etch back the isolation structure of the low-voltage device area. The plasma during the etch-back process can damage the mask layer of the high-voltage device area and the gate oxide layer located below the mask layer. The plasma during the etch-back process can even create holes in the mask layer and gate oxide layer of the high-voltage device area, thereby affecting the breakdown voltage of the gate oxide layer.

[0057] refer to Figure 11 , Figure 11 This is an electron microscope image of the gate oxide layer in the relevant technical solution. For example... Figure 11 As shown, the gate oxide layer in the high-voltage device region is damaged during the etch-back process; specifically, the gate oxide layer develops punch defects.

[0058] Understandably, the gate oxide layer is a crucial structure in semiconductor devices. Defects such as voids in the gate oxide layer can reduce the reliability of the semiconductor device. Therefore, improving the quality of the gate oxide layer in semiconductor devices is a pressing issue that needs to be addressed.

[0059] In view of this, embodiments of this application provide a method for forming a semiconductor structure. Figure 12 A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application is shown, such as... Figure 12 As shown, the method for forming the semiconductor structure includes:

[0060] S1201, A substrate is provided that includes a high-voltage device region and a low-voltage device region; the high-voltage device region includes an isolation structure formed in the substrate, and a gate oxide layer and a mask layer formed on the substrate; the low-voltage device region includes an isolation structure formed in the substrate, and a pad oxide layer and a mask layer formed on the substrate.

[0061] like Figure 5 As shown, the substrate 100 includes a high-voltage device region 300 and a low-voltage device region 200. The high-voltage device region 300 includes an isolation structure 500 formed within the substrate 100, and the high-voltage device region 300 may include a gate oxide layer 601 and a mask layer 700 sequentially formed on the substrate 100. The low-voltage device region 200 includes an isolation structure 500 formed within the substrate 100, and the low-voltage device region 200 may include a pad oxide layer 602 and a mask layer 700 sequentially formed on the substrate 100.

[0062] In some embodiments of this application, CMOS devices are formed in the high-voltage device region and the low-voltage device region, respectively. The operating voltage of the CMOS device formed in the high-voltage device region is higher than that of the CMOS device formed in the low-voltage device region.

[0063] In some embodiments of this application, the surface of the gate oxide layer is higher than the surface of the pad oxide layer. Specifically, the thickness of the gate oxide layer located in the high-voltage device region is greater than the thickness of the pad oxide layer located in the low-voltage device region.

[0064] In some embodiments of this application, the low-voltage device region includes a first low-voltage device region and a second low-voltage device region; wherein the operating voltage of the CMOS device formed in the first low-voltage device region is higher than the operating voltage of the CMOS device formed in the second low-voltage device region.

[0065] Still referencing Figure 5 The low-voltage device region 200 includes a first low-voltage device region 201 and a second low-voltage device region 202; wherein the operating voltage of the CMOS device formed in the first low-voltage device region 201 is higher than the operating voltage of the CMOS device formed in the second low-voltage device region 202.

[0066] S1202, A protective layer is formed on the mask layer in the high-voltage device region; the protective layer includes a polysilicon layer and a dielectric layer.

[0067] In some embodiments of this application, forming a protective layer on the mask layer in the high-voltage device region includes: forming a protective layer on the mask layer; forming a patterned photoresist layer on the protective layer, the patterned photoresist layer exposing the low-voltage device region; and etching through the patterned photoresist layer to remove the protective layer in the low-voltage device region.

[0068] Continue to refer to Figure 5 A protective layer 800 is formed on the substrate 100, which completely covers the mask layer 700 and the upper surface of the isolation structure 500. A patterned photoresist layer 900 is formed on the protective layer 800, which exposes the low-voltage device region 200. The patterned photoresist layer 900 is etched to remove the protective layer 800 located above the low-voltage device region 200.

[0069] Further reference Figure 6 , Figure 6 The protective layer 800 shown only covers the mask layer 700 and the upper surface of the isolation structure 500 located above the high-voltage device area 300.

[0070] In some embodiments of this application, the protective layer includes a polysilicon layer and a dielectric layer.

[0071] Still referencing Figure 5 A polysilicon film 801 is first formed on the upper surface of the mask layer 700 and the isolation structure 500 as a cap layer. Then, a dielectric layer 802 is formed on the polysilicon film 801. A patterned photoresist layer 900 is formed on the dielectric layer 802, which exposes the low-voltage device region 200. The patterned photoresist layer 900 is etched to remove the dielectric layer 802 and the polysilicon film 801 located above the low-voltage device region 200.

[0072] To form the polysilicon layer and dielectric layer in the above-mentioned protective layer, one or more thin film deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof, can be used.

[0073] In some embodiments of this application, the dielectric layer includes a silicon oxide layer and / or a silicon nitride layer. The dielectric layer may be a silicon oxide layer, and for example, its thickness may be 80 angstroms.

[0074] In some embodiments of this application, the method for forming the semiconductor structure further includes: removing the pad oxide layer and the mask layer from the low-voltage device region.

[0075] like Figure 7As shown, the pad oxide layer and mask layer located above the low-voltage device region 200 are removed, specifically including the removal of the mask layer located above the first low-voltage device region 201 and the mask layer located above the second low-voltage device region 202, to expose part of the sidewalls of the isolation structure 500 located in the first low-voltage device region 201 and the second low-voltage device region 202. At this time, the upper surface of the isolation structure 500 is higher than the upper surface of the substrate 100.

[0076] S1203. The isolation structure of the low-voltage device area is etched back using the Certas etching process.

[0077] In some embodiments of this application, the step of using the Certas etching process to etch back and remove a portion of the isolation structure of the low-voltage device region includes:

[0078] The isolation structure of the low-voltage device region is etched back using the Certas etching process, and the dielectric layer of the high-voltage device region is removed.

[0079] like Figure 8 As shown, the Certas etching process can be used to etch back the isolation structure 500 of the low-voltage device region 200 and remove the dielectric layer in the protective layer above the high-voltage device region. At this time, the upper surface of the isolation structure 500 is lower than the upper surface of the substrate 100, so the upper surface of the isolation structure 500 and the upper surface of the substrate 100 form a recess region.

[0080] Specifically, the etching process uses a Certas (chemical gas etching) machine, which can use the Certas dry etching process to etch the isolation structure of the low-voltage device area in the semiconductor structure. A first inlet pipe and a second inlet pipe are respectively provided on both sides of the reaction chamber of the machine. Ammonia (NH3) and hydrogen fluoride (HF) gases are introduced into the reaction chamber of the machine through the first and second inlet pipes, respectively, to form plasma for etching the isolation structure.

[0081] S1204. Remove the protective layer from the high-voltage device area.

[0082] In some embodiments of this application, removing the protective layer from the high-voltage device region includes:

[0083] The polysilicon layer in the high-voltage device region is removed by etching gas;

[0084] The selectivity of the etching gas for the polycrystalline silicon layer is greater than the selectivity of the etching gas for the substrate.

[0085] like Figure 9As shown, the polysilicon layer of the high-voltage device region 300 can be removed by etching gas. Since the material selectivity of the etching gas for the polysilicon layer is greater than that for the substrate, the etching gas can remove only the polysilicon layer without causing much damage to the substrate exposed in the low-voltage device region.

[0086] In some embodiments of this application, the selection ratio of the polysilicon layer to the substrate is greater than 20:1.

[0087] As shown in Table 1, the etching gas can be, for example, hydrogen chloride (HCl) gas. At a temperature of 660°C, the etching rate of polycrystalline silicon material by hydrogen chloride gas is 45 Å / min, while the etching rate of substrate material, such as epitaxial silicon, by hydrogen chloride gas is 2.1 Å / min. Based on this analysis, the selection ratio of hydrogen chloride for etching polycrystalline silicon to epitaxial silicon is 21.4.

[0088] Table 1. Etching selectivity of etching gases for polysilicon and epitaxial silicon

[0089]

[0090] The semiconductor structure formation method provided in this application provides a protective layer comprising a polysilicon layer and a dielectric layer on a mask layer in the high-voltage device region. This prevents damage to the mask layer in the high-voltage device region and the gate oxide layer beneath the mask layer during the Certas process's back etching of the isolation structure in the low-voltage device region, thereby ensuring the quality of the gate oxide layer in the high-voltage device region. Furthermore, after the back etching process, a gas with a high selectivity for the polysilicon layer and substrate material, such as hydrogen chloride gas, can be used to remove the polysilicon layer without damaging the substrate material in the low-voltage device region.

[0091] In some embodiments of this application, after removing the protective layer of the high-voltage device region, the method further includes:

[0092] Remove the mask layer from the high-voltage device region to expose the gate oxide layer.

[0093] like Figure 10 As shown, the mask layer of the high-voltage device region is removed, and the material of the mask layer can be silicon nitride. In other words, the hard mask (HM) of the high-voltage device region is removed to expose the gate oxide layer 601 of the high-voltage device region.

[0094] This application also provides a method for fabricating a CMOS device, including the method for forming a semiconductor structure as described in the above technical solution.

[0095] This application provides a method for forming a semiconductor structure and a method for fabricating a CMOS device. The method for forming the semiconductor structure includes: providing a substrate comprising a high-voltage device region and a low-voltage device region; the high-voltage device region comprising an isolation structure formed within the substrate, and a gate oxide layer and a mask layer formed on the substrate; the low-voltage device region comprising an isolation structure formed within the substrate, and a pad oxide layer and a mask layer formed on the substrate; forming a protective layer on the mask layer of the high-voltage device region; the protective layer comprising a polysilicon layer and a dielectric layer; etching back a portion of the isolation structure of the low-voltage device region using a Cetas etching process; and removing the protective layer of the high-voltage device region. The semiconductor structure formation method provided in this application avoids damage to the mask layer of the high-voltage device region and the gate oxide layer below the mask layer when etching back a portion of the isolation structure of the low-voltage device region using a Cetas etching process, thereby ensuring the quality of the gate oxide layer of the high-voltage device region.

[0096] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0097] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided that includes a high-voltage device region and a low-voltage device region; the high-voltage device region includes an isolation structure formed within the substrate, and a gate oxide layer and a mask layer formed on the substrate; the low-voltage device region includes an isolation structure formed within the substrate, and a pad oxide layer and a mask layer formed on the substrate. A protective layer is formed on the mask layer in the high-voltage device region; the protective layer includes a polysilicon layer and a dielectric layer. The isolation structure of the low-voltage device region was etched back using the Certas etching process. Remove the protective layer of the high-voltage device region; wherein the surface of the isolation structure of the low-voltage device region is lower than the surface of the isolation structure of the high-voltage device region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dielectric layer includes a silicon oxide layer and / or a silicon nitride layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before the Certas etching process is used to etch back the isolation structure of the low-voltage device region, the method further includes: Remove the pad oxide layer and the mask layer from the low-voltage device region.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The formation of a protective layer on the mask layer in the high-voltage device region includes: A protective layer is formed on the mask layer; A patterned photoresist layer is formed on the protective layer, and the patterned photoresist layer exposes the low-voltage device region; The protective layer of the low-voltage device region is removed by etching through the patterned photoresist layer.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of using Certas etching process to etch back and remove part of the isolation structure of the low-voltage device region includes: The isolation structure of the low-voltage device region is etched back using the Certas etching process, and the dielectric layer of the high-voltage device region is removed.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, Removing the protective layer from the high-voltage device region includes: The polysilicon layer in the high-voltage device region is removed by etching gas; The selectivity of the etching gas for the polycrystalline silicon layer is greater than the selectivity of the etching gas for the substrate.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The etching gas includes hydrogen chloride gas.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The selection ratio of the polycrystalline silicon layer to the substrate is greater than 20:

1.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the protective layer from the high-voltage device region, the method further includes: Remove the mask layer from the high-voltage device region to expose the gate oxide layer.

10. The method for forming a semiconductor structure as described in claim 1 or 9, characterized in that, The method further includes: CMOS devices are formed in the high-voltage device region and the low-voltage device region, respectively.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The low-voltage device region includes a first low-voltage device region and a second low-voltage device region; wherein, the operating voltage of the CMOS device formed in the first low-voltage device region is higher than the operating voltage of the CMOS device formed in the second low-voltage device region.

12. A method for fabricating a CMOS device, comprising a method for forming a semiconductor structure as described in any one of claims 1 to 11.

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