Electrostatic protection structure and method for forming electrostatic protection structure

Abstract

An electrostatic protection structure and a method for forming the same. The structure includes: a substrate having a well region therein, the well region including adjacent first, second and third regions; a first gate structure and a second gate structure on a surface of the second region; a first doped region in the second region, the first doped region, the first gate structure and the second gate structure being electrically connected; a second doped region across the second region and the first region; a third doped region across the second region and the third region, the third doped region and the first doped region being on opposite sides of the second gate structure; a fourth doped region and a fifth doped region in the first region, the fourth doped region and the fifth doped region being electrically connected; a sixth doped region and a seventh doped region in the third region, the sixth doped region and the seventh doped region being electrically connected. The performance of the electrostatic protection structure is improved.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection devices, and more particularly to an ESD protection structure and a method for forming the ESD protection structure. Background Technology

[0002] In human life and manufacturing processes, the accumulation and release of electric charge occur constantly, a phenomenon known as static electricity. The moment of charge release, in particular, is extremely harmful to industrial manufacturing due to its short duration and large instantaneous current, especially in the advanced integrated circuit industry. As integrated circuits advance towards advanced processes, their gate oxide layer thickness is reduced to the nanometer scale, making them highly susceptible to damage during static discharge.

[0003] Conventional electrostatic discharge (ESD) protection devices, such as GGNMOS and GDPMOS, have relatively low robustness. To achieve a higher ESD protection level, the area of ​​the corresponding devices needs to be increased, which reduces their economic benefits and cannot meet the application requirements of bidirectional high clamping voltage. While conventional silicon controlled rectifier (SCR) devices have high robustness, their breakdown voltage is relatively high and their holding voltage is relatively low. They are ineffective in providing protection and are prone to inducing latch-up effects, leading to chip damage.

[0004] Therefore, there is a need to provide a high-performance electrostatic discharge protection device. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an electrostatic discharge protection structure and a method for forming the electrostatic discharge protection structure, so as to improve the performance of electrostatic discharge protection devices.

[0006] To solve the above technical problems, the present invention provides an electrostatic protection structure, comprising: a substrate having a well region therein, the well region including an adjacent first region, a second region, and a third region, the second region being located between the first and third regions, the first and third regions having the same conductivity type, and the first and second regions having opposite conductivity types; a first gate structure and a second gate structure located on the surface of the second region; a first doped region located within the second region, the first doped region being located between the first gate structure and the second gate structure, the first doped region containing a first ion, the first ion having the same conductivity type as the second region, the first doped region, the first gate structure, and the second gate structure being electrically connected; and a second doped region spanning the second region and the first region, the second doped region and the first doped region being located on opposite sides of the first gate structure, the second doped region containing a second ion, the second ion having the same conductivity type as the second region; and a second doped region spanning the second region and the first region, the second doped region being located on opposite sides of the first gate structure, the second doped region containing a second ion, the second ion having the same conductivity type as the second region. The electrical type is opposite to that of the first ion; a third doped region spanning the second and third regions, the third doped region and the first doped region being located on opposite sides of the second gate structure, the third doped region containing a third ion, the conductivity type of the third ion being opposite to that of the first ion; a fourth doped region and a fifth doped region located within the first region, the fourth doped region containing a fourth ion, the fifth doped region containing a fifth ion, the fourth ion having the same conductivity type as the first region, the fourth ion having the opposite conductivity type to the fifth ion, the fourth doped region and the fifth doped region being electrically connected; a sixth doped region and a seventh doped region located within the third region, the sixth doped region containing a sixth ion, the seventh doped region containing a seventh ion, the seventh ion having the same conductivity type as the fourth ion, the sixth ion having the opposite conductivity type to the seventh ion, the sixth doped region and the seventh doped region being electrically connected.

[0007] Optionally, it further includes: a first electrical connection structure located on the substrate, wherein the first doped region, the first gate structure, and the second gate structure are electrically connected through the first electrical connection structure; a second electrical connection structure located on the substrate, wherein the fourth doped region and the fifth doped region are electrically connected through the second electrical connection structure; and a third electrical connection structure located on the substrate, wherein the sixth doped region and the seventh doped region are electrically connected through the third electrical connection structure.

[0008] Optionally, it also includes: a third gate structure located on the first region, the third gate structure being adjacent to the fifth doped region; and a fourth gate structure located on the third region, the fourth gate structure being adjacent to the sixth doped region.

[0009] Optionally, the second electrical connection structure electrically connects the fourth doped region, the fifth doped region, and the third gate structure; the third electrical connection structure electrically connects the sixth doped region, the seventh doped region, and the fourth gate structure.

[0010] Optionally, it further includes: a third isolation structure located in the first region, wherein the third gate structure and the second doped region are located on both sides of the third isolation structure; and a fourth isolation structure located in the third region, wherein the fourth gate structure and the third doped region are located on both sides of the fourth isolation structure.

[0011] Optionally, the materials of the third and fourth isolation structures include silicon dioxide.

[0012] Optionally, the first gate structure includes a first gate oxide layer and a first gate layer located on the first gate oxide layer; the second gate structure includes a second gate oxide layer and a second gate layer located on the second gate oxide layer; the third gate structure includes a third gate oxide layer and a third gate layer located on the third gate oxide layer; and the fourth gate structure includes a fourth gate oxide layer and a fourth gate layer located on the fourth gate oxide layer.

[0013] Optionally, the materials of the first gate oxide layer, the second gate oxide layer, the third gate oxide layer, and the fourth gate oxide layer include silicon dioxide; the materials of the first gate layer, the second gate layer, the third gate layer, and the fourth gate layer include polysilicon.

[0014] Optionally, the first, fifth, and sixth ions may be of N-type conductivity, and the N-type ions may include phosphorus ions or arsenic ions; the second, third, fourth, and seventh ions may be of P-type conductivity, and the P-type ions may include boron ions.

[0015] Optionally, the conductivity type of the first and third regions includes P-type; the conductivity type of the second region includes N-type.

[0016] Optionally, the dopant ion concentrations in the first, fifth, and sixth dopant regions are the same; and the dopant ion concentrations in the second, third, fourth, and seventh dopant regions are the same.

[0017] Optionally, it also includes: a first isolation structure located within the first region, the first isolation structure being located between the fourth doped region and the fifth doped region; and a second isolation structure located within the third region, the second isolation structure being located between the sixth doped region and the seventh doped region.

[0018] Optionally, the materials of the first and second isolation structures include silicon dioxide.

[0019] Accordingly, the present invention also provides a method for forming an electrostatic protection structure, comprising: providing a substrate having a well region therein, the well region including an adjacent first region, a second region, and a third region, the second region being located between the first region and the third region, the first region and the third region having the same conductivity type, and the first region and the second region having opposite conductivity types; forming a first gate structure and a second gate structure on the surface of the second region; forming a first doped region within the second region, the first doped region being located between the first gate structure and the second gate structure, the first doped region containing a first ion, the first ion having the same conductivity type as the second region; forming a second doped region within the second region and within the first region, the second doped region and the first doped region being located on opposite sides of the first gate structure, the second doped region containing a second ion, the second ion having an opposite conductivity type to the first ion; forming a second doped region within the second region and within the first region, the second doped region and the first doped region being located on opposite sides of the first gate structure, the second doped region containing a second ion, the second ion having an opposite conductivity type to the first ion; forming a first gate structure and a second gate structure on the surface of the second region and the third region; forming a first doped region within the second region and within the third region; forming a first doped region within the second region and within the first region; forming a second doped region within the second region and within the first region; forming a second doped region within the second region and within the third region; forming a second doped region within the second region and within the first ... third region; forming a second doped region within the second region and within the first region; forming a second doped region within the second region A third doped region is formed within the first region, and the third doped region and the first doped region are located on opposite sides of the second gate structure, respectively. The third doped region contains a third ion, and the conductivity type of the third ion is opposite to that of the first ion. A fourth doped region and a fifth doped region are formed within the first region, and the fourth doped region contains a fourth ion, and the fifth doped region contains a fifth ion. The fourth ion has the same conductivity type as the first region, and the conductivity type of the fourth ion is opposite to that of the fifth ion. A sixth doped region and a seventh doped region are formed within the third region, and the sixth doped region contains a seventh ion. The seventh ion has the same conductivity type as the fourth ion, and the conductivity type of the sixth ion is opposite to that of the seventh ion. The first doped region, the first gate structure, and the second gate structure are electrically connected. The fourth doped region and the fifth doped region are electrically connected. The sixth doped region and the seventh doped region are electrically connected.

[0020] Optionally, the method of electrically connecting the first doped region, the first gate structure, and the second gate structure, electrically connecting the fourth and fifth doped regions, and electrically connecting the sixth and seventh doped regions includes: forming a first electrical connection structure, a second electrical connection structure, and a third electrical connection structure on a substrate, wherein the first electrical connection structure electrically connects the first doped region, the first gate structure, and the second gate structure, the second electrical connection structure electrically connects the fourth and fifth doped regions, and the third electrical connection structure electrically connects the sixth and seventh doped regions.

[0021] Optionally, while forming the first gate structure and the second gate structure on the surface of the second region, the method further includes: forming a third gate structure on the first region, wherein the fifth doped region is adjacent to the third gate structure; forming a fourth gate structure on the third region, wherein the sixth doped region is adjacent to the fourth gate structure; the second electrical connection structure electrically connects the fourth doped region, the fifth doped region and the third gate structure; and the third electrical connection structure electrically connects the sixth doped region, the seventh doped region and the fourth gate structure.

[0022] Optionally, before forming the fourth and fifth doped regions in the first region, the method further includes: forming a first isolation structure in the first region, wherein the fourth and fifth doped regions are located in the first region on both sides of the first isolation structure; and before forming the sixth and seventh doped regions in the third region, the method further includes: forming a second isolation structure in the third region, wherein the sixth and seventh doped regions are located in the third region on both sides of the second isolation structure.

[0023] Optionally, the second isolation structure and the first isolation structure are formed simultaneously; while forming the second isolation structure and the first isolation structure, the method further includes: forming a third isolation structure in the first region, wherein the third gate structure and the second doped region are respectively located on both sides of the third isolation structure; and forming a fourth isolation structure in the third region, wherein the fourth gate structure and the third doped region are respectively located on both sides of the fourth isolation structure.

[0024] Optionally, the formation process of the first doped region includes an ion implantation process; the formation process of the second doped region includes an ion implantation process; the formation process of the third doped region includes an ion implantation process; the formation process of the fourth doped region includes an ion implantation process; the formation process of the fifth doped region includes an ion implantation process; the formation process of the sixth doped region includes an ion implantation process; and the formation process of the seventh doped region includes an ion implantation process.

[0025] Optionally, the first, fifth, and sixth ions may be of N-type conductivity, and the N-type ions may include phosphorus ions or arsenic ions; the second, third, fourth, and seventh ions may be of P-type conductivity, and the P-type ions may include boron ions.

[0026] Optionally, the first doped region, the fifth doped region, and the sixth doped region are formed simultaneously; the second doped region, the third doped region, the fourth doped region, and the seventh doped region are formed simultaneously.

[0027] Optionally, the conductivity type of the first and third regions includes P-type; the conductivity type of the second region includes N-type.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The technical solution of this invention involves forming a first gate structure and a second gate structure on the surface of a second region, with the first doped region, the first gate structure, and the second gate structure electrically connected. On one hand, as the electrostatic voltage increases, the drift current in the first, second, and third regions increases. Due to the presence of parasitic resistance, the second region has a higher potential than the third region. The first gate structure and the second gate structure, electrically connected to the first doped region, are at the same potential, causing the negative charge in the second region to move upwards, resulting in the parasitic diode formed by the second doped region and the second region opening earlier to form the first channel for discharge current. As the electrostatic voltage further increases, the PNPN SCR structure formed by the fourth, first, second, second, third, third, and sixth doped regions opens, forming the main second channel for discharge current. The presence of the first channel reduces the emitter injection efficiency of the parasitic PNP and NPN, decreasing the positive feedback gain between PNP and NPN. The first gate structure and the second gate structure can improve the holding voltage and reduce the probability of latch-up. On the other hand, the first and third regions are symmetrical structures, thus allowing them to be interchanged to form a bidirectional structure.

[0030] Furthermore, a third gate structure is formed on the first region, and a fourth gate structure is formed on the third region. The second electrical connection structure electrically connects the fourth doped region, the fifth doped region, and the third gate structure. The third electrical connection structure electrically connects the sixth doped region, the seventh doped region, and the fourth gate structure. When forward electrostatic discharge occurs at the anode of either the second or third electrical connection structure, a downward-directed electric field is formed below the third gate structure. Under the action of the electric field, the positive charges in the first region flow into the device body, preventing charge congestion on the device surface, increasing the device's failure current, and improving robustness. Attached Figure Description

[0031] Figures 1 to 4 This is a cross-sectional structural schematic diagram of the formation process of the electrostatic protection structure in an embodiment of the present invention. Detailed Implementation

[0032] Figures 1 to 4 This is a cross-sectional structural schematic diagram of the formation process of the electrostatic protection structure in an embodiment of the present invention.

[0033] Please refer to Figure 1 A substrate is provided, the substrate having a well region comprising an adjacent first region 102, a second region 103 and a third region 104, the second region 103 being located between the first region 102 and the third region 104, the first region 102 and the third region 104 having the same conductivity type, and the first region 102 and the second region 103 having opposite conductivity types.

[0034] The conductivity type of the first region 102 includes N-type or P-type; the conductivity type of the second region 103 includes N-type or P-type; and the conductivity type of the third region 104 includes N-type or P-type.

[0035] In this embodiment, the conductivity type of the first region 102 and the third region 104 includes P-type, and the conductivity type of the second region 103 includes N-type.

[0036] In this embodiment, the substrate includes: a substrate 100, a buried layer 101 on the substrate 100, and a well region on the buried layer 101.

[0037] The conductivity type of the buried layer 101 is the same as that of the second region 103.

[0038] In this embodiment, the substrate is made of silicon.

[0039] Please refer to Figure 2 A first isolation structure 105 is formed in the first zone 102, and a second isolation structure 108 is formed in the third zone 104.

[0040] In this embodiment, the second isolation structure 108 and the first isolation structure 105 are formed simultaneously. Simultaneously with the formation of the second isolation structure 108 and the first isolation structure 105, the embodiment further includes: forming a third isolation structure 106 within the first region 102, the third isolation structure 106 being adjacent to the second region 103; and forming a fourth isolation structure 107 within the third region 104, the fourth isolation structure 107 being adjacent to the second region 103.

[0041] In this embodiment, the materials of the first isolation structure 105, the second isolation structure 108, the third isolation structure 106, and the fourth isolation structure 107 include silicon dioxide.

[0042] The method for forming the first isolation structure 105, the second isolation structure 108, the third isolation structure 106, and the fourth isolation structure 107 includes: forming a first groove (not shown) and a third groove (not shown) in a first region 102, and forming a second groove (not shown) and a fourth groove (not shown) in a third region 104; forming an isolation material layer (not shown) in the first groove, the third groove, the second groove, the fourth groove, and on the substrate; planarizing the isolation material layer until the substrate surface is exposed; forming the first isolation structure 105 in the first groove, forming the third isolation structure 106 in the third groove, forming the second isolation structure 108 in the second groove, and forming the fourth isolation structure 107 in the fourth groove.

[0043] Please continue to refer to this. Figure 2 A first gate structure and a second gate structure are formed on the surface of the second region 103.

[0044] In this embodiment, while forming the first gate structure and the second gate structure on the surface of the second region 103, the method further includes: forming a third gate structure on the first region 102, the third gate structure being located between the first isolation structure 105 and the third isolation structure 106; and forming a fourth gate structure on the third region 104, the fourth gate structure being located between the second isolation structure 108 and the fourth isolation structure 107.

[0045] The method for forming the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure includes: forming a gate oxide material layer (not shown) on a substrate; forming a gate material layer (not shown) on the gate oxide material layer; forming a patterned mask layer (not shown) on the gate material layer; etching the gate material layer and the gate oxide material layer using the patterned mask layer as a mask until the substrate surface is exposed; forming the first gate structure and the second gate structure on the surface of the second region 103; forming the third gate structure on the first region 102; and forming the fourth gate structure on the third region 104.

[0046] The first gate structure includes a first gate oxide layer 109 and a first gate layer 110 on the first gate oxide layer 109; the second gate structure includes a second gate oxide layer 111 and a second gate layer 112 on the second gate oxide layer 111; the third gate structure includes a third gate oxide layer 113 and a third gate layer 114 on the third gate oxide layer 113; the fourth gate structure includes a fourth gate oxide layer 115 and a fourth gate layer 116 on the fourth gate oxide layer 115.

[0047] In this embodiment, the material of the gate oxide layer includes silicon dioxide; the material of the gate material layer includes polysilicon.

[0048] In other embodiments, a third gate structure may not be formed on the first region; a fourth gate structure may not be formed on the third region.

[0049] Please refer to Figure 3 A first doped region 117 is formed in the second region 103. The first doped region 117 is located between the first gate structure and the second gate structure. The first doped region 117 contains a first ion, and the conductivity type of the first ion is the same as that of the second region 103.

[0050] The formation process of the first doped region 117 includes an ion implantation process.

[0051] In this embodiment, the conductivity type of the first ion includes N-type, and the N-type ion includes phosphorus ions or arsenic ions.

[0052] Please continue to refer to this. Figure 3A second doped region 118 is formed in the second region 103 and the first region 102. The second doped region 118 and the first doped region 117 are located on both sides of the first gate structure, respectively. The third gate structure and the second doped region 118 are located on both sides of the third isolation structure 106, respectively. The second doped region 118 contains a second ion, and the conductivity type of the second ion is opposite to that of the first ion.

[0053] The formation process of the second doped region 118 includes an ion implantation process.

[0054] In this embodiment, the conductivity type of the second ion includes P-type, and the P-type ion includes boron ions.

[0055] Please continue to refer to this. Figure 3 A third doped region 119 is formed in the second region 103 and the third region 104. The third doped region 119 and the first doped region 117 are located on both sides of the second gate structure, respectively. The fourth gate structure and the third doped region 119 are located on both sides of the fourth isolation structure 107, respectively. The third doped region 119 contains a third ion, and the conductivity type of the third ion is opposite to that of the first ion.

[0056] The formation process of the third doped region 119 includes an ion implantation process.

[0057] In this embodiment, the conductivity type of the third ion includes P-type, and the P-type ion includes boron ions.

[0058] Please continue to refer to this. Figure 3 A fourth doped region 120 and a fifth doped region 121 are formed within the first region 102. The fourth doped region 120 and the fifth doped region 121 are located within the first region 102 on both sides of the first isolation structure 105. The fourth doped region 120 contains a fourth ion, and the fifth doped region 121 contains a fifth ion. The fourth ion and the first region 102 have the same conductivity type, and the fourth ion and the fifth ion have opposite conductivity types.

[0059] The formation process of the fourth doped region 120 includes an ion implantation process; the formation process of the fifth doped region 121 includes an ion implantation process.

[0060] In this embodiment, the fifth doped region 121 and the third isolation structure 106 are located on both sides of the third gate structure, respectively.

[0061] In this embodiment, the fourth ion has a conductivity type including P-type, and the P-type ion includes boron ions; the fifth ion has a conductivity type including N-type, and the N-type ion includes phosphorus ions or arsenic ions.

[0062] Please continue to refer to this. Figure 3 A sixth doped region 122 and a seventh doped region 123 are formed in the third region 104. The sixth doped region 122 and the seventh doped region 123 are located in the third region 104 on both sides of the second isolation structure 108. The sixth doped region 122 contains a sixth ion, and the seventh doped region 123 contains a seventh ion. The seventh ion and the fourth ion have the same conductivity type, and the sixth ion and the seventh ion have opposite conductivity types.

[0063] The formation process of the sixth doped region 122 includes an ion implantation process; the formation process of the seventh doped region 123 includes an ion implantation process.

[0064] In this embodiment, the sixth doped region 122 and the fourth isolation structure 107 are located on both sides of the fourth gate structure, respectively.

[0065] In this embodiment, the seventh ion has a conductivity type including P-type, and the P-type ion includes boron ions; the sixth ion has a conductivity type including N-type, and the N-type ion includes phosphorus ions or arsenic ions.

[0066] In this embodiment, the first doped region 117, the fifth doped region 121, and the sixth doped region 122 are formed simultaneously, and the dopant ion concentrations of the first doped region 117, the fifth doped region 121, and the sixth doped region 122 are the same; the second doped region 118, the third doped region 119, the fourth doped region 120, and the seventh doped region 123 are formed simultaneously, and the dopant ion concentrations of the second doped region 118, the third doped region 119, the fourth doped region 120, and the seventh doped region 123 are the same.

[0067] In this embodiment, the breakdown voltage ranges of the first doped region 117, the fifth doped region 121, the sixth doped region 122, the second doped region 118, the third doped region 119, the fourth doped region 120, and the seventh doped region 123 are the same.

[0068] For example, in this embodiment, the operating voltage of the electrostatic protection device is 5 volts, and the breakdown voltage range of the first doped region 117, the fifth doped region 121, the sixth doped region 122, the second doped region 118, the third doped region 119, the fourth doped region 120 and the seventh doped region 123 is 10 volts to 13 volts.

[0069] Please refer to Figure 4 It is electrically connected to the first doped region 117, the first gate structure, and the second gate structure; electrically connected to the fourth doped region 120 and the fifth doped region 121; and electrically connected to the sixth doped region 122 and the seventh doped region 123.

[0070] In this embodiment, the first doped region 117, the first gate structure, and the second gate structure are electrically connected through a first electrical connection structure 124 located on the substrate, the fourth doped region 120 and the fifth doped region 121 are electrically connected through a second electrical connection structure 125 located on the substrate, and the sixth doped region 122 and the seventh doped region 123 are electrically connected through a third electrical connection structure 126 located on the substrate.

[0071] The method of electrically connecting the first doped region 117, the first gate structure, and the second gate structure, electrically connecting the fourth doped region 120 and the fifth doped region 121, and electrically connecting the sixth doped region 122 and the seventh doped region 123 includes: forming a dielectric structure (not shown) on a substrate; forming a first electrical connection structure 124, a second electrical connection structure 125, and a third electrical connection structure 126 within the dielectric structure; the first electrical connection structure 124 electrically connecting the first doped region 117, the first gate structure, and the second gate structure; the second electrical connection structure 125 electrically connecting the fourth doped region 120 and the fifth doped region 121; and the third electrical connection structure 126 electrically connecting the sixth doped region 122 and the seventh doped region 123.

[0072] In this embodiment, the first region 102 has a third gate structure, and the third region 104 has a fourth gate structure. The second electrical connection structure 125 electrically connects the fourth doped region 120, the fifth doped region 121, and the third gate structure; the third electrical connection structure 126 electrically connects the sixth doped region 122, the seventh doped region 123, and the fourth gate structure.

[0073] The technical solution of this invention involves forming a first gate structure and a second gate structure on the surface of the second region 103, with the first doped region 117, the first gate structure, and the second gate structure electrically connected. On one hand, as the electrostatic voltage increases, the drift current in the first region 102, the second region 103, and the third region 104 increases. Due to the presence of parasitic resistance, the second region 103 has a higher potential relative to the third region 104. Meanwhile, the first gate structure and the second gate structure, electrically connected to the first doped region 117, are at the same potential. This causes the negative charge in the second region 103 to move upwards, resulting in the parasitic diode formed by the second doped region 118 and the second region 103 opening prematurely to form the first channel for discharging current. As the electrostatic voltage further increases, the PNPN SCR structure formed by the fourth doped region 120, the first region 102, the second doped region 118, the second region 103, the third doped region 119, the third region 104, and the sixth doped region 122 opens, forming the main second channel for discharging current. The presence of the first channel reduces the emitter injection efficiency of parasitic PNP and NPN, and decreases the positive feedback gain between PNP and NPN. The first gate structure and the second gate structure can improve the holding voltage and reduce the probability of latch-up. On the other hand, the first region 102 and the third region 104 are symmetrical structures, so the first region 102 and the third region 104 can be interchanged to form a bidirectional structure.

[0074] Furthermore, a third gate structure is formed on the first region 102, and a fourth gate structure is formed on the third region 104. The second electrical connection structure 125 electrically connects the fourth doped region 120, the fifth doped region 121, and the third gate structure. The third electrical connection structure 126 electrically connects the sixth doped region 122, the seventh doped region 123, and the fourth gate structure. When forward electrostatic discharge occurs at the anode of either the second electrical connection structure 125 or the third electrical connection structure 126, a downward-directed electric field is formed below the third gate structure. Under the action of the electric field, the positive charge in the first region 102 flows into the device body, preventing charge congestion on the device surface, increasing the device's failure current, and improving robustness.

[0075] Accordingly, the present invention also provides an electrostatic protection structure, please refer to the following: Figure 4 ,include:

[0076] A substrate having a well region, the well region comprising an adjacent first region 102, a second region 103 and a third region 104, the second region 103 being located between the first region 102 and the third region 104, the first region 102 and the third region 104 having the same conductivity type, and the first region 102 and the second region 103 having opposite conductivity types.

[0077] The first gate structure and the second gate structure are located on the surface of the second region 103;

[0078] A first doped region 117 is located within the second region 103. The first doped region 117 is located between the first gate structure and the second gate structure. The first doped region 117 contains a first ion. The conductivity type of the first ion is the same as that of the second region. The first doped region 117, the first gate structure, and the second gate structure are electrically connected.

[0079] A second doped region 118 spans the second region 103 and the first region 102. The second doped region 118 and the first doped region 117 are located on both sides of the first gate structure. The second doped region 118 contains second ions, and the conductivity type of the second ions is opposite to that of the first ions.

[0080] A third doped region 119 spans the second region 103 and the third region 104. The third doped region 119 and the first doped region 117 are located on both sides of the second gate structure. The third doped region 119 contains a third ion, and the conductivity type of the third ion is opposite to that of the first ion.

[0081] The fourth doped region 120 and the fifth doped region 121 are located in the first region 102. The fourth doped region 120 contains a fourth ion, and the fifth doped region 121 contains a fifth ion. The fourth ion has the same conductivity type as the first region, and the fourth ion has the opposite conductivity type to the fifth ion. The fourth doped region 120 and the fifth doped region 121 are electrically connected.

[0082] The sixth doped region 122 and the seventh doped region 123 are located in the third region 104. The sixth doped region 122 contains a sixth ion, and the seventh doped region 123 contains a seventh ion. The seventh ion and the fourth ion have the same conductivity type, and the sixth ion and the seventh ion have opposite conductivity types. The sixth doped region 122 and the seventh doped region 123 are electrically connected.

[0083] In this embodiment, the system further includes: a first electrical connection structure 124 located on the substrate, through which the first doped region 117, the first gate structure, and the second gate structure are electrically connected; a second electrical connection structure 125 located on the substrate, through which the fourth doped region 120 and the fifth doped region 121 are electrically connected; and a third electrical connection structure 126 located on the substrate, through which the sixth doped region 122 and the seventh doped region 123 are electrically connected.

[0084] In this embodiment, it further includes: a third gate structure located on the first region 102, the third gate structure being adjacent to the fifth doped region 121; and a fourth gate structure located on the third region 104, the fourth gate structure being adjacent to the sixth doped region 122.

[0085] In other embodiments, the third gate structure and the fourth gate structure are not present.

[0086] In this embodiment, the second electrical connection structure 125 electrically connects the fourth doped region 120, the fifth doped region 121 and the third gate structure; the third electrical connection structure 126 electrically connects the sixth doped region 122, the seventh doped region 123 and the fourth gate structure.

[0087] In this embodiment, it further includes: a third isolation structure 106 located in the first region 102, wherein the third gate structure and the second doped region 118 are located on both sides of the third isolation structure 106; and a fourth isolation structure 107 located in the third region 104, wherein the fourth gate structure and the third doped region 119 are located on both sides of the fourth isolation structure 107.

[0088] In this embodiment, the materials of the third isolation structure 106 and the fourth isolation structure 107 include silicon dioxide.

[0089] In this embodiment, the first gate structure includes a first gate oxide layer 109 and a first gate layer 110 located on the first gate oxide layer 109; the second gate structure includes a second gate oxide layer 111 and a second gate layer 112 located on the second gate oxide layer 111; the third gate structure includes a third gate oxide layer 113 and a third gate layer 114 located on the third gate oxide layer 113; and the fourth gate structure includes a fourth gate oxide layer 115 and a fourth gate layer 116 located on the fourth gate oxide layer 115.

[0090] In this embodiment, the first gate oxide layer 109, the second gate oxide layer 111, the third gate oxide layer 113, and the fourth gate oxide layer 115 are made of silicon dioxide; the first gate layer 110, the second gate layer 112, the third gate layer 114, and the fourth gate layer 116 are made of polysilicon.

[0091] In this embodiment, the first, fifth, and sixth ions are of N-type conductivity, and the N-type ions include phosphorus ions or arsenic ions; the second, third, fourth, and seventh ions are of P-type conductivity, and the P-type ions include boron ions.

[0092] In this embodiment, the conductivity type of the first region 102 and the third region 104 includes P-type; the conductivity type of the second region 103 includes N-type.

[0093] In this embodiment, the doping ion concentrations of the first doping region 117, the fifth doping region 121, and the sixth doping region 122 are the same; the doping ion concentrations of the second doping region 118, the third doping region 119, the fourth doping region 120, and the seventh doping region 123 are the same.

[0094] In this embodiment, it further includes: a first isolation structure 105 located in the first region 102, the first isolation structure 105 being located between the fourth doped region 120 and the fifth doped region 121; and a second isolation structure 108 located in the third region 104, the second isolation structure 108 being located between the sixth doped region 122 and the seventh doped region 123.

[0095] In this embodiment, the materials of the first isolation structure 105 and the second isolation structure 108 include silicon dioxide.

[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrostatic protection structure, characterized in that, include: A substrate having a well region comprising an adjacent first region, a second region, and a third region, wherein the second region is located between the first and third regions, the first and third regions having the same conductivity type, and the first and second regions having opposite conductivity types. The first gate structure and the second gate structure are located on the surface of the second region; A first doped region is located within the second region, between the first gate structure and the second gate structure. The first doped region contains a first ion, the conductivity type of which is the same as that of the second region. The first doped region, the first gate structure, and the second gate structure are electrically connected. A second doped region spans the second region and the first region, the second doped region and the first doped region are located on both sides of the first gate structure, the second doped region contains a second ion, the conductivity type of the second ion is opposite to that of the first ion; A third doped region spans the second region and the third region. The third doped region and the first doped region are located on both sides of the second gate structure. The third doped region contains a third ion, and the conductivity type of the third ion is opposite to that of the first ion. The fourth doped region and the fifth doped region are located within the first region. The fourth doped region contains a fourth ion, and the fifth doped region contains a fifth ion. The fourth ion has the same conductivity type as the first region, and the fourth ion has the opposite conductivity type to the fifth ion. The fourth doped region and the fifth doped region are electrically connected. The sixth and seventh doped regions are located within the third region. The sixth doped region contains a sixth ion, and the seventh doped region contains a seventh ion. The seventh ion and the fourth ion have the same conductivity type, while the sixth ion and the seventh ion have opposite conductivity types. The sixth and seventh doped regions are electrically connected.

2. The electrostatic protection structure as described in claim 1, characterized in that, Also includes: A first electrical connection structure is located on the substrate, and the first doped region, the first gate structure, and the second gate structure are electrically connected through the first electrical connection structure. A second electrical connection structure is located on the substrate, through which the fourth and fifth doped regions are electrically connected; a third electrical connection structure is located on the substrate, through which the sixth and seventh doped regions are electrically connected.

3. The electrostatic protection structure as described in claim 2, characterized in that, Also includes: A third gate structure located on the first region, the third gate structure being adjacent to the fifth doped region; A fourth gate structure is located in the third region, and the fourth gate structure is adjacent to the sixth doped region.

4. The electrostatic protection structure as described in claim 3, characterized in that, The second electrical connection structure electrically connects the fourth doped region, the fifth doped region, and the third gate structure; the third electrical connection structure electrically connects the sixth doped region, the seventh doped region, and the fourth gate structure.

5. The electrostatic protection structure as described in claim 3, characterized in that, Also includes: A third isolation structure is located within the first region, with the third gate structure and the second doped region located on both sides of the third isolation structure; a fourth isolation structure is located within the third region, with the fourth gate structure and the third doped region located on both sides of the fourth isolation structure.

6. The electrostatic protection structure as described in claim 5, characterized in that, The materials of the third and fourth isolation structures include silicon dioxide.

7. The electrostatic protection structure as described in claim 3, characterized in that, The first gate structure includes a first gate oxide layer and a first gate layer located on the first gate oxide layer; the second gate structure includes a second gate oxide layer and a second gate layer located on the second gate oxide layer; the third gate structure includes a third gate oxide layer and a third gate layer located on the third gate oxide layer; the fourth gate structure includes a fourth gate oxide layer and a fourth gate layer located on the fourth gate oxide layer.

8. The electrostatic protection structure as described in claim 7, characterized in that, The first gate oxide layer, the second gate oxide layer, the third gate oxide layer, and the fourth gate oxide layer are made of silicon dioxide; the first gate layer, the second gate layer, the third gate layer, and the fourth gate layer are made of polysilicon.

9. The electrostatic protection structure as described in claim 1, characterized in that, The first, fifth, and sixth ions are of N-type conductivity, and the N-type ions include phosphorus ions or arsenic ions; the second, third, fourth, and seventh ions are of P-type conductivity, and the P-type ions include boron ions.

10. The electrostatic protection structure as described in claim 1, characterized in that, The first and third regions have a conductivity type of P; the second region has a conductivity type of N.

11. The electrostatic protection structure as described in claim 1, characterized in that, The dopant ion concentrations are the same in the first, fifth, and sixth dopant regions; the dopant ion concentrations are the same in the second, third, fourth, and seventh dopant regions.

12. The electrostatic protection structure as described in claim 1, characterized in that, Also includes: A first isolation structure located within the first region, the first isolation structure being situated between the fourth doped region and the fifth doped region; The second isolation structure is located within the third region, between the sixth and seventh doped regions.

13. The electrostatic protection structure as described in claim 12, characterized in that, The materials of the first isolation structure and the second isolation structure include silicon dioxide.

14. A method for forming an electrostatic protection structure, characterized in that, include: A substrate is provided having a well region therein, the well region comprising an adjacent first region, a second region, and a third region, the second region being located between the first region and the third region, the first region and the third region having the same conductivity type, and the first region and the second region having opposite conductivity types; A first gate structure and a second gate structure are formed on the surface of the second region; A first doped region is formed in the second region. The first doped region is located between the first gate structure and the second gate structure. The first doped region contains a first ion, and the conductivity type of the first ion is the same as that of the second region. A second doped region is formed within the well region, spanning the second region and the first region. The second doped region and the first doped region are located on opposite sides of the first gate structure. The second doped region contains second ions, and the conductivity type of the second ions is opposite to that of the first ions. A third doped region is formed within the well region, spanning the second and third regions. The third doped region and the first doped region are located on opposite sides of the second gate structure. The third doped region contains a third ion, the conductivity type of which is opposite to that of the first ion. A fourth doped region and a fifth doped region are formed within the first region. The fourth doped region contains a fourth ion, and the fifth doped region contains a fifth ion. The fourth ion has the same conductivity type as the first region, and the fourth ion has the opposite conductivity type to the fifth ion. A sixth doped region and a seventh doped region are formed in the third region. The sixth doped region contains a sixth ion, and the seventh doped region contains a seventh ion. The seventh ion and the fourth ion have the same conductivity type, while the sixth ion and the seventh ion have opposite conductivity types. Electrically connects the first doped region, the first gate structure, and the second gate structure; Electrically connect the fourth doped region and the fifth doped region; The sixth and seventh doped regions are electrically connected.

15. The method for forming the electrostatic protection structure as described in claim 14, characterized in that, A method for electrically connecting the first doped region, the first gate structure, and the second gate structure, electrically connecting the fourth and fifth doped regions, and electrically connecting the sixth and seventh doped regions includes: forming a first electrical connection structure, a second electrical connection structure, and a third electrical connection structure on a substrate, wherein the first electrical connection structure electrically connects the first doped region, the first gate structure, and the second gate structure, the second electrical connection structure electrically connects the fourth and fifth doped regions, and the third electrical connection structure electrically connects the sixth and seventh doped regions.

16. The method for forming the electrostatic protection structure as described in claim 15, characterized in that, While forming the first gate structure and the second gate structure on the surface of the second region, the method further includes: forming a third gate structure on the first region, wherein the fifth doped region is adjacent to the third gate structure; forming a fourth gate structure on the third region, wherein the sixth doped region is adjacent to the fourth gate structure; the second electrical connection structure electrically connects the fourth doped region, the fifth doped region and the third gate structure; and the third electrical connection structure electrically connects the sixth doped region, the seventh doped region and the fourth gate structure.

17. The method for forming the electrostatic protection structure as described in claim 16, characterized in that, Before forming the fourth and fifth doped regions in the first region, the method further includes: forming a first isolation structure in the first region, wherein the fourth and fifth doped regions are located in the first region on both sides of the first isolation structure; before forming the sixth and seventh doped regions in the third region, the method further includes: forming a second isolation structure in the third region, wherein the sixth and seventh doped regions are located in the third region on both sides of the second isolation structure.

18. The method for forming the electrostatic protection structure as described in claim 17, characterized in that, The second isolation structure and the first isolation structure are formed simultaneously; While forming the second isolation structure and the first isolation structure, the method also includes: forming a third isolation structure in the first region, wherein the third gate structure and the second doped region are located on both sides of the third isolation structure, respectively. A fourth isolation structure is formed within the third region, with the fourth gate structure and the third doped region located on opposite sides of the fourth isolation structure.

19. The method for forming the electrostatic protection structure as described in claim 14, characterized in that, The formation process of the first doped region includes an ion implantation process; the formation process of the second doped region includes an ion implantation process; the formation process of the third doped region includes an ion implantation process; the formation process of the fourth doped region includes an ion implantation process; the formation process of the fifth doped region includes an ion implantation process; the formation process of the sixth doped region includes an ion implantation process; and the formation process of the seventh doped region includes an ion implantation process.

20. The method for forming the electrostatic protection structure as described in claim 14, characterized in that, The first, fifth, and sixth ions are of N-type conductivity, and the N-type ions include phosphorus ions or arsenic ions; the second, third, fourth, and seventh ions are of P-type conductivity, and the P-type ions include boron ions.

21. The method for forming the electrostatic protection structure as described in claim 20, characterized in that, The first doped region, the fifth doped region, and the sixth doped region are formed simultaneously; the second doped region, the third doped region, the fourth doped region, and the seventh doped region are formed simultaneously.

22. The method for forming the electrostatic protection structure as described in claim 14, characterized in that, The first and third regions have a conductivity type of P; the second region has a conductivity type of N.

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