Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: forming first trenches between a plurality of first active areas and adjacent first active areas in the storage area, forming second trenches between a plurality of second active areas and adjacent second active areas in the peripheral area, forming floating gates with the floating gate material layer, providing third trenches between adjacent floating gates on the peripheral area, wherein the bottom of the third trench exposes a portion of the top surface of the second active area; performing oxidation treatment on the surface of the first active area exposed by the first trench, the surface of the second active area exposed by the second trench, and the surface of the second active area exposed by the third trench to form an inner liner layer, wherein a first vertex angle is provided between the sidewall and the top of the first active area, and a second vertex angle is provided between the sidewall and the top of the second active area, and the curvature of the second vertex angle is greater than the curvature of the first vertex angle, so as to form active areas with different vertex angle roundnesses in the storage area and the peripheral area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Flash memory is a type of non-volatile memory that can retain data even without a current supply, meaning it persists even during power outages. Its lack of high voltages for electrical erasure and reprogramming, combined with its low manufacturing cost and high storage density, have made it a mainstream non-volatile semiconductor storage technology. Its unique properties have led to its widespread application in various fields, including embedded systems such as telecommunications switches, cellular phones, network interconnect equipment, instrumentation, and automotive devices, as well as emerging voice, image, and data storage products.

[0003] ETOX (Erasable Programmable Read Only Memory with Tunnel Oxide) flash memory is a type of non-volatile flash memory. Its characteristic is that applications can run directly in the flash memory without having to read the code into the system random access memory, which makes it have higher transmission efficiency. Therefore, flash memory with this structure is widely used.

[0004] However, the ETOX structure formed by existing flash memory technology needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a storage area and a peripheral area; a plurality of first active areas located in the storage area and a plurality of second active areas located in the peripheral area, a first trench being provided between adjacent first active areas, and a second trench being provided between adjacent second active areas; floating gates located on the first active areas and the second active areas, a third trench being provided between adjacent floating gates on the peripheral area, the third trench being connected to the second trench, and the bottom of the third trench exposing a portion of the top surface of the second active area; an inner liner layer being located at the first trench exposing the surface of the first active area, the second trench, and the surface of the second active area exposed by the third trench, a first vertex angle being provided between the sidewall and the top of the first active area, a second vertex angle being provided between the sidewall and the top of the second active area, and a curvature of the second vertex angle being greater than that of the first vertex angle.

[0007] Optionally, an isolation layer is provided in the first trench and the second trench.

[0008] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a storage area and a peripheral area; forming a floating gate material layer on the substrate; removing part of the floating gate material layer and part of the substrate, forming a plurality of first active areas and first trenches between adjacent first active areas in the storage area, forming a plurality of second active areas and second trenches between adjacent second active areas in the peripheral area, forming a floating gate with the floating gate material layer, a third trench between adjacent floating gates on the peripheral area, the third trench being connected to the second trench, and the bottom of the third trench exposing part of the top surface of the second active area; performing oxidation treatment on the surface of the first active area exposed by the first trench, the second trench, and the surface of the second active area exposed by the third trench to form an inner liner layer, wherein a first vertex angle is formed between the sidewall and the top of the first active area, a second vertex angle is formed between the sidewall and the top of the second active area, and a curvature of the second vertex angle is greater than the curvature of the first vertex angle.

[0009] Optionally, the method further includes: forming a hard mask layer on the surface of the floating gate before forming the liner layer.

[0010] Optionally, after forming the first trench, the second trench and the third trench are formed.

[0011] Optionally, the method for forming the plurality of first active areas, the plurality of second active areas, the first trench, the second trench, the third trench, the floating gate, and the hard mask layer includes: forming a hard mask material layer on the surface of the floating gate material layer; patterning the hard mask material layer to form a transition hard mask layer, wherein the transition hard mask layer exposes a portion of the surface of the floating gate material layer on the storage area; using the transition hard mask layer as a mask, etching the floating gate material layer and the storage area to form the first trench and the first active area, so as to The floating gate material layer forms a transition floating gate; a protective layer is formed in the first trench, and the protective layer is also located on the sidewalls of the transition floating gate and the sidewalls of the transition hard mask layer; after the protective layer is formed, the transition hard mask layer is patterned to form a hard mask layer, and the hard mask layer exposes part of the surface of the transition floating gate on the peripheral area; using the hard mask layer as a mask, the transition floating gate and the peripheral area are etched to form the second active area, the second trench, the third trench and the floating gate; after the second active area is formed, the protective layer is removed.

[0012] Optionally, the process of etching the transition floating gate and the peripheral region includes a first dry etching process.

[0013] Optionally, the etching selectivity ratio of the first dry etching process to the floating gate material layer and the substrate ranges from 1:1 to 5:1.

[0014] Optionally, the first trench is formed after the second trench and the third trench are formed.

[0015] Optionally, the method for forming the plurality of first active areas, the plurality of second active areas, the first trench, the second trench, the third trench, the floating gate, and the hard mask layer includes: forming a hard mask material layer on the surface of the floating gate material layer; patterning the hard mask material layer to form a transition hard mask layer, wherein the transition hard mask layer exposes a portion of the surface of the floating gate material layer on the peripheral area; using the transition hard mask layer as a mask, etching the floating gate material layer and the peripheral area to form the third trench, the second trench, and the third trench. a second active area, forming a transition floating gate with the floating gate material layer; forming a protective layer in the second trench and the third trench, the protective layer also being located on the sidewalls of the transition hard mask layer; after forming the protective layer, patterning the transition hard mask layer to form a hard mask layer, the hard mask layer exposing a portion of the surface of the transition floating gate on the storage area; using the hard mask layer as a mask, etching the transition floating gate and the storage area to form the first active area, the first trench and the floating gate; after forming the first active area, removing the protective layer.

[0016] Optionally, the process of etching the floating gate material layer and the peripheral region includes a first dry etching process.

[0017] Optionally, the etching selectivity ratio of the first dry etching process to the floating gate material layer and the substrate ranges from 1:1 to 5:1.

[0018] Optionally, before forming the liner layer and after forming the floating gate, the method further includes: etching back the hard mask layer to expose a portion of the top surface of the floating gate.

[0019] Optionally, the process of etching back the hard mask layer includes a wet etching process.

[0020] Optionally, before forming the floating gate material layer, a tunneling oxide material layer is further formed on the substrate; and the tunneling oxide material layer is etched to form a tunneling oxide layer.

[0021] Optionally, after forming the liner layer, the method further includes: forming an isolation layer in the first trench and the second trench.

[0022] Optionally, the oxidation treatment process includes an in-situ steam generation process.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the method for forming a semiconductor structure provided by the technical solution of the present invention, an oxidation treatment is performed on the surface of the first active area exposed by the first trench and the surfaces of the second active area exposed by the second and third trenches to form a liner layer. The sidewalls and top of the first active area have a first vertex angle, and the sidewalls and top of the second active area have a second vertex angle, and the curvature of the second vertex angle is greater than the curvature of the first vertex angle. During the formation of the liner layer, the vertex angle of the second active area is more exposed than the vertex angle of the first active area. Therefore, the vertex angle of the second active area is consumed more during the oxidation reaction, thereby making the curvature of the second vertex angle greater than the curvature of the first vertex angle. In response to the different device requirements of the storage area and the peripheral area, active areas with different vertex angle roundness are formed in the storage area and the peripheral area, thereby reducing the occurrence of MOS tube device leakage problems caused by the difference in vertex angle roundness of the active area in the peripheral area, and facilitating improved device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 3 It is a structural schematic diagram of each step of a conventional method for forming a semiconductor structure;

[0026] Figures 4 to 9 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0027] Figures 10 to 12 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0028] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0029] As described in the background art, the ETOX structure formed using existing flash memory technology needs to be further improved. A method for forming a semiconductor structure is now described and analyzed.

[0030] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a conventional method for forming a semiconductor structure.

[0031] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a storage area Cell and a peripheral area Peri; forming a tunneling oxygen material layer 101, a floating gate material layer 102 located on the tunneling oxygen material layer 101, and a hard mask material layer 103 located on the floating gate material layer 102 on the substrate 100.

[0032] Please refer to Figure 2, etching the hard mask material layer 103, the floating gate material layer 102, the tunneling oxide material layer 101 and the substrate 100, forming a first active area 104 in the storage area Cell, and a first trench 105 in the hard mask material layer 103, the floating gate material layer 102, and the tunneling oxide material layer 101 between adjacent first active areas 104 and on the storage area Cell, and forming a second active area 106 in the peripheral area Peri, and a second trench 107 in the hard mask material layer 103, the floating gate material layer 102, and the tunneling oxide material layer 101 between adjacent second active areas 106 and on the peripheral area Peri.

[0033] Please refer to Figure 3 A liner layer 108 is formed on the bottom and sidewalls of the first trench 105 and the bottom and sidewalls of the second trench 107 .

[0034] In the above method, the material of the liner layer 108 is silicon oxide. After the sinking layer 108 is formed, a shallow trench isolation region for the storage area Cell is formed in the first trench 105, and a shallow trench isolation region for the peripheral area Peri is formed in the second shallow trench 108. During the formation of the liner layer 108, two in-situ water vapor oxidation processes are typically used. The top corners Corner of the first active area 104 and the second active area 106 are consumed during the oxidation process and become rounded, thereby reducing the roundness of the top corners Corner. The top corners of the active areas of the storage area Cell and the peripheral area Peri obtained by this method have the same roundness.

[0035] However, the storage area Cell devices and the peripheral area Peri devices have different requirements for the roundness of the top corners of the active area. The devices in the storage area Cell have lower requirements for the roundness of the top corners than the devices in the peripheral area Peri, while the logic circuits in the peripheral area Peri have higher requirements for the roundness of the top corners of the active area. The poor roundness of the top corners of the active area in the peripheral area Peri will lead to problems such as leakage of MOS tube devices.

[0036] To address the above-mentioned problems, the present invention provides a semiconductor structure and a method for forming the same. The surface of the first active area exposed by the first trench and the surfaces of the second active area exposed by the second and third trenches are oxidized to form a liner layer. The first active area has a first vertex angle between its sidewalls and top, and a second vertex angle between its sidewalls and top. The curvature of the second vertex angle is greater than the curvature of the first vertex angle. During the formation of the liner layer, the vertex angle of the second active area is exposed to a greater extent than the vertex angle of the first active area. Therefore, the vertex angle of the second active area is consumed more during the oxidation reaction, thereby making the curvature of the second vertex angle greater than the curvature of the first vertex angle. To meet the different device requirements of the storage area and the peripheral area, active areas with different vertex angle roundness are formed in the storage area and the peripheral area. This reduces leakage problems in MOS transistor devices caused by the difference in vertex angle roundness of the active areas in the peripheral area, thereby improving device performance.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 4 to 9 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0039] Please refer to Figure 4 , providing a substrate 200, wherein the substrate 200 includes a storage area I and a peripheral area II.

[0040] In this embodiment, the substrate 200 is made of single crystal silicon. In other embodiments, the substrate may be polycrystalline silicon or amorphous silicon, or a semiconductor material such as germanium, silicon germanium, gallium arsenide, or a semiconductor-on-insulator structure.

[0041] The storage area I is used to form a storage device, and the peripheral area II is used to form a peripheral device.

[0042] In this embodiment, the storage area I includes a first double deep well region (not shown in the figure), a heavily doped well region (not shown in the figure) located above the first double deep well region, and a threshold voltage adjustment region (not shown in the figure) located above the heavily doped well region. Specifically, the first double deep well region has an N-type conductivity, and the heavily doped well region has a P-type conductivity.

[0043] In this embodiment, a second deep well region (not shown in the figure) is provided in the peripheral region II, and the conductivity type of the second deep well region is N-type.

[0044] Please continue to refer to Figure 4 , a floating gate material layer 201 is formed on the substrate 200.

[0045] In this embodiment, before forming the floating gate material layer 201 , a tunneling oxide material layer 202 is further formed on the substrate 200 .

[0046] Subsequently, part of the floating gate material layer 201 and part of the substrate 200 are removed, and first trenches are formed between several first active areas and adjacent first active areas in the storage area I, and second trenches are formed between several second active areas and adjacent second active areas in the peripheral area II. A floating gate is formed with the floating gate material layer 201, and a third trench is provided between adjacent floating gates on the peripheral area II. The third trench is connected to the second trench, and the bottom of the third trench exposes part of the top surface of the second active area; the surface of the first active area exposed by the first trench, the second trench, and the surface of the second active area exposed by the third trench are oxidized to form an inner liner layer.

[0047] In this embodiment, before forming the liner layer, a hard mask layer is formed on the surface of the floating gate, and the hard mask layer is used as a mask to form the plurality of second active regions, the second trenches, and the third trenches.

[0048] In this embodiment, the second trench and the third trench are formed after the first trench is formed. In another embodiment, the first trench is formed after the second trench and the third trench are formed.

[0049] In this embodiment, the formation method of the plurality of first active areas, the plurality of second active areas, the first trench, the second trench, the third trench, the floating gate and the hard mask layer can be referred to. Figures 5 to 7 .

[0050] Please refer to Figure 5 , forming a hard mask material layer (not shown in the figure) on the surface of the floating gate material layer 201; patterning the hard mask material layer to form a transition hard mask layer 203, wherein the transition hard mask layer 203 exposes part of the surface of the floating gate material layer 201 on the storage area I; using the transition hard mask layer 203 as a mask, etching the floating gate material layer 201 and the storage area I to form the first trench 204 and the first active area 205, and forming a transition floating gate 206 with the floating gate material layer 201.

[0051] The process of etching the floating gate material layer 201 and the storage area I includes a second dry etching process. The second dry etching process is conducive to forming a better opening morphology.

[0052] The method for forming the transition hard mask layer 203 includes: forming a first photoresist material layer (not shown in the figure) on the surface of the hard mask material layer; patterning the first photoresist material layer to form a first photolithography layer (not shown in the figure), the first photolithography layer exposing a portion of the surface of the hard mask material layer on the storage area I; and etching the hard mask material layer using the first photolithography layer as a mask.

[0053] Please refer to Figure 6 A protection layer 208 is formed in the first trench 205 . The protection layer 208 is also located on the sidewalls of the transition floating gate 206 and the sidewalls of the transition hard mask layer 203 .

[0054] Specifically, the protective layer 208 is also located on the surface of the transition hard mask layer 203; the surface of the protective layer 208 also has a second photoresist material layer 209. During the subsequent etching process of the second trench, the protective layer 208 is used to protect the first trench 205 from further etching. The second photoresist material layer 209 is used to pattern the transition hard mask layer 203 to form a hard mask layer.

[0055] The material of the protective layer 208 includes an organic polymer. The organic polymer has fluidity and is easy to fill in the first groove 205. In this embodiment, the material of the protective layer 208 is a spin-on-carbon (SOC) material.

[0056] Please refer to Figure 7 After forming the protective layer 208, the transition hard mask layer 203 is patterned to form a hard mask layer 210, wherein the hard mask layer 210 exposes a portion of the surface of the transition floating gate 206 on the peripheral region II; using the hard mask layer 210 as a mask, the transition floating gate 206 and the peripheral region II are etched to form the second active region 211, the second trench 212, the third trench 213 and the floating gate 214; after forming the second active region 211, the protective layer 208 is removed.

[0057] Specifically, the method for forming the hard mask layer 210 also includes: patterning the second photoresist material layer 209 to form a second photoresist layer (not shown in the figure), the second photoresist layer exposing a portion of the surface of the transition hard mask layer 203 on the peripheral area II; using the second photoresist layer as a mask, etching the transition hard mask layer 203.

[0058] A second trench 212 is provided between adjacent second active regions 211 , and a third trench 213 is provided between adjacent floating gates 214 on the peripheral region II. The third trench 213 is connected to the second trench 212 , and the bottom of the third trench 213 partially exposes the top surface of the second active region 211 .

[0059] The process of etching the transition floating gate 206 and the peripheral region II includes a first dry etching process.

[0060] The first dry etching process has an etching selectivity ratio between the floating gate material layer 201 and the substrate 200 ranging from 1:1 to 5:1. This etching selectivity range is selected to facilitate etching of the floating gate material layer 201 relative to the substrate 200, exposing a portion of the top surface of the second active region 211 at the bottom of the third trench 213, while avoiding over-etching of the floating gate 214 formed in the peripheral region II.

[0061] In this embodiment, the second active region 211, the second trench 212, and the third trench 213 are formed by a single dry etching process. In other embodiments, the dry etching process may not be limited to a single process, and multiple etching processes may be used.

[0062] In this embodiment, the tunneling oxide material layer 202 is etched to form a tunneling oxide layer 215 .

[0063] In this embodiment, before forming the liner layer and after forming the floating gate 214, please refer to Figure 8 .

[0064] Please refer to Figure 8 , the hard mask layer 210 is etched back to expose a portion of the top surface of the floating gate 214.

[0065] The purpose of etching back the hard mask layer 210 is to increase the opening between adjacent hard mask layers 210 to facilitate the subsequent filling of the isolation layer material in the first trench and the second trench. In other embodiments, the hard mask layer 210 may not be etched back.

[0066] The process of etching back the hard mask layer 210 includes a wet etching process. In this embodiment, phosphoric acid solution is used to etch the hard mask layer 210.

[0067] Please refer to Figure 9 The surface of the first active area 204 exposed by the first trench 205 and the surfaces of the second active area 211 exposed by the second trench 212 and the third trench 213 are oxidized to form an inner liner 216. A first vertex angle E is formed between the sidewall and the top of the first active area 204, and a second vertex angle D is formed between the sidewall and the top of the second active area 211. The curvature of the second vertex angle D is greater than the curvature of the first vertex angle E.

[0068] In this embodiment, the oxidation process includes an in-situ water vapor generation process. The oxidation process is used to form a protective layer between the isolation layer and the first active area 204 and the second active area 211. At the same time, during the formation of the liner layer 216, the top corner of the second active area 211 is more exposed than the top corner of the first active area 204. Therefore, the top corner of the second active area 211 is consumed more during the oxidation reaction, thereby making the curvature of the second top corner D greater than the curvature of the first top corner E. In response to the different device requirements of the storage area I and the peripheral area II, active areas with different top corner roundness are formed in the storage area I and the peripheral area II, thereby reducing the leakage problem of the MOS tube device caused by the difference in top corner roundness of the active area in the peripheral area II, thereby improving device performance.

[0069] In this embodiment, the liner layer 216 is also located on the sidewalls of the floating gate 214 and the sidewalls of the hard mask layer 210 .

[0070] After the liner layer 216 is formed, an isolation layer (not shown) is further formed in the first trench 205 and the second trench 212 .

[0071] Correspondingly, the technical solution of the present invention also provides an embodiment of a semiconductor structure formed by the above-mentioned forming method, please continue to refer to Figure 9 , comprising: a substrate 200, the substrate 200 comprising a storage area I and a peripheral area II; a plurality of first active areas 204 located in the storage area I and a plurality of second active areas 211 located in the peripheral area II, a first trench 205 being provided between adjacent first active areas 204, a second trench 212 being provided between adjacent second active areas 211; floating gates 214 located on the first active areas 204 and the second active areas 211, a third trench 213 being provided between adjacent floating gates 214 on the peripheral area II, the third trench 213 The third trench 213 is connected to the second trench 212, and the bottom of the third trench 213 exposes a portion of the top surface of the second active area 211; the liner layer 216 is located between the surface of the first active area 204 exposed by the first trench 205, the surface of the second active area 211 exposed by the second trench 212 and the third trench 213, and the first active area 204 has a first vertex angle E between the side wall and the top, and the second active area 211 has a second vertex angle D between the side wall and the top, and the curvature of the second vertex angle D is greater than the curvature of the first vertex angle E.

[0072] An isolation layer (not shown) is provided in the first trench 205 and the second trench 212 .

[0073] Figures 10 to 12 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention.

[0074] The difference between this embodiment and the previous embodiment is the order in which the first trench, the second trench, and the third trench are formed. In this embodiment, the first trench is formed after the second trench and the third trench are formed. Specifically, the method for forming the plurality of first active areas, the plurality of second active areas, the first trench, the second trench, the third trench, the floating gate, and the hard mask layer is described in detail. Figure 4 Based on this, continue to refer to Figures 10 to 12 .

[0075] Please refer to Figure 10 , forming a hard mask material layer (not shown in the figure) on the surface of the floating gate material layer 201; patterning the hard mask material layer to form a transition hard mask layer 301, the transition hard mask layer 301 exposing a portion of the surface of the floating gate material layer 201 on the peripheral area II; using the transition hard mask layer 301 as a mask, etching the floating gate material layer 201 and the peripheral area II to form the third trench 302, the second trench 303 and the second active area 304, and forming a transition floating gate 305 with the floating gate material layer 201.

[0076] A second trench 303 is defined between adjacent second active regions 304 .

[0077] Subsequently, the transition floating gate 305 on the peripheral region II is used as the floating gate on the peripheral region II. A third trench 302 is formed between adjacent floating gates on the peripheral region II. The third trench 302 is connected to the second trench 303. The bottom of the third trench 302 exposes a portion of the top surface of the second active region 304.

[0078] The process of etching the floating gate material layer 201 and the peripheral region II includes a first dry etching process.

[0079] The etching selectivity ratio of the first dry etching process to the floating gate material layer 201 and the substrate 200 ranges from 1:1 to 5:1.

[0080] Please refer to Figure 11 A protection layer 306 is formed in the second trench 303 and the third trench 302 . The protection layer 306 is also located on the sidewalls of the transition hard mask layer 301 .

[0081] Specifically, the protective layer 306 is also located on the surface of the transition hard mask layer 301; the surface of the protective layer 306 also has a second photoresist material layer 307. During the subsequent etching process of the first trench, the protective layer 306 is used to protect the second trench 303 and the third trench 302 from further etching. The second photoresist material layer 307 is used to pattern the transition hard mask layer 301 to form a hard mask layer.

[0082] Please refer to Figure 12 After forming the protective layer 306, the transition hard mask layer 301 is patterned to form a hard mask layer 308, wherein the hard mask layer 308 exposes a portion of the surface of the transition floating gate 305 on the storage area I; using the hard mask layer 308 as a mask, the transition floating gate 305 and the storage area I are etched to form the first active area 309, the first trench 310 and the floating gate 311; after forming the first active area 309, the protective layer 306 is removed.

[0083] Specifically, the method for forming the hard mask layer 308 also includes: patterning the second photoresist material layer 307 to form a second photoresist layer (not shown in the figure), the second photoresist layer exposing a portion of the surface of the transition hard mask layer 301 on the storage area I; using the second photoresist layer as a mask, etching the transition hard mask layer 301.

[0084] In this embodiment, the tunneling oxide material layer 202 is etched to form a tunneling oxide layer 312 .

[0085] In this embodiment, the formation methods of other structures can be referred to the previous embodiment and will not be described in detail here.

[0086] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a storage area and a peripheral area; forming a tunneling oxide material layer on the substrate; forming a floating gate material layer on the tunneling oxide material layer; removing a portion of the floating gate material layer, a portion of the tunneling oxide material layer, and a portion of the substrate, forming first trenches between a plurality of first active areas and adjacent first active areas in the storage area, forming second trenches between a plurality of second active areas and adjacent second active areas in the peripheral area, forming floating gates with the floating gate material layer, forming tunneling oxide layers with the tunneling oxide material layer, providing third trenches between adjacent floating gates and adjacent tunneling oxide layers in the peripheral area, the third trenches communicating with the second trenches, the bottoms of the third trenches exposing portions of the top surfaces of the second active areas, wherein the third trenches, the second trenches, and the second active areas are formed by etching the floating gate material layer and the peripheral area in the same process, the process for etching the floating gate material layer and the peripheral area comprising a first dry etching process, wherein the floating gate material layer is easily etched relative to the substrate in the first dry etching process; The surface of the first active area exposed by the first trench, the surface of the second active area exposed by the second trench, and the surface of the second active area exposed by the third trench are oxidized to form an inner liner layer, a first vertex angle is provided between the side wall and the top of the first active area, a second vertex angle is provided between the side wall and the top of the second active area, and a curvature of the second vertex angle is greater than a curvature of the first vertex angle.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the liner layer, a hard mask layer is formed on the surface of the floating gate.

3. The method for forming a semiconductor structure according to claim 2, wherein: After forming the first trench, the second trench and the third trench are formed.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the plurality of first active areas, the plurality of second active areas, the first trench, the second trench, the third trench, the floating gate, and the hard mask layer comprises: forming a hard mask material layer on the surface of the floating gate material layer; patterning the hard mask material layer to form a transition hard mask layer, wherein the transition hard mask layer exposes a portion of the surface of the floating gate material layer on the storage area; etching the floating gate material layer and the storage area using the transition hard mask layer as a mask to form the first trench and the first active area, and forming the floating gate material layer and the storage area using the transition hard mask layer as a mask to form the first trench and the first active area. A gate material layer forms a transition floating gate; a protective layer is formed in the first trench, and the protective layer is also located on the sidewalls of the transition floating gate and the sidewalls of the transition hard mask layer; after the protective layer is formed, the transition hard mask layer is patterned to form a hard mask layer, and the hard mask layer exposes a portion of the surface of the transition floating gate on the peripheral area; using the hard mask layer as a mask, the transition floating gate and the peripheral area are etched to form the second active area, the second trench, the third trench and the floating gate; after the second active area is formed, the protective layer is removed.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process of etching the transition floating gate and the peripheral region includes a first dry etching process.

6. The method for forming a semiconductor structure according to claim 5, wherein: The etching selectivity ratio of the first dry etching process to the floating gate material layer and the substrate ranges from 1:1 to 5:

1.

7. The method for forming a semiconductor structure according to claim 2, wherein: After forming the second trench and the third trench, the first trench is formed.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the plurality of first active areas, the plurality of second active areas, the first trench, the second trench, the third trench, the floating gate, and the hard mask layer comprises: forming a hard mask material layer on the surface of the floating gate material layer; patterning the hard mask material layer to form a transition hard mask layer, wherein the transition hard mask layer exposes a portion of the surface of the floating gate material layer on the peripheral area; etching the floating gate material layer and the peripheral area using the transition hard mask layer as a mask to form the third trench, the second trench, and the second an active area, forming a transition floating gate with the floating gate material layer; forming a protective layer in the second trench and the third trench, the protective layer also being located on the sidewalls of the transition hard mask layer; after forming the protective layer, patterning the transition hard mask layer to form a hard mask layer, the hard mask layer exposing a portion of the surface of the transition floating gate on the storage area; using the hard mask layer as a mask, etching the transition floating gate and the storage area to form the first active area, the first trench and the floating gate; after forming the first active area, removing the protective layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process of etching the floating gate material layer and the peripheral region includes a first dry etching process.

10. The method for forming a semiconductor structure according to claim 9, wherein: The etching selectivity ratio of the first dry etching process to the floating gate material layer and the substrate ranges from 1:1 to 5:

1.

11. The method for forming a semiconductor structure according to claim 2, wherein: Before forming the liner layer and after forming the floating gate, the method further includes: etching back the hard mask layer to expose a portion of the top surface of the floating gate.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of etching back the hard mask layer includes a wet etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: After forming the liner layer, the method further includes forming an isolation layer in the first trench and the second trench.

14. The method for forming a semiconductor structure according to claim 1, wherein: The oxidation treatment process includes an in-situ steam generation process.

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