Semiconductor field effect transistor with double gate structure and method of manufacturing the same

Abstract

A semiconductor field effect transistor with double gate structure and a manufacturing method thereof, comprising a first gate and a second gate, so that the first gate and the second gate are respectively a bottom gate and a top gate of a field effect tube structure, and the bottom gate and the top gate are respectively arranged as a MOSFET structure and a MESFET structure, due to the advantages of the MOSFET structure and the MESFET structure, the working voltage range of the double gate device is expanded, the control ability of the gate to the channel is increased, the carrier mobility, SS and other parameters of the device are optimized, and the stability of the device is improved. In addition, since the MESFET (JFET) device is more sensitive to the change of the gate bias, the double gate semiconductor field effect transistor in the application can be applied to the sensing field by using this characteristic, thereby increasing the application range.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a double-gate structure semiconductor field effect transistor and a manufacturing method thereof. BACKGROUND

[0002] Today's semiconductor manufacturing industry is rapidly developing under the guidance of Moore's Law, constantly improving the performance and integration density of integrated circuits, while at the same time, trying to reduce the power consumption of integrated circuits as much as possible. Therefore, the preparation of high-performance, low-power consumption ultra-short channel devices will become the focus of future semiconductor manufacturing industry. The carrier mobility, sub-threshold swing (SS), stability, etc. of the traditional single-gate device are generally poor, and cannot adapt to the development of semiconductor manufacturing.

[0003] In order to overcome the above series of problems, a variety of gate structure field effect tubes are proposed in the prior art, the purpose is to strengthen the control ability to the channel, reduce the leakage current, and suppress the short channel effect.

[0004] However, in the current various field effect tube devices, for example, MOSFET device structure, because its switching voltage is large (generally greater than 1.5V), therefore can only be applied in high voltage circuit; and for MESFET (JFET) device structure, generally can only be applied in low voltage circuit. Therefore, the current semiconductor field effect tube device is limited by the working voltage, so that the application in the circuit is very limited. SUMMARY

[0005] The technical problem solved by the present application is to provide a double-gate structure semiconductor field effect transistor and a manufacturing method thereof, which has a wide working range and can be applied in more fields.

[0006] According to a first aspect, in one embodiment, a double-gate structure semiconductor field effect transistor is provided, comprising:

[0007] a substrate;

[0008] a first gate electrode located on a part of the surface of the substrate;

[0009] a bottom gate insulating layer covering the first gate electrode and in contact with the rest of the glass substrate surface;

[0010] an active layer located above the bottom gate insulating layer;

[0011] a second gate electrode located above the active layer;

[0012] a source layer and a drain layer located on both sides of the second gate electrode and in ohmic contact with the active layer.

[0013] Optionally, the first gate electrode is an ohmic contact metal, and the second gate electrode is a high work function metal.

[0014] Optionally, the bottom gate insulating layer is aluminum oxide, silicon nitride or silicon oxide.

[0015] Optionally, the active layer is a single active layer or a double active layer.

[0016] When the active layer is a single active layer, the active layer is a-Si, a-IGZO, a-IZO, a-ZTO, a-ITZO, LTPS, organic material or carbon nanotube; when the active layer is a double active layer, the double active layer is a composite layer of a-IGZO and a-IZO.

[0017] According to a second aspect, in an embodiment, a semiconductor field effect transistor of a double gate structure is provided, characterized in that it comprises:

[0018] a substrate;

[0019] an insulating adhesion layer on part of the surface of the substrate;

[0020] a first gate electrode covering the insulating adhesion layer;

[0021] an active layer covering the first gate electrode;

[0022] a top gate insulating layer on part of the active layer;

[0023] a second gate electrode above the active layer;

[0024] a source electrode layer and a drain electrode layer on both sides of the second gate electrode and in ohmic contact with the active layer.

[0025] Optionally, the first gate electrode is a high work function metal and the second gate electrode is an ohmic contact metal.

[0026] Optionally, the insulating adhesion layer is aluminum oxide, silicon nitride or silicon oxide.

[0027] Optionally, the active layer is a single active layer or a double active layer.

[0028] When the active layer is a single active layer, the active layer is a-Si, a-IGZO, a-IZO, a-ZTO, a-ITZO, LTPS, organic material or carbon nanotube; when the active layer is a double active layer, the double active layer is a composite layer of a-IGZO and a-IZO.

[0029] According to a third aspect, in an embodiment, a manufacturing method of a semiconductor field effect transistor of a double gate structure is provided, comprising:

[0030] growing an ohmic metal on a substrate and patterning to form a first gate electrode;

[0031] growing a bottom gate insulating layer on the first gate electrode;

[0032] Forming an active layer on the bottom gate insulating layer;

[0033] Forming a second gate, a source layer and a drain layer above the active layer, the second gate being a Schottky contact, and the source layer and the drain layer being Ohmic contacts.

[0034] According to a fourth aspect, in one embodiment, a method for manufacturing a semiconductor field effect transistor of a double gate structure, comprising:

[0035] Depositing an insulating adhesion layer on a substrate;

[0036] Depositing a high work function metal on the insulating adhesion layer to form a first gate;

[0037] Forming an active layer on the first gate, the active layer covering the first gate;

[0038] Forming a top gate insulating layer and a second gate on the active layer in sequence;

[0039] Forming a source layer and a drain layer, the source layer and the drain layer being located on two sides of the top gate insulating layer and the second gate respectively, and the source layer and the drain layer being Ohmic contacts with the active layer.

[0040] The semiconductor field effect transistor of a double gate structure and the method for manufacturing the same according to the above-mentioned embodiments comprise a first gate and a second gate, which are respectively used as a bottom gate and a top gate of a field effect transistor structure, and the bottom gate and the top gate are respectively set as a MOSFET structure and a MESFET structure. The advantages of the MOSFET structure and the MESFET structure are combined, so that the working voltage range of the double gate device is expanded, the control of the gate on the channel is increased, the carrier mobility, SS and other parameters of the device are optimized, and the stability of the device is improved. In addition, the MESFET (JFET) device is more sensitive to the change of the gate bias, so that the double gate semiconductor field effect transistor in the present application can be applied to the sensing field by using this feature, and the application range is increased. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A schematic diagram of a MOSFET structure in the prior art;

[0042] Figure 2 A schematic diagram of a MESFET structure in the prior art;

[0043] Figure 3 A schematic diagram of a MOSFET double gate structure in the prior art;

[0044] Figure 4 A schematic diagram of a structure of a semiconductor field effect transistor of a double gate structure provided by an embodiment of the present application;

[0045] Figure 5A structure diagram of a semiconductor field effect transistor with double gate structure according to another embodiment of the present application is shown in the figure;

[0046] Figure 6 A flow chart of a manufacturing process of a semiconductor field effect transistor with double gate structure according to an embodiment of the present application is shown in the figure;

[0047] Figure 7 A structure diagram of a semiconductor field effect transistor with double gate structure according to another embodiment of the present application is shown in the figure;

[0048] Figure 8 A flow chart of a manufacturing process of a semiconductor field effect transistor with double gate structure according to another embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0049] The application will be further described in details through specific embodiments and with reference to the drawings. In different embodiments, similar elements are denoted by similar reference numerals. In the following embodiments, many details are described in order to make the application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different cases, or can be replaced by other elements, materials, methods. In some cases, some operations related to the application are not shown or described in the specification in order to avoid the core part of the application being overwhelmed by too much description, and it is not necessary to describe these related operations in detail for those skilled in the art according to the description in the specification and general technical knowledge in the art.

[0050] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. At the same time, the steps or actions in the method description can also be sequentially adjusted or adjusted in a manner that is obvious to those skilled in the art. Therefore, the order in the specification and the drawings is only for the purpose of clearly describing a certain embodiment, and does not mean that it is the necessary order, unless otherwise stated that a certain order must be followed.

[0051] The serial numbers of components in this paper, such as "first", "second", etc., are only used to distinguish the described objects, and have no order or technical meaning. Unless otherwise specified, "connection", "coupling" in this application includes direct and indirect connection (coupling).

[0052] MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor;

[0053] MESFET, Metal-Semiconductor Field Effect Transistor, metal-semiconductor field effect transistor;

[0054] JFET, Junction Field-Effect Transistor, junction field effect transistor;

[0055] SS, Subthreshold swing, also known as S factor.

[0056] It can be seen that the current field effect transistor device has the problems of limited working voltage and narrow application range.

[0057] The current field effect transistor includes MOSFET and MESFET (JFET), and the gate structure of MESFET and JFET is Schottky contact, so the structure of MESFET and JFET in the present application can be replaced with each other, for example, the MOSFET structure diagram shown in FIG. 1, the gate structure of the MOSFET includes a gate insulating layer 31 and a gate metal layer 30 on a substrate 10, above an active layer 20, for example, the MESFET gate structure shown in FIG. 2 includes a gate metal layer 30 on a substrate 10, above an active layer 20. Figure 1 Figure 2 Figure 3 As shown in FIG. 3, the double-gate structure in the prior art includes a gate insulating layer 31 / 41 and a gate metal layer 30 / 40 on a substrate 10, on the upper and lower sides of an active layer 20, that is, the upper and lower sides of the active layer 20 of the existing double-gate structure are MOSFET structures, this structure increases the control of the gate on the channel, optimizes the carrier mobility, SS and other parameters of the device, and improves the stability of the device, but due to the gate insulating layer in the MOSFET, the control ability of the gate structure is weakened, and the switching characteristics are relatively poor compared with MESFET (JFET). However, there are still many problems in the current MESFET (JFET) structure, for example, first, the stability of the MESFET (JFET) double-gate structure is very poor, which is not conducive to application, and in the MESFET (JFET) device, when a high work function metal (Pt, Pd, etc.) or a P-type oxide semiconductor (NiO, CuO, etc.) is used to prepare a MESFET or a Schottky diode, the adhesion of the Schottky electrode (gate metal) has certain problems, which also limits the manufacturing and application of the MESFET (JFET) device.

[0058] ​​In the embodiment of the present application, a double-gate semiconductor field effect transistor is provided, which replaces the MOSFET structure of one side of the double-gate device with a MESFET (JFET) structure, so that the SS and switching characteristics of the device are further improved, and the advantages of the MOSFET structure and the MESFET (JFET) structure are combined, so that the operating voltage range of the double-gate device is expanded, the control of the gate on the channel is increased, the carrier mobility, SS and other parameters of the device are optimized, and the stability of the device is improved. In addition, since the double-gate structure device can regulate the threshold voltage of the device, the device can work in a specific situation, compared with the MOSFET structure device, since there is no gate insulating layer in the MESFET (JFET) structure, the SS and switching characteristics of the double-gate device are further improved, and since the MESFET (JFET) device is more sensitive to the change of the gate bias, the double-gate semiconductor field effect transistor in the present application can be applied to the sensing field, thereby increasing the application range.

[0059] Embodiment 1

[0060] Reference Figure 4 and Figure 5 In the embodiment, a double-gate semiconductor field effect transistor is provided, which includes a substrate 100, a first gate 400, a bottom gate insulating layer 401, an active layer 200, and a second gate 300, a source 501 layer and a drain 502 layer on the active layer 200, which are sequentially stacked.

[0061] The substrate 100 in the embodiment is a glass substrate 100, which can also be a plastic substrate 100 or a flexible substrate 100.

[0062] The first gate 400 is located on part of the surface of the substrate 100.

[0063] In the embodiment, the first gate 400 is an ohmic contact metal, which forms an ohmic contact with the substrate 100. For example, the material of the first gate 400 is metal Mo, which is used as the bottom gate electrode in the embodiment.

[0064] The bottom gate insulating layer 401 covers the first gate 400 and contacts the surface of the glass substrate 100. The bottom gate insulating layer 401 is an insulating material, which is silicon oxide, aluminum oxide or silicon nitride in the embodiment, and is used as the insulating material between the first gate 400 and the active layer 200 to reduce the leakage current and stabilize the electrical performance of the device.

[0065] The active layer 200 is located above the oxide layer and on the upper surface of part of the oxide layer.

[0066] The active layer 200 can be a single active layer or a double active layer. For example, when the active layer 200 is a single active layer, the active layer 200 is a-Si, a-IGZO, a-IZO, a-ZTO, a-ITZO, LTPS, an organic material, or a carbon nanotube, as shown in Figure 4 .

[0067] When the active layer 200 is a double active layer, the double active layer is a composite layer of a-IGZO 201 and a-IZO 200, as shown in Figure 5 . When the active layer 200 is a double active layer 200, it can be a combination of any two of the above-mentioned materials for a single active layer. In this embodiment, the combination of a-IGZO 201 and a-IZO 200 is used for a double active layer. A heterojunction two-dimensional electron gas (2DEG) is formed between the composite layer formed by the combination of the two materials, which can further improve the mobility and other performance of the device.

[0068] The second gate 300 is located above the active layer 200.

[0069] The second gate 300 in this embodiment is a high work function metal, such as Pt, Pd, and the like, which forms a Schottky contact with the active layer 200. In this embodiment, the second gate 300 is a top gate electrode.

[0070] The source 501 and drain 502 layers are located on both sides of the second gate 300 and form an ohmic contact with the active layer 200. The source 501 and drain 502 layers can be metal Mo.

[0071] The gate structure formed by the first gate 400 in this embodiment is a MOSFET structure, and the structure formed by the second gate 300 is a MESFET (JFET) structure. This combines the functions of the gate control of the channel in the double-gate structure, optimizes the carrier mobility, SS, and other parameters of the device, and combines the MOSFET structure to improve the stability of the device. At the same time, the MESFET (JFET) structure can realize the function of fast switching, which further improves the SS and switching characteristics. In addition, since the MESFET (JFET) device is more sensitive to changes in gate bias, the double-gate semiconductor field effect transistor in this application can be applied to the sensing field, thereby increasing the application range.

[0072] In this embodiment, a manufacturing method of a double-gate semiconductor field effect transistor is also provided. Please refer to Figure 6 for details. The manufacturing includes:

[0073] Step 1, growing ohmic metal on the substrate and patterning to form the first gate, which is ohmic contact metal.

[0074] The substrate needs to be provided before forming the first gate. The provided substrate can be a rigid material such as silicon, glass, etc., or a flexible material such as PI, PET, etc.

[0075] The first gate can be formed by sputtering or deposition. A layer of first gate metal material is deposited or sputtered on the substrate, and then patterned to form the first gate as the bottom gate electrode.

[0076] The first gate metal material in this embodiment is Mo.

[0077] Step 2, growing a bottom gate insulating layer on the first gate.

[0078] In this embodiment, the bottom gate insulating layer is formed by deposition, which serves as the gate dielectric layer between the first gate and the active layer. The bottom gate insulating layer can be a metal oxide, such as silicon oxide, silicon nitride.

[0079] Step 3, forming an active layer on the bottom gate insulating layer.

[0080] The active layer is formed on the bottom gate insulating layer. The material of the active layer can be a non-metal oxide, which is formed on the bottom gate insulating layer by deposition.

[0081] For example, the material of the active layer can be a-Si, a-IGZO, a-IZO, a-ZTO, a-ITZO, LTPS, organic material or carbon nanotube.

[0082] In some embodiments, the active layer can be a double active layer, i.e. a combination of any two of the above single active layer materials. In this embodiment, it can be a composite layer of a-IGZO and a-IZO. a-IGZO can form a more stable Schottky contact with high work function metal, and a-IZO has a higher carrier concentration, which can improve the working current of the device and further improve the electrical performance of the device.

[0083] Step 4, forming a second gate, a source layer and a drain layer on the active layer, the second gate being a Schottky contact, and the source layer and the drain layer being ohmic contacts.

[0084] A layer of high power function metal, such as Pt, Pd, etc., is formed on the active layer by deposition to form a Schottky contact with the active layer, and then patterned to retain the high power function metal at the predetermined gate position to form the second gate, which serves as the top gate structure of the device.

[0085] Then, an ohmic contact metal, such as metal Mo, is formed on the active layer in a deposition manner, and then is patterned to reserve the ohmic contact metal at the preset source and drain positions to form the source and the drain, thereby forming the semiconductor field effect transistor with the hybrid double-gate structure.

[0086] In some embodiments, a passivation layer is further formed on the above device structure to improve the stability of the device, and the material of the passivation layer can be silicon nitride or silicon oxide.

[0087] By the manufacturing method of the semiconductor field effect transistor with the double-gate structure in the embodiment, the double-gate device with the MOSFET as the bottom gate and the MESFET (JFET) as the top gate is manufactured, the advantages of the MOSFET and the MESFET (JFET) are combined, the parameters of the semiconductor field effect transistor, such as the carrier mobility and the SS, are optimized, and the gate control ability and the electrical performance are better.

[0088] Embodiment 2

[0089] Reference Figure 7 The embodiment provides a semiconductor field effect transistor with a double-gate structure, which comprises a substrate 100, an insulating adhesion layer 500, a first gate 400, an active layer 200, a top gate insulating layer 301, a second gate 300, a source 501 layer and a drain 502 layer which are sequentially stacked.

[0090] The substrate 100 in the embodiment is a glass substrate 100, and the substrate 100 can also be a plastic substrate 100 or a flexible substrate 100.

[0091] The substrate 100 has the insulating adhesion layer 500, and the insulating adhesion layer 500 is located on part of the surface of the substrate 100.

[0092] The insulating adhesion layer 500 in the embodiment is aluminum oxide, and in some embodiments, the insulating adhesion layer 500 can also be silicon nitride.

[0093] The first gate 400 covers the insulating adhesion layer 500, and since the first gate 400 in the embodiment is a high work function metal, the first gate 400 is a MESFET (JFET) structure as the bottom gate structure and is a Schottky contact electrode. In order to solve the adhesion problem of the Schottky contact electrode, the insulating adhesion layer 500 is formed between the first gate 400 and the glass substrate 100 to improve the adhesion of the high work function metal or the P-type oxide semiconductor, so that the MESFET (JFET) device can be manufactured and applied.

[0094] The active layer 200 covers the first gate 400.

[0095] The active layer 200 can be a single active layer 200 or a double active layer 200. For example, when the active layer 200 is a single active layer 200, the active layer 200 is a-Si, a-IGZO, an organic material, a-IZO, a-ZTO, a-ITZO, LTPS, or a carbon nanotube.

[0096] When the active layer 200 is a double active layer 200, the double active layer 200 is a composite layer of a-IGZO and a-IZO.

[0097] When the active layer 200 is a double active layer 200, a heterojunction two-dimensional electron gas (2DEG) is formed between the composite layer of a-IGZO and a-IZO, which can further improve the mobility and other performance of the device.

[0098] The top gate insulating layer 301 and the second gate 300 are sequentially located on part of the active layer 200, forming a MOSFET structure.

[0099] In this embodiment, the top gate insulating layer 301 can be aluminum oxide or silicon nitride.

[0100] The source 501 and drain 502 layers are located on both sides of the second gate 300 and are in ohmic contact with the active layer 200. The source 501 and drain 502 layers can be metal Mo.

[0101] In the double-gate device structure of this embodiment, the gate structure formed by the first gate 400 is a MESFET (JFET) structure as a bottom gate of the double-gate structure. An insulating adhesive layer 500 is provided between the first gate 400 and the substrate 100, solving the problem of manufacturing MESFET (JFET) in the bottom gate structure, enabling the device to switch quickly and improving the SS and switching characteristics. At the same time, the gate structure formed by the second gate 300 as a top gate is a MOSFET structure, which combines the function of the gate controlling the channel in the double-gate structure, optimizes the carrier mobility, SS, and other parameters of the device, and improves the stability of the device due to the MOSFET structure. Since the MESFET (JFET) device is more sensitive to changes in gate bias, the double-gate semiconductor field effect transistor in this application can be applied to the sensing field, increasing the application range.

[0102] In this embodiment, a manufacturing method of a double-gate semiconductor field effect transistor is also provided, which is described in detail in Figure 8 , and the manufacturing includes:

[0103] Step 1: depositing an insulating adhesive layer on a substrate.

[0104] The substrate in the embodiment can be a rigid material such as silicon or glass, or a flexible material such as PI or PET. The insulating adhesive layer can be silicon oxide or silicon nitride, which has good contact with the substrate and can adhere well to the substrate material. In addition, silicon oxide or silicon nitride can form good adhesion with high-power function metals, thereby improving the adhesion between the high-power function metals and the substrate.

[0105] Step 2: Forming a first gate on the insulating adhesive layer.

[0106] The first gate in the embodiment is a high-power function metal, such as Pt or Pd, which is formed by a Schottky contact process as a bottom gate structure in the embodiment.

[0107] Step 3: Forming an active layer on the first gate.

[0108] In the embodiment, a non-metal oxide is deposited on the first gate to form an active layer. The first gate and the active layer are in Schottky contact. The active layer 200 can be one of a-Si, a-IGZO, an organic material, a-IZO, a-ZTO, a-ITZO, LTPS, or a carbon nanotube, or a combination of any two. In the embodiment, a composite layer of a-IGZO and a-IZO is used. a-IGZO can form a more stable Schottky contact with high-power function metals, and a-IZO has a higher carrier concentration, which can improve the working current of the device and further improve the electrical performance of the device.

[0109] Step 4: Forming a top gate insulating layer and a second gate on the active layer in sequence.

[0110] The top gate insulating layer is an insulating medium layer between the second gate and the active layer, which can be a metal oxide such as aluminum oxide or silicon nitride.

[0111] In an embodiment, a layer of metal oxide can be deposited on the active layer, and then patterned to retain the metal oxide at the predetermined second gate position as the top gate insulating layer. Then, an ohmic contact metal such as Mo is formed on the top gate insulating layer to form the second gate.

[0112] In an embodiment, metal oxide and ohmic contact metal can be deposited on the active layer in sequence, and then patterned to etch the metal oxide and ohmic contact metal, and only retain the metal oxide and ohmic contact metal at the predetermined second gate position to form the top gate insulating layer and the second gate.

[0113] Step 5: Forming a source layer and a drain layer.

[0114] The source layer and the drain layer can be formed before the second gate is formed, after the second gate is formed, or simultaneously.

[0115] An ohmic contact metal is deposited on the upper surface of the substrate, then patterned and etched, and the ohmic contact metal at the preset source and drain positions is reserved, wherein the preset source and drain positions are located on both sides of the top gate insulating layer and the second gate, thereby forming the semiconductor field effect transistor with the hybrid double-gate structure in the embodiment.

[0116] In some embodiments, a passivation layer is further formed on the device structure to improve the stability of the device, and the material of the passivation layer can be silicon nitride or silicon oxide.

[0117] The manufacturing method of the semiconductor field effect transistor with the double-gate structure in the embodiment manufactures the double-gate device with the top gate as a MOSFET and the bottom gate as a MESFET (JFET), solves the adhesion problem of the MESFET (JFET) device in the manufacturing process by depositing an insulating adhesion layer on the substrate, and combines the advantages of the MOSFET and the MESFET (JFET), so that the semiconductor field effect transistor has optimized parameters such as carrier mobility and SS, and has good gate control ability and stable electrical performance.

[0118] The above application of specific examples is used to illustrate the present application, which is only used to help understand the present application, and does not limit the present application. For those skilled in the art to which the present application belongs, according to the idea of the present application, several simple deductions, deformations or substitutions can be made.

Claims

1. A semiconductor field effect transistor of double gate structure, characterized by, include: substrate; A first gate, the first gate being located on a portion of the surface of the substrate; A bottom gate insulating layer, which covers the first gate and contacts the remaining portion of the glass substrate surface; The active layer is located above the bottom gate insulating layer; The second gate is located above the active layer; The source layer and drain layer are located on both sides of the second gate and are in ohmic contact with the active layer.

2. The semiconductor field effect transistor of claim 1, wherein, The first gate is an ohmic contact metal, and the second gate is a high work function metal.

3. The semiconductor field effect transistor of claim 1, wherein the gate electrode is formed of a material selected from the group consisting of titanium, platinum, iridium, ruthenium, palladium, gold, silver, and alloys thereof. The bottom gate insulating layer is made of aluminum oxide, silicon nitride, or silicon oxide.

4. The semiconductor field effect transistor of claim 1, wherein the gate electrode is formed of a material selected from the group consisting of titanium, platinum, iridium, ruthenium, and alloys thereof. The active layer can be a single active layer or a dual active layer; When the active layer is a single active layer, the active layer is a-Si, a-IGZO, a-IZO, a-ZTO, a-ITZO, LTPS, organic materials, or carbon nanotubes; when the active layer is a dual active layer, the dual active layer is a composite layer of a-IGZO and a-IZO.

5. A semiconductor field effect transistor of double gate structure, characterized by include: substrate; An insulating adhesive layer is located on a portion of the surface of the substrate; A first gate, the first gate covering the insulating adhesive layer; An active layer covers the first gate. A top gate insulating layer is located on a portion of the active layer; The second gate is located above the active layer; The source layer and drain layer are located on both sides of the second gate and are in ohmic contact with the active layer.

6. The semiconductor field effect transistor of claim 5, wherein the gate electrode is formed of a material selected from the group consisting of titanium, platinum, gold, silver, copper, aluminum, and alloys thereof. The first gate is a high work function metal, and the second gate is an ohmic contact metal.

7. The semiconductor field effect transistor of claim 5 wherein the gate electrode is formed of a material selected from the group consisting of aluminum, titanium, chromium, nickel, copper, silver, gold, platinum, and alloys thereof. The insulating adhesive layer is aluminum oxide, silicon nitride, or silicon oxide.

8. The semiconductor field effect transistor of claim 5, wherein the gate electrode is formed of a material selected from the group consisting of titanium, platinum, gold, silver, copper, aluminum, and alloys thereof. The active layer can be a single active layer or a dual active layer; When the active layer is a single active layer, the active layer is a-Si, a-IGZO, a-IZO, a-ZTO, a-ITZO, LTPS, organic materials, or carbon nanotubes; when the active layer is a dual active layer, the dual active layer is a composite layer of a-IGZO and a-IZO.

9. A method of manufacturing a semiconductor field effect transistor of double gate structure, characterized by, include: An ohmic contact metal is grown and patterned on a substrate to form the first gate; A bottom gate insulating layer is grown on the first gate; An active layer is formed on the bottom gate insulating layer; A second gate, a source layer, and a drain layer are formed above the active layer. The second gate is a Schottky contact, and the source and drain layers are ohmic contacts.

10. A method of manufacturing a semiconductor field effect transistor of double gate structure, characterized by, include: An insulating adhesion layer is deposited on the substrate; A high work function metal is deposited on the insulating adhesion layer to form a first gate; An active layer is formed on the first gate, the active layer covering the first gate; A top gate insulating layer and a second gate are sequentially formed on the active layer; A source layer and a drain layer are formed, which are located on both sides of the top gate insulating layer and the second gate, respectively, and the source layer and drain layer are in ohmic contact with the active layer.

Images