Memristor and manufacturing method thereof

Abstract

The application provides a memristor and a manufacturing method thereof, which comprises a substrate, a lower electrode with TiN material located on the substrate, wherein the ratio of N component and Ti component of the lower electrode is 0.96-1.1, including the end point value, a resistance change layer located on the side of the lower electrode away from the substrate, and an upper electrode located on the side of the resistance change layer away from the substrate. According to the above content, the technical scheme provided by the application adjusts the component ratio of Ti and N in the lower electrode of the memristor to 0.96-1.1, and then optimizes the resistivity and thermoelectric conductivity of the lower electrode, so that the memristor forms a self-heating effect in the programming process. Further, the thermoelectric coupling effect is adopted to reduce the defect formation energy of the resistance change layer through the thermal field assistance of the lower electrode, improve the defect formation probability, reduce the required electric field intensity in the programming process, and achieve the purpose of reducing the programming voltage, thereby improving the reliability of the memristor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a memristor and a method for manufacturing the same. Background Technology

[0002] Resistive random access memory (RRAM) is a novel non-volatile memory technology with a simple metal-insulator-metal sandwich structure. It is fully compatible with traditional CMOS (Complementary Metal-Oxide-Semiconductor) back-end processes and features low operating voltage and good reliability. It holds significant promise for applications in embedded memory, logic circuits, and neuromorphic computing.

[0003] Under the excitation of an external electric field, conductive filaments form and break in the dielectric layer of a resistive random access memory (IRRAM), with their resistance cyclically switching between high and low resistance states. The first formation of conductive filaments in IRRAM is called the forming process, which generally requires a relatively high voltage, Vforming. For some individual devices, Vforming can reach 3.5V or even higher, while Vforming in an array can reach 4.5V. This is mismatched with the highest voltages provided by currently used CMOS process nodes. For example, the highest operating voltage of a MOSFET in a 28nm process is 1.8V, while in more advanced processes, the operating voltage is even lower. Therefore, in practical circuits, multiple voltages need to be provided to meet the operating requirements of different devices, thus increasing circuit complexity. In other words, an excessively high operating voltage, especially the Vforming voltage, can lead to problems with the compatibility and uniformity of operating voltages, affecting the practical application of IRRAM and hindering its reliability. Summary of the Invention

[0004] In view of this, the present invention provides a memristor and a method for manufacturing the same, which effectively solves the technical problems existing in the prior art, achieves the purpose of reducing the programming voltage, and thus improves the reliability of the memristor.

[0005] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0006] A memristor, comprising:

[0007] Substrate;

[0008] A lower electrode located on the substrate and made of TiN, wherein the ratio of N component to Ti component in the lower electrode is 0.96-1.1, including the endpoint values;

[0009] A resistive switching layer located on the side of the lower electrode opposite to the substrate;

[0010] The upper electrode is located on the side of the resistive switching layer opposite to the substrate.

[0011] Optionally, the resistivity of the lower electrode is 250-350 μΩ·cm, including the endpoint value;

[0012] Furthermore, the thermal conductivity of the lower electrode is 55-70 W / m·℃.

[0013] Optionally, the thickness of the lower electrode ranges from 20 to 500 nm, including the endpoint values;

[0014] And, the thickness of the upper electrode ranges from 20 to 500 nm, including the endpoint values.

[0015] Optionally, the upper electrode is made of Ir, Al, Ru, Pd, TiN or TaN.

[0016] Optionally, the resistive switching layer is made of a binary metal oxide.

[0017] Optionally, the binary metal oxide is HfO. x Ta2O5, Al2O3, WO x TiO x Or CuO.

[0018] Optionally, the memristor further includes an intercalation layer located between the resistive switching layer and the upper electrode, the intercalation layer being a metal layer or a semiconductor layer.

[0019] Optionally, the memristor is a resistive random access memory (RRAM).

[0020] Accordingly, the present invention also provides a method for fabricating a memristor, comprising:

[0021] Provide substrate;

[0022] A lower electrode made of TiN is formed on the substrate, wherein the ratio of N component to Ti component in the lower electrode is 0.96-1.1, including the endpoint values;

[0023] A resistive switching layer is formed on the side of the lower electrode opposite to the substrate;

[0024] An upper electrode is formed on the side of the resistive switching layer opposite to the substrate.

[0025] Optionally, a lower electrode made of TiN is formed on the substrate, including:

[0026] When forming the lower electrode on the substrate, N gas and Ar gas are introduced, wherein the flow rates of N gas and Ar gas are in the range of 8 sccm: 50 sccm to 8 sccm: 35 sccm, including the endpoint values.

[0027] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0028] This invention provides a memristor and a method for fabricating the same, comprising: a substrate; a lower electrode located on the substrate and made of TiN, wherein the ratio of N component to Ti component in the lower electrode is 0.96-1.1, including endpoint values; a resistive switching layer located on the side of the lower electrode opposite to the substrate; and an upper electrode located on the side of the resistive switching layer opposite to the substrate.

[0029] As described above, the technical solution provided by this invention optimizes the resistivity and thermal conductivity of the lower electrode of the memristor by adjusting the Ti-N composition ratio to 0.96-1.1, thereby enabling the memristor to generate a self-heating effect during programming. Furthermore, by employing thermoelectric coupling, the defect formation energy of the resistive switching layer is reduced through the thermal field assistance of the lower electrode, increasing the defect formation probability and reducing the electric field strength required during programming, thus lowering the programming voltage and improving the reliability of the memristor. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a memristor provided in an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of another memristor structure provided in an embodiment of the present invention;

[0033] Figure 3 A flowchart illustrating another method for fabricating a memristor provided in this embodiment of the invention;

[0034] Figure 4 A flowchart illustrating yet another method for fabricating a memristor provided in this embodiment of the invention;

[0035] Figures 5a-5d for Figure 3 The corresponding structural diagrams for each step in the process. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] As described in the background section, under the excitation of an external electric field, conductive filaments form and break in the dielectric layer of a resistive random access memory (IRRAM), with their resistance cyclically switching between high and low resistance states. The initial formation of these conductive filaments in IRRAM is called the forming process, which generally requires a relatively high voltage, Vforming. For some individual devices, Vforming can reach 3.5V or even higher, while Vforming in an array can reach 4.5V. This is mismatched with the highest voltages provided by currently used CMOS process nodes. For example, the highest operating voltage of a MOSFET in a 28nm process is 1.8V, while in more advanced processes, the operating voltage is even lower. Therefore, in practical circuits, multiple voltages are needed to meet the operating requirements of different devices, increasing circuit complexity. In other words, an excessively high operating voltage, especially Vforming, in IRRAM can lead to problems with the compatibility and uniformity of the operating voltage, affecting the practical application of IRRAM and hindering its reliability.

[0038] Based on this, embodiments of the present invention provide a memristor and its manufacturing method, effectively solving the technical problems existing in the prior art, achieving the purpose of reducing the programming voltage, and thus improving the reliability of the memristor.

[0039] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 5d The technical solutions provided in the embodiments of the present invention will be described in detail.

[0040] refer to Figure 1 The diagram shown is a structural schematic of a memristor provided in an embodiment of the present invention. The memristor provided in this embodiment includes:

[0041] Substrate 100.

[0042] A lower electrode 200 located on the substrate 100 and made of TiN, wherein the ratio of N component to Ti component of the lower electrode 200 is 0.96-1.1, including the endpoint values.

[0043] The resistive switching layer 300 is located on the side of the lower electrode 200 opposite to the substrate 100.

[0044] The upper electrode 400 is located on the side of the resistive switching layer 300 opposite to the substrate 100.

[0045] Understandably, a forming process is typically required for a memristor to trigger the resistance switching behavior in subsequent cycles. This forming process can be understood as a soft breakdown process under the influence of electric field and thermal effects, mainly related to the generation of oxygen ions and oxygen vacancies. Oxygen vacancies can be understood as defects in the material, and the probability of defect formation in the resistive switching layer is related to the electric field voltage and temperature. Specifically, when the electric field voltage is the same, the probability of defect formation increases with increasing temperature; conversely, when the temperature is the same, the probability of defect formation increases with increasing electric field voltage.

[0046] Based on the above principles, the technical solution provided in this embodiment of the invention optimizes the resistivity and thermal conductivity of the lower electrode of the memristor by adjusting the Ti-N composition ratio to 0.96-1.1, thereby enabling the memristor to form a self-heating effect during programming. Furthermore, by employing the thermoelectric coupling effect and using the thermal field assistance of the lower electrode to reduce the defect formation energy of the resistive switching layer, the probability of defect formation is increased, the electric field strength required during programming is reduced, and the programming voltage is lowered, thereby improving the reliability of the memristor.

[0047] In one embodiment of the present invention, the resistivity of the lower electrode provided in the embodiment of the present invention can be 250-350 uΩ·cm, including the endpoint value.

[0048] Furthermore, the thermal conductivity of the lower electrode can be 55-70 W / m·℃.

[0049] Optionally, the thickness range of the lower electrode provided in this embodiment of the invention is 20-500 nm, including the endpoint values.

[0050] And, the thickness of the upper electrode ranges from 20 to 500 nm, including the endpoint values.

[0051] In one embodiment of the present invention, the material of the upper electrode provided by the present invention is Ir, Al, Ru, Pd, TiN or TaN, etc.

[0052] In one embodiment of the present invention, the resistive switching layer provided in this embodiment is made of a binary metal oxide. The binary metal oxide provided in this embodiment can be HfO. x Ta2O5, Al2O3, WO x TiO x Alternatively, CuO; or, the resistive switching layer provided in the embodiments of the present invention can be some organic resistive switching materials.

[0053] refer to Figure 2The diagram shown is a schematic diagram of another memristor provided in an embodiment of the present invention. The memristor provided by the present invention further includes an intercalation layer 500 located between the resistive switching layer 300 and the upper electrode 400. The intercalation layer 500 is a metal layer or a semiconductor layer.

[0054] Understandably, the intercalation layer provided in this embodiment of the invention is used to provide a higher initial oxygen vacancy defect concentration, which is beneficial for reducing the operating voltage of the memristor. The intercalation layer provided in this embodiment of the invention is conductive and can be a metal layer or a semiconductor layer. Specifically, the intercalation layer can be Ta, Ti, etc., or amorphous silicon, amorphous C, graphene, etc.

[0055] In one embodiment of the present invention, the memristor provided by the present invention can be a resistive random access memory (RRAM), but the present invention does not impose specific limitations on it, and it can also be other types of devices.

[0056] Accordingly, embodiments of the present invention also provide a method for fabricating a memristor. For example... Figure 3 The diagram shows a flowchart of a method for fabricating a memristor according to an embodiment of the present invention, wherein the fabrication method includes:

[0057] S1, Provide a substrate.

[0058] S2. A lower electrode made of TiN is formed on the substrate, wherein the ratio of N component to Ti component in the lower electrode is 0.96-1.1, including the endpoint values.

[0059] S3. A resistive switching layer is formed on the side of the lower electrode away from the substrate.

[0060] S4. An upper electrode is formed on the side of the resistive switching layer opposite to the substrate.

[0061] Understandably, a forming process is typically required for a memristor to trigger the resistance switching behavior in subsequent cycles. This forming process can be understood as a soft breakdown process under the influence of electric field and thermal effects, mainly related to the generation of oxygen ions and oxygen vacancies. Oxygen vacancies can be understood as defects in the material, and the probability of defect formation in the resistive switching layer is related to the electric field voltage and temperature. Specifically, when the electric field voltage is the same, the probability of defect formation increases with increasing temperature; conversely, when the temperature is the same, the probability of defect formation increases with increasing electric field voltage.

[0062] Based on the above principles, the technical solution provided in this embodiment of the invention optimizes the resistivity and thermal conductivity of the lower electrode of the memristor by adjusting the Ti-N composition ratio to 0.96-1.1, thereby enabling the memristor to form a self-heating effect during programming. Furthermore, by employing the thermoelectric coupling effect and using the thermal field assistance of the lower electrode to reduce the defect formation energy of the resistive switching layer, the probability of defect formation is increased, the electric field strength required during programming is reduced, and the programming voltage is lowered, thereby improving the reliability of the memristor.

[0063] To adjust the Ti and N composition in the lower electrode and thus achieve suitable resistivity and thermal conductivity, a lower electrode made of TiN is formed on the substrate, comprising:

[0064] When forming the lower electrode on the substrate, N gas and Ar gas are introduced, wherein the flow rates of N gas and Ar gas are in the range of 8 sccm:50 sccm to 8 sccm:35 sccm, including the endpoint values. By introducing a certain amount of inert gas Ar, plasma can be generated through glow discharge at low pressure, thereby increasing the thin film deposition rate, while simultaneously achieving the purpose of adjusting the N gas concentration.

[0065] Specifically, such as Figure 4 The diagram shows a flowchart of another method for fabricating a memristor according to an embodiment of the present invention, wherein the fabrication method includes:

[0066] S1, Provide a substrate.

[0067] S2. A lower electrode made of TiN is formed on the substrate, wherein the ratio of N component to Ti component in the lower electrode is 0.96-1.1, including the endpoint values. During the formation of the lower electrode on the substrate, N gas and Ar gas are introduced, wherein the flow rates of N gas and Ar gas are in the range of 8 sccm:50 sccm to 8 sccm:35 sccm, including the endpoint values.

[0068] S3. A resistive switching layer is formed on the side of the lower electrode away from the substrate.

[0069] S4. An upper electrode is formed on the side of the resistive switching layer opposite to the substrate.

[0070] The following is combined Figures 5a to 5d The preparation method provided in the embodiments of the present invention will be described in more detail. Figures 5a-5d for Figure 3 The corresponding structural diagrams for each step in the process.

[0071] like Figure 5a As shown, in step S1, a substrate 100 is provided.

[0072] like Figure 5bAs shown, corresponding to step S2, a lower electrode 200 made of TiN is formed on the substrate 100, wherein the ratio of N component to Ti component of the lower electrode 200 is 0.96-1.1, including the endpoint values.

[0073] In one embodiment of the present invention, the lower electrode provided by the present invention can be prepared by processes such as sputtering, atomic layer deposition, physical vapor deposition or chemical vapor deposition.

[0074] In one embodiment of the present invention, the resistivity of the lower electrode provided in this embodiment can be 250-350 μΩ·cm, including the endpoint values. Furthermore, the thermal conductivity of the lower electrode can be 55-70 W / m·℃. The thickness of the lower electrode provided in this embodiment ranges from 20-500 nm, including the endpoint values.

[0075] To adjust the Ti and N composition in the lower electrode and thus achieve suitable resistivity and thermal conductivity, a lower electrode made of TiN is formed on the substrate, comprising:

[0076] When forming the lower electrode on the substrate, N gas and Ar gas are introduced, wherein the flow rates of N gas and Ar gas are in the range of 8 sccm:50 sccm to 8 sccm:35 sccm, including the endpoint values. By introducing a certain amount of inert gas Ar, plasma can be generated through glow discharge at low pressure, thereby increasing the thin film deposition rate, while simultaneously achieving the purpose of adjusting the N gas concentration.

[0077] like Figure 5c As shown, corresponding to step S3, a resistive switching layer 300 is formed on the side of the lower electrode 200 away from the substrate 100.

[0078] In one embodiment of the present invention, the resistive switching layer provided in this embodiment is made of a binary metal oxide. The binary metal oxide provided in this embodiment can be HfO. x Ta2O5, Al2O3, WO x TiO x Alternatively, CuO; or, the resistive switching layer provided in the embodiments of the present invention can be some organic resistive switching materials.

[0079] like Figure 5d As shown, corresponding to step S4, an upper electrode 400 is formed on the side of the resistive switching layer 300 away from the substrate 100.

[0080] In one embodiment of the present invention, the thickness of the upper electrode provided by the present invention ranges from 20 to 500 nm, including the endpoint values. The material of the upper electrode provided by the present invention is Ir, Al, Ru, Pd, TiN, or TaN, etc.

[0081] This invention provides a memristor and its fabrication method, comprising: a substrate; a lower electrode located on the substrate and made of TiN, wherein the ratio of N component to Ti component in the lower electrode is 0.96-1.1, including endpoint values; a resistive switching layer located on the side of the lower electrode opposite to the substrate; and an upper electrode located on the side of the resistive switching layer opposite to the substrate.

[0082] As described above, the technical solution provided by this invention optimizes the resistivity and thermal conductivity of the lower electrode by adjusting the Ti-N composition ratio in the lower electrode of the memristor to 0.96-1.1, thereby enabling the memristor to generate a self-heating effect during programming. Furthermore, by employing thermoelectric coupling, the defect formation energy of the resistive switching layer is reduced through the thermal field assistance of the lower electrode, increasing the defect formation probability and reducing the electric field strength required during programming, thus achieving the goal of reducing the programming voltage and improving the reliability of the memristor.

[0083] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memristor, characterized in that, include: Substrate; A lower electrode located on the substrate and made of TiN, wherein the ratio of N component to Ti component in the lower electrode is 0.96-1.1, including endpoint values; forming the lower electrode made of TiN on the substrate includes: when forming the lower electrode on the substrate, introducing N gas and Ar gas, wherein the flow rates of N gas and Ar gas are in the range of 8sccm:50scccm-8sccm:35scccm, including endpoint values; A resistive switching layer located on the side of the lower electrode opposite to the substrate; The upper electrode is located on the side of the resistive switching layer opposite to the substrate; The resistivity of the lower electrode is 250-350 uΩ·cm, including the endpoint value; Furthermore, the thermal conductivity of the lower electrode is 55-70 W / m·℃, which causes the memristor to generate a self-heating effect during programming.

2. The memristor according to claim 1, characterized in that, The thickness of the lower electrode ranges from 20 to 500 nm, including the endpoint values; And, the thickness of the upper electrode ranges from 20 to 500 nm, including the endpoint values.

3. The memristor according to claim 1, characterized in that, The material of the upper electrode is Ir, Al, Ru, Pd, TiN or TaN.

4. The memristor according to claim 1, characterized in that, The resistive switching layer is made of binary metal oxide.

5. The memristor according to claim 4, characterized in that, The binary metal oxide is HfO. x Ta2O5, Al2O3, WO x TiO x Or CuO.

6. The memristor according to claim 1, characterized in that, The memristor further includes an intercalation layer located between the resistive switching layer and the upper electrode, the intercalation layer being a metal layer or a semiconductor layer.

7. The memristor according to claim 1, characterized in that, The memristor is a resistive random access memory.

8. A method for fabricating a memristor, characterized in that, The method for preparing the memristor is used to prepare the memristor according to any one of claims 1-7, comprising: Provide substrate; A lower electrode made of TiN is formed on the substrate, wherein the ratio of N component to Ti component in the lower electrode is 0.96-1.1, including the endpoint values; the resistivity of the lower electrode is 250-350 uΩ·cm, including the endpoint values; and the thermal conductivity of the lower electrode is 55-70 W / m·℃. A resistive switching layer is formed on the side of the lower electrode opposite to the substrate; An upper electrode is formed on the side of the resistive switching layer opposite to the substrate.

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