In-memory computing unit and in-memory computing circuit with reconfigurable logic functions

Abstract

The present invention provides a memory - in - computing integrated circuit with reconfigurable logic functions. The circuit includes: a cascaded input stage and N output stages. The input stage includes 2<supgt;N< / supgt> STT - MTJs. The number of STT - MTJs in each subsequent stage is half of the number of STT - MTJs in its previous stage. Two STT - MTJs in the previous stage and one STT - MTJ in the subsequent stage form a memory - in - computing unit with two inputs and one output. Through different configuration conditions, each memory - in - computing unit with two inputs and one output is used to implement four logics: "NAND", "NOR", "AND", and "OR". The present invention can achieve data storage and logic calculation under the same circuit architecture and can also achieve different logic function reconfigurations.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a memory - in - computing unit and a memory - in - computing circuit with reconfigurable logic functions. Background Art

[0002] With the advent of the era of artificial intelligence, image recognition has become one of the essential capabilities of intelligent systems. Image recognition generally consists of two major modules: feature extraction and classification, and edge extraction of images is one of the most widely used methods in feature extraction.

[0003] Commonly used image edge extraction operators include Robert operator, Sobel operator, Prewitt operator, Kirsch operator, Robinson operator, Canny operator, etc. The specific implementation circuits of each operator are limited by device characteristics and circuit architectures, and the storage and the processor are separated. Therefore, problems such as "memory wall" and "power consumption wall" exist, and the functions are single. Summary of the Invention

[0004] To solve the above problems, the present invention provides a memory - in - computing unit and a memory - in - computing circuit with reconfigurable logic functions, which can realize data storage and logical calculation under the same circuit architecture and can realize different reconfigurations of logical functions.

[0005] On the one hand, the present invention provides a memory - in - computing unit with two inputs and one output, including: two input STT - MTJs and one output STT - MTJ, wherein,

[0006] The free - layer sides of the two input STT - MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage;

[0007] The reference - layer sides of the two input STT - MTJs are connected to the reference - layer side of the output STT - MTJ;

[0008] The free - layer side of the output STT - MTJ is used as the ground terminal and is connected to the negative end of the operating voltage;

[0009] Or, the reference - layer sides of the two input STT - MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage;

[0010] The free - layer sides of the two input STT - MTJs are connected to the free - layer side of the output STT - MTJ;

[0011] The reference - layer side of the output STT - MTJ is used as the ground terminal and is connected to the negative end of the operating voltage.

[0012] Optionally, the memory - in - computing unit with two inputs and one output is used to implement four logics of "NAND", "NOR", "AND" and "OR",

[0013] If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input terminal and the ground terminal is between 0.0731 V and 0.0908 V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:1, the two-input single-output memory-computation integrated unit implements a NAND logic;

[0014] If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input terminal and the ground terminal is between 0.0650 V and 0.0730 V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:1, the two-input single-output memory-computation integrated unit implements a NOR logic;

[0015] If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.202 V and 0.195 V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:0.5, the two-input single-output memory-computation integrated unit implements an AND logic;

[0016] If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.211 V and 0.205 V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:0.7, the two-input single-output memory-computation integrated unit implements an OR logic.

[0017] On the other hand, the present invention provides a memory-computation integrated circuit with reconfigurable logic functions, including: an input stage, including 2 N STT-MTJs, each STT-MTJ stores 1-bit data respectively;

[0018] N-level output stages, where the first-level output stage includes 2 N-1 STT-MTJs, and the subsequent output stages satisfy that the number of STT-MTJs included in the subsequent output stage is half of the number of STT-MTJs included in its previous output stage until the Nth-level output stage only includes one STT-MTJ;

[0019] A plurality of switches, the plurality of switches are arranged between the input stage and the first-level output stage and between the output stages, and are used to configure the connection mode between the STT-MTJs in the input stage and the first-level output stage and the connection mode between the STT-MTJs in the output stages;

[0020] In the input stage, every two STT-MTJs form a group, which corresponds one-to-one with one STT-MTJ in the first-stage output stage. By configuring the switches between the input stage and the first-stage output stage, 2 N-1 memory-computation integrated units with two inputs and one output are formed. Two STT-MTJs in the input stage serve as two input STT-MTJs, and one STT-MTJ in the first-stage output stage serves as the output STT-MTJ. The free layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage; the reference layer sides of the two input STT-MTJs are connected to the reference layer side of the output STT-MTJ; the free layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage; or, the reference layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage; the free layer sides of the two input STT-MTJs are connected to the free layer side of the output STT-MTJ; the reference layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage;

[0021] In the N-stage output stage, every two STT-MTJs in the previous-stage output stage form a group, which corresponds one-to-one with one STT-MTJ in the next-stage output stage. By configuring the switches between the previous-stage output stage and the next-stage output stage, memory-computation integrated units with two inputs and one output, the number of which is equal to the number of STT-MTJs in the next-stage output stage, are formed. Two STT-MTJs in the previous-stage output stage serve as two input STT-MTJs, and one STT-MTJ in the next-stage output stage serves as the output STT-MTJ. The free layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage; the reference layer sides of the two input STT-MTJs are connected to the reference layer side of the output STT-MTJ; the free layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage; or, the reference layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage; the free layer sides of the two input STT-MTJs are connected to the free layer side of the output STT-MTJ; the reference layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage.

[0022] Optionally, any memory-computation integrated unit with two inputs and one output is used to implement four logics of "NAND", "NOR", "AND", and "OR".

[0023] If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input terminal and the ground terminal is between 0.0731V and 0.0908V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:1, the two-input single-output memory-computation integrated unit implements the "NAND" logic;

[0024] If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input terminal and the ground terminal is between 0.0650V and 0.0730V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:1, the two-input single-output memory-computation integrated unit implements the "NOR" logic;

[0025] If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.202V and 0.195V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:0.5, the two-input single-output memory-computation integrated unit implements the "AND" logic;

[0026] If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.211V and 0.205V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:0.7, the two-input single-output memory-computation integrated unit implements the "OR" logic.

[0027] Optionally, the memory-computation integrated circuit with reconfigurable logic functions has 4 to the power of n reconfiguration possibilities, where n represents the number of two-input single-output memory-computation integrated units.

[0028] Optionally, the switch is a single-pole single-throw electronic switch or a single-pole double-throw electronic switch.

[0029] Optionally, it includes:

[0030] An input stage, including the first STT-MTJ, the second STT-MTJ, the third STT-MTJ, the fourth STT-MTJ, the fifth STT-MTJ, the sixth STT-MTJ, the seventh STT-MTJ, and the eighth STT-MTJ, a total of 8 STT-MTJs, and each STT-MTJ stores 1 bit of data;

[0031] The first-level output stage, including the ninth STT-MTJ, the tenth STT-MTJ, the eleventh STT-MTJ, and the twelfth STT-MTJ, a total of 4 STT-MTJs;

[0032] The second-level output stage includes the thirteenth STT-MTJ and the fourteenth STT-MTJ, a total of 2 STT-MTJs;

[0033] The third-level output stage includes the fifteenth STT-MTJ, a total of 1 STT-MTJ;

[0034] And, the first switch to the sixteenth switch, a total of 16 switches;

[0035] Every two STT-MTJs in the input stage form a group and correspond one-to-one with one STT-MTJ in the first-level output stage, constituting a total of 4 memory-computation integrated units with two inputs and one output. Among them,

[0036] The first STT-MTJ, the fourth STT-MTJ, and the ninth STT-MTJ form the first memory-computation integrated unit. The free layer sides of the first STT-MTJ and the fourth STT-MTJ are used as voltage input terminals and are connected to the first operating voltage. The reference layer sides of the first STT-MTJ and the fourth STT-MTJ are connected to the reference layer side of the ninth STT-MTJ through the first switch, and the free layer side of the ninth STT-MTJ is grounded through the ninth switch;

[0037] The second STT-MTJ, the third STT-MTJ, and the tenth STT-MTJ form the second memory-computation integrated unit. The free layer sides of the second STT-MTJ and the third STT-MTJ are used as voltage input terminals and are connected to the first operating voltage. The reference layer sides of the second STT-MTJ and the third STT-MTJ are connected to the reference layer side of the tenth STT-MTJ through the fourth switch, and the free layer side of the tenth STT-MTJ is grounded through the twelfth switch;

[0038] The fifth STT-MTJ, the eighth STT-MTJ, and the eleventh STT-MTJ form the third memory-computation integrated unit. The free layer sides of the fifth STT-MTJ and the eighth STT-MTJ are used as voltage input terminals and are connected to the first operating voltage. The reference layer sides of the fifth STT-MTJ and the eighth STT-MTJ are connected to the reference layer side of the eleventh STT-MTJ through the fifth switch, and the free layer side of the eleventh STT-MTJ is grounded through the thirteenth switch;

[0039] The sixth STT-MTJ, the seventh STT-MTJ, and the twelfth STT-MTJ form the fourth memory-computation integrated unit. The free layer sides of the sixth STT-MTJ and the seventh STT-MTJ are used as voltage input terminals and are connected to the first operating voltage. The reference layer sides of the sixth STT-MTJ and the seventh STT-MTJ are connected to the reference layer side of the twelfth STT-MTJ through the eighth switch, and the free layer side of the twelfth STT-MTJ is grounded through the sixteenth switch;

[0040] In the first-level output stage, every two STT-MTJs form a group, which corresponds one-to-one with one STT-MTJ in the second-level output stage, and together they form two memory-computation integrated units with two inputs and one output. Among them,

[0041] The ninth STT-MTJ, the tenth STT-MTJ and the thirteenth STT-MTJ form the fifth memory-computation integrated unit. The reference layer sides of the ninth STT-MTJ and the tenth STT-MTJ serve as voltage input terminals. The reference layer side of the ninth STT-MTJ is connected to the second operating voltage through the second switch, and the reference layer side of the tenth STT-MTJ is connected to the second operating voltage through the third switch. The free layer side of the ninth STT-MTJ is connected to the free layer side of the thirteenth STT-MTJ through the tenth switch, and the free layer side of the tenth STT-MTJ is connected to the free layer side of the thirteenth STT-MTJ through the eleventh switch;

[0042] The eleventh STT-MTJ, the twelfth STT-MTJ and the fourteenth STT-MTJ form the sixth memory-computation integrated unit. The reference layer sides of the eleventh STT-MTJ and the twelfth STT-MTJ serve as voltage input terminals. The reference layer side of the eleventh STT-MTJ is connected to the second operating voltage through the sixth switch, and the reference layer side of the twelfth STT-MTJ is connected to the second operating voltage through the seventh switch. The free layer side of the eleventh STT-MTJ is connected to the free layer side of the fourteenth STT-MTJ through the fourteenth switch, and the free layer side of the twelfth STT-MTJ is connected to the free layer side of the fourteenth STT-MTJ through the fifteenth switch;

[0043] Two STT-MTJs in the second-level output stage and one STT-MTJ in the third-level output stage form the seventh memory-computation integrated unit with two inputs and one output. Among them,

[0044] The free layer sides of the thirteenth STT-MTJ and the fourteenth STT-MTJ serve as voltage input terminals. The reference layer sides of the thirteenth STT-MTJ and the fourteenth STT-MTJ are connected to the reference layer side of the fifteenth STT-MTJ, and the free layer side of the fifteenth STT-MTJ is grounded.

[0045] Optionally, if the first STT-MTJ stores data A, the second STT-MTJ stores the inversion of data A, the third STT-MTJ stores data D, the fourth STT-MTJ stores the inversion of data D, the fifth STT-MTJ stores data C, the sixth STT-MTJ stores the inversion of data C, the seventh STT-MTJ stores data B, the eighth STT-MTJ stores the inversion of data B, and the first arithmetic-in-memory unit, the second arithmetic-in-memory unit, the third arithmetic-in-memory unit, and the fourth arithmetic-in-memory unit are configured to implement an "AND" logic, and the fifth arithmetic-in-memory unit, the sixth arithmetic-in-memory unit, and the seventh arithmetic-in-memory unit are configured to implement an "OR" logic, then the arithmetic-in-memory circuit with reconfigurable logic functions is specifically used to implement the first-order Robert operator.

[0046] Optionally, if the first STT-MTJ stores the inversion of data C, the second STT-MTJ stores data A, the third STT-MTJ stores the inversion of data B, the fourth STT-MTJ stores data A, the fifth STT-MTJ stores data B, the sixth STT-MTJ stores the inversion of data A, the seventh STT-MTJ stores data C, the eighth STT-MTJ stores the inversion of data A, and the first arithmetic-in-memory unit, the second arithmetic-in-memory unit, the third arithmetic-in-memory unit, the fourth arithmetic-in-memory unit, the fifth arithmetic-in-memory unit, and the sixth arithmetic-in-memory unit are configured to implement a "NOR" logic, and the seventh arithmetic-in-memory unit is configured to implement a "NAND" logic, then the arithmetic-in-memory circuit with reconfigurable logic functions is specifically used to implement the gradient operator;

[0047] If the first STT-MTJ stores the inversion of data D, the second STT-MTJ stores data C, the third STT-MTJ stores the inversion of data C, the fourth STT-MTJ stores data B, the fifth STT-MTJ stores the inversion of data B, the sixth STT-MTJ stores data A, the seventh STT-MTJ stores data D, the eighth STT-MTJ stores the inversion of data A, and the first arithmetic-in-memory unit, the second arithmetic-in-memory unit, the third arithmetic-in-memory unit, the fourth arithmetic-in-memory unit, the fifth arithmetic-in-memory unit, and the sixth arithmetic-in-memory unit are configured to implement a "NOR" logic, and the seventh arithmetic-in-memory unit is configured to implement a "NAND" logic, then the arithmetic-in-memory circuit with reconfigurable logic functions is specifically used to implement the basic operator.

[0048] The in-memory computing circuit structure provided by the present invention is such that each logic operation unit is composed of in-memory computing units with two inputs and one output. The input data, logic operation, and operation result are all stored in the same circuit architecture, so there is no need to access an additional memory. In addition, in the same architecture, the original input data, the operation paradigm for image edge extraction, and the output result data are all stored, realizing in-memory computing integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of an in-memory computing unit with two inputs and one output according to an embodiment of the present invention;

[0050] Figure 2 It is a schematic diagram of an in-memory computing unit with two inputs and one output according to an embodiment of the present invention;

[0051] Figure 3 It is a schematic diagram of an in-memory computing circuit with reconfigurable logic functions according to an embodiment of the present invention;

[0052] Figure 4 It is a schematic diagram of the logic structure for implementing a gradient operator of an in-memory computing circuit with reconfigurable logic functions according to an embodiment of the present invention;

[0053] Figure 5 It is a schematic diagram of the logic structure for implementing a basic operator of an in-memory computing circuit with reconfigurable logic functions according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0055] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of this application described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0056] In this application, the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe this application and its embodiments, and are not used to limit that the indicated devices, elements, or components must have a specific orientation, or be constructed and operated in a specific orientation.

[0057] Moreover, in addition to being able to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this application can be understood according to specific circumstances.

[0058] In addition, the terms "mounted", "arranged", "provided with", "connected", "coupled", "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there can be internal communication between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0059] The following will describe in detail some embodiments of the present invention with reference to the drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0060] An embodiment of the present invention provides a two-input single-output memory-computation integrated unit, which is implemented based on STT-MTJ (Spin Transfer Torque–Magnetic Tunnel Junction). Figure 1 A schematic structural diagram of the memory-computation integrated unit is shown. As Figure 1 shown, the two-input single-output memory-computation integrated unit includes two input STT-MTJs and one output STT-MTJ. Among them, the free layer sides of the two input STT-MTJs are used as voltage input terminals, connected to the positive terminal Vdd of the operating voltage; the reference layer sides of the two input STT-MTJs are connected to the reference layer side of the output STT-MTJ; the free layer side of the output STT-MTJ is used as a ground terminal, connected to the negative terminal GND of the operating voltage.

[0061] It can be seen that the above two-input single-output memory-computation integrated unit is composed of STT-MTJs through parallel and series combinations, and the resistance states of the STT-MTJs are used as the inputs and outputs of logical operations. Refer to Figure 1, under the condition of a certain operating voltage Vdd, different resistance states of the two MTJs at the input end will affect the combined current flowing through the MTJ at the output end. Therefore, there is a clear relationship between the resistance states of the input MTJ and the output MTJ, and Boolean logic can be implemented. In addition, by initializing the resistance state of the output MTJ and providing an appropriate operating voltage Vdd, different logic functions can be achieved. It can be seen that data storage and logical calculation can be realized under the same circuit architecture, and different logic function reconstructions can be achieved.

[0062] Figure 2 Another structural schematic diagram of the memory-computation integrated unit is shown. As Figure 2 shown, the two-input single-output memory-computation integrated unit includes two input STT-MTJs and one output STT-MTJ. Among them, the reference layer sides of the two input STT-MTJs are used as voltage input ends and are connected to the positive end Vdd of the operating voltage; the free layer sides of the two input STT-MTJs are connected to the free layer side of the output STT-MTJ; the reference layer side of the output STT-MTJ is used as the grounding end and is connected to the negative end GND of the operating voltage. It can be seen that Figure 2 the structure of the memory-computation integrated unit shown Figure 1 compared with the structure of the memory-computation integrated unit shown, there are only slight differences in the connection methods, but the working principles are all based on the current flowing through the STT-MTJ to achieve logical functions.

[0063] Furthermore, through actual tests, it is found that the above two-input single-output memory-computation integrated unit can implement four logics: "NAND", "NOR", "AND", and "OR".

[0064] If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input end and the grounding end is between 0.0731V and 0.0908V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:1, the two-input single-output memory-computation integrated unit implements the "NAND" logic;

[0065] If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input end and the grounding end is between 0.0650V and 0.0730V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:1, the two-input single-output memory-computation integrated unit implements the "NOR" logic;

[0066] If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input end and the grounding end is between -0.202V and 0.195V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:0.5, the two-input single-output memory-computation integrated unit implements the "AND" logic;

[0067] If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.211V and 0.205V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:0.7, and the two-input single-output memory-computation integrated unit realizes the "OR" logic.

[0068] It can be seen that by only adjusting the operating voltage applied between the voltage input terminal and the ground terminal and changing the initial value of the output STT-MTJ, four different logics can be realized on the two-input single-output memory-computation integrated unit.

[0069] On the other hand, based on the two-input single-output memory-computation integrated unit in the above embodiment, an embodiment of the present invention proposes a memory-computation integrated circuit with reconfigurable logic functions. The memory-computation integrated circuit includes:

[0070] An input stage, including 2 N STT-MTJs, and the 2 N STT-MTJs respectively store 1-bit data;

[0071] An N-stage output stage, where the first-stage output stage includes 2 N-1 STT-MTJs, and the subsequent output stages satisfy that the number of STT-MTJs included in each subsequent output stage is half of the number of STT-MTJs included in its previous output stage until the Nth output stage only includes one STT-MTJ;

[0072] A plurality of switches, which are arranged between the input stage and the first-stage output stage and between the output stages, and are used to configure the connection modes between the STT-MTJs in the input stage and the first-stage output stage and the connection modes between the STT-MTJs in the output stages;

[0073] Every two STT-MTJs in the input stage are grouped into a set and correspond one-to-one with one STT-MTJ in the first-stage output stage. By configuring the switches between the input stage and the first-stage output stage, 2 N-1A two-input single-output computing-in-memory unit. In the input stage, two STT-MTJs serve as two input STT-MTJs. In the first-stage output stage, one STT-MTJ serves as the output STT-MTJ. The free layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage. The reference layer sides of the two input STT-MTJs are connected to the reference layer side of the output STT-MTJ. The free layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage. Or, the reference layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage. The free layer sides of the two input STT-MTJs are connected to the free layer side of the output STT-MTJ. The reference layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage.

[0074] In the N-stage output stage, every two STT-MTJs in the previous-stage output stage form a group and correspond one-to-one with one STT-MTJ in the next-stage output stage. By configuring the switches between the previous-stage output stage and the next-stage output stage, computing-in-memory units with two inputs and one output and equal in number to the STT-MTJs in the next-stage output stage are formed. Two STT-MTJs in the previous-stage output stage serve as two input STT-MTJs, and one STT-MTJ in the next-stage output stage serves as the output STT-MTJ. The free layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage. The reference layer sides of the two input STT-MTJs are connected to the reference layer side of the output STT-MTJ. The free layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage. Or, the reference layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage. The free layer sides of the two input STT-MTJs are connected to the free layer side of the output STT-MTJ. The reference layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage.

[0075] Similarly, in the above computing-in-memory circuit with reconfigurable logic functions, any two-input single-output computing-in-memory unit can implement four logics: "NAND", "NOR", "AND", and "OR".

[0076] That is, if the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input terminal and the ground terminal is between 0.0731V and 0.0908V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:1, the two-input single-output computing-in-memory unit implements the "NAND" logic.

[0077] If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input terminal and the ground terminal is between 0.0650V and 0.0730V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:1, the two-input single-output memory-computation integrated unit implements the "NOR" logic;

[0078] If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.202V and 0.195V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:0.5, the two-input single-output memory-computation integrated unit implements the "AND" logic;

[0079] If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.211V and 0.205V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:0.7, the two-input single-output memory-computation integrated unit implements the "OR" logic.

[0080] Substantially, the memory-computation integrated circuit with reconfigurable logic functions according to the embodiments of the present invention includes several levels of cascaded memory-computation integrated units, and a switch configuration connection method is added between each level. The output of the previous level serves as the input of the next level, and the logical values are all represented by the resistance states of the MTJs. Therefore, there is no need to exchange data with the outside. In addition, since each memory-computation integrated unit can implement the reconstruction of four Boolean logic functions through different configuration conditions, the complete circuit has 4 to the power of n reconstruction possibilities, where n represents the number of two-input single-output memory-computation integrated units.

[0081] Further, when constructing the memory-computation integrated circuit, the switch forms between the memory-computation integrated units at each level can be flexible and diverse. For example, the switch can be two single-pole single-throw electronic switches or a single-pole double-throw electronic switch.

[0082] To facilitate the understanding of the above-mentioned memory-computation integrated circuit with reconfigurable logic functions, a specific embodiment of the memory-computation integrated circuit with reconfigurable logic functions of the present invention is given below for illustration.

[0083] Figure 3 Shows an implementation form of the memory-computation integrated circuit with reconfigurable logic functions according to the embodiments of the present invention. As Figure 3 shown, the memory-computation integrated circuit includes:

[0084] The input stage further includes eight STT-MTJs, denoted as the first STT-MTJ, the second STT-MTJ, the third STT-MTJ, the fourth STT-MTJ, the fifth STT-MTJ, the sixth STT-MTJ, the seventh STT-MTJ, and the eighth STT-MTJ, which are sequentially represented by the symbols MTJ1 to MTJ8. Each STT-MTJ stores 1 bit of data;

[0085] The first-stage output stage includes the ninth STT-MTJ, the tenth STT-MTJ, the eleventh STT-MTJ, and the twelfth STT-MTJ, a total of four STT-MTJs, which are respectively represented by the symbols MTJ9 to MTJ12;

[0086] The second-stage output stage includes the thirteenth STT-MTJ and the fourteenth STT-MTJ, a total of two STT-MTJs, which are respectively represented by the symbols MTJ13 and MTJ14;

[0087] The third-stage output stage includes the fifteenth STT-MTJ, a total of one STT-MTJ, which is represented by the symbol MTJ15;

[0088] And, the first switch to the sixteenth switch, a total of 16 switches, which are represented by the symbols S1 to S16.

[0089] The specific connection relationship is as follows:

[0090] In the input stage, every two STT-MTJs form a group, which corresponds one-to-one with one STT-MTJ in the first-stage output stage, and a total of four memory-computation integrated units with two inputs and one output are formed. Among them,

[0091] MTJ1, MTJ4 and MTJ9 form the first memory-computation integrated unit. The free layer sides of MTJ1 and MTJ4 are used as voltage input terminals, connected to the first operating voltage Vdd1. The reference layer sides of MTJ1 and MTJ4 are connected to the reference layer side of MTJ9 through the first switch S1, and the free layer side of MTJ9 is grounded through the ninth switch S9;

[0092] MTJ2, MTJ3 and MTJ10 form the second memory-computation integrated unit. The free layer sides of MTJ2 and MTJ3 are used as voltage input terminals, connected to the first operating voltage Vdd1. The reference layer sides of MTJ2 and MTJ3 are connected to the reference layer side of MTJ10 through the fourth switch S4, and the free layer side of MTJ10 is grounded through the twelfth switch S12;

[0093] MTJ5, MTJ8, and MTJ11 form the third memory - computing integrated unit. The free layer sides of MTJ5 and MTJ8 serve as voltage input terminals, connected to the first operating voltage Vdd1. The reference layer sides of MTJ5 and MTJ8 are connected to the reference layer side of MTJ11 through the fifth switch S5, and the free layer side of MTJ11 is grounded through the thirteenth switch S13;

[0094] MTJ6, MTJ7, and MTJ12 form the fourth memory - computing integrated unit. The free layer sides of MTJ6 and MTJ7 serve as voltage input terminals, connected to the first operating voltage Vdd1. The reference layer sides of MTJ6 and MTJ7 are connected to the reference layer side of MTJ12 through the eighth switch S8, and the free layer side of MTJ12 is grounded through the sixteenth switch S16;

[0095] In the first - stage output stage, every two STT - MTJs form a group, corresponding one - to - one with one STT - MTJ in the second - stage output stage, and together they form 2 two - input single - output memory - computing integrated units. Among them,

[0096] MTJ9, MTJ10, and MTJ13 form the fifth memory - computing integrated unit. The reference layer sides of MTJ9 and MTJ10 serve as voltage input terminals. The reference layer side of MTJ9 is connected to the second operating voltage Vdd2 through the second switch S2, the reference layer side of MTJ10 is connected to the second operating voltage Vdd2 through the third switch S3, the free layer side of MTJ9 is connected to the free layer side of MTJ13 through the tenth switch S10, and the free layer side of MTJ10 is connected to the free layer side of MTJ13 through the eleventh switch S11;

[0097] MTJ11, MTJ12, and MTJ14 form the sixth memory - computing integrated unit. The reference layer sides of MTJ11 and MTJ12 serve as voltage input terminals. The reference layer side of MTJ11 is connected to the second operating voltage Vdd2 through the sixth switch S6, the reference layer side of MTJ12 is connected to the second operating voltage Vdd2 through the seventh switch S7, the free layer side of MTJ11 is connected to the free layer side of MTJ14 through the fourteenth switch S14, and the free layer side of MTJ12 is connected to the free layer side of MTJ14 through the fifteenth switch S15;

[0098] In the second - stage output stage, two STT - MTJs and one STT - MTJ in the third - stage output stage form the seventh two - input single - output memory - computing integrated unit. Among them,

[0099] The free layer sides of MTJ13 and MTJ14 serve as voltage input terminals. The reference layer sides of MTJ13 and MTJ14 are connected to the reference layer side of MTJ15, and the free layer side of MTJ15 is grounded.

[0100] Application Figure 3The circuit can be used to implement the first-order Robert operator. As is known, the truth table of the first-order Robert operator is as follows:

[0101] Input 1 Input 2 Input 3 Input 4 Output 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0

[0102] If the first STT-MTJ stores data A, the second STT-MTJ stores the inversion A' of data A, the third STT-MTJ stores data D, the fourth STT-MTJ stores the inversion D' of data D, the fifth STT-MTJ stores data C, the sixth STT-MTJ stores the inversion C' of data C, the seventh STT-MTJ stores data B, the eighth STT-MTJ stores the inversion B' of data B, and the first arithmetic-in-memory unit, the second arithmetic-in-memory unit, the third arithmetic-in-memory unit, and the fourth arithmetic-in-memory unit are configured to implement the "AND" logic, and the fifth arithmetic-in-memory unit, the sixth arithmetic-in-memory unit, and the seventh arithmetic-in-memory unit are configured to implement the "OR" logic, then first, switches S1, S4, S5, S8, S9, S12, S13, and S16 are closed. At this time, A / D', A' / D, B / C', and C' / D simultaneously perform the AND operation, and the corresponding working voltage is Vdd1. Then, switches S2, S3, S6, S7, S10, S11, S14, and S15 are closed. At this time, the output of the upper stage is used as the input of the lower stage to complete the OR operation, and the corresponding working voltage is Vdd2. Finally, the logical operation of y = A'D + AD' + BC' + B'C is completed, that is, the function of image edge extraction based on the Robert operator is realized. Thus, it can be seen that the calculation method proposed by the present invention does not rely on CMOS logic circuits, and in addition, arithmetic-in-memory integration is realized.

[0103] In addition, based on Figure 3 the arithmetic-in-memory circuit with reconfigurable logic functions, since the first arithmetic-in-memory unit to the seventh arithmetic-in-memory unit can all implement four logical calculations under different configuration conditions, other types of operators can also be constructed.

[0104] For example, referring to Figure 4, if the first STT-MTJ stores the inversion ~C of data C, the second STT-MTJ stores data A, the third STT-MTJ stores the inversion ~B of data B, the fourth STT-MTJ stores data A, the fifth STT-MTJ stores data B, the sixth STT-MTJ stores the inversion ~A of data A, the seventh STT-MTJ stores data C, the eighth STT-MTJ stores the inversion ~A of data A, and the first arithmetic-in-memory unit, the second arithmetic-in-memory unit, the third arithmetic-in-memory unit, the fourth arithmetic-in-memory unit, the fifth arithmetic-in-memory unit, and the sixth arithmetic-in-memory unit are configured to implement the "NOR" logic, and the seventh arithmetic-in-memory unit is configured to implement the "NAND" logic, then the arithmetic-in-memory circuit with reconfigurable logic functions is specifically used to implement the gradient operator;

[0105] For another example, referring to Figure 5 , if the first STT-MTJ stores the inversion ~D of data D, the second STT-MTJ stores data C, the third STT-MTJ stores the inversion ~C of data C, the fourth STT-MTJ stores data B, the fifth STT-MTJ stores the inversion ~B of data B, the sixth STT-MTJ stores data A, the seventh STT-MTJ stores data D, the eighth STT-MTJ stores the inversion ~A of data A, and the first arithmetic-in-memory unit, the second arithmetic-in-memory unit, the third arithmetic-in-memory unit, the fourth arithmetic-in-memory unit, the fifth arithmetic-in-memory unit, and the sixth arithmetic-in-memory unit are configured to implement the "NOR" logic, and the seventh arithmetic-in-memory unit is configured to implement the "NAND" logic, then the arithmetic-in-memory circuit with reconfigurable logic functions is specifically used to implement the basic operator.

[0106] The arithmetic-in-memory circuit structure provided by the embodiment of the present invention, each logic operation unit is composed of an arithmetic-in-memory unit with two inputs and one output, and the input data, logic operation, and operation result are all stored in the same circuit architecture, so there is no need to access the memory additionally; in addition, in the same architecture, both the original input data and the operation paradigm for image edge extraction are stored, and the output result data is also stored, realizing the integration of arithmetic and memory.

[0107] At the same time, for the cascading between different logic functions, only multiple switches need to be set, and the switches can be selected through time multiplexing, which improves the drawback that a conventional spin logic cascade requires an operational amplifier and reduces the energy efficiency overhead; in addition, while performing each-level logic operation, the logic function of the previous level can be dynamically reconfigured, enhancing the confidentiality of the circuit.

[0108] In addition, through different configuration conditions, the reconstruction of three operator functions under the same circuit architecture can be achieved. The reconstruction time is the writing time of the tunnel junction at the output end of each arithmetic unit. Therefore, the reconstruction can reach the nanosecond level. In addition, the calculation process can be realized by controlling the switch through an asynchronous clock, without relying on CMOS logic circuits. Also, due to its characteristic of integrating storage and computing, this circuit supports large-scale parallel computing.

[0109] Finally, it should be noted that the memory-computation integrated circuit structure provided by the embodiments of the present invention can be applied to an image edge extraction circuit to flexibly implement various operators for image edge extraction.

[0110] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A memory - in - computing integrated circuit with reconfigurable logic functions, characterized in that, Including: Input stage, including 2 N STT-MTJs, each STT-MTJ storing 1-bit data respectively; N - level output stage, where the first - level output stage includes 2 N-1 STT - MTJs, and the subsequent output stages satisfy that the number of STT - MTJs included in each subsequent output stage is half of the number of STT - MTJs included in its previous output stage until the N - th output stage includes only one STT - MTJ; A plurality of switches, which are arranged between the input stage and the first-stage output stage and between the output stages, and are used to configure the connection mode between the STT-MTJs in the input stage and the first-stage output stage and the connection mode between the STT-MTJs in each output stage; In the input stage, every two STT-MTJs form a group, which corresponds one-to-one with one STT-MTJ in the first-stage output stage. By configuring the switches between the input stage and the first-stage output stage, 2 N-1 memory and computing integrated units with two inputs and one output are formed. Two STT-MTJs in the input stage serve as two input STT-MTJs, and one STT-MTJ in the first-stage output stage serves as the output STT-MTJ. The free layer sides of the two input STT-MTJs are used as voltage input ends and are connected to the positive end of the operating voltage; the reference layer sides of the two input STT-MTJs are connected to the reference layer side of the output STT-MTJ; the free layer side of the output STT-MTJ is used as the ground end and is connected to the negative end of the operating voltage; or, the reference layer sides of the two input STT-MTJs are used as voltage input ends and are connected to the positive end of the operating voltage; the free layer sides of the two input STT-MTJs are connected to the free layer side of the output STT-MTJ; the reference layer side of the output STT-MTJ is used as the ground end and is connected to the negative end of the operating voltage; In the N-stage output stage, every two STT-MTJs in the previous output stage are grouped together and correspond one-to-one to one STT-MTJ in the next output stage. By configuring the switches between the previous output stage and the next output stage, a memory-computation integrated unit with two inputs and one output and the same number of STT-MTJs as in the next output stage is formed. Two STT-MTJs in the previous output stage serve as two input STT-MTJs, and one STT-MTJ in the next output stage serves as the output STT-MTJ. The free layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage; the reference layer sides of the two input STT-MTJs are connected to the reference layer side of the output STT-MTJ; the free layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage; or, the reference layer sides of the two input STT-MTJs are used as voltage input terminals and are connected to the positive end of the operating voltage; the free layer sides of the two input STT-MTJs are connected to the free layer side of the output STT-MTJ; the reference layer side of the output STT-MTJ is used as the ground terminal and is connected to the negative end of the operating voltage.

2. The compute-in-memory circuit with reconfigurable logic functions according to claim 1, wherein Any memory-computation integrated unit with two inputs and one output is used to implement four logics of "NAND", "NOR", "AND" and "OR". If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input terminal and the ground terminal is between 0.0731V and 0.0908V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:1, the memory-computation integrated unit with two inputs and one output implements the "NAND" logic. If the initial value of the output STT-MTJ is 0, the operating voltage applied between the voltage input terminal and the ground terminal is between 0.0650V and 0.0730V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:1, the memory-computation integrated unit with two inputs and one output implements the "NOR" logic. If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.202V and 0.195V, and the critical dimension ratio of the two input STT-MTJs to the output STT-MTJ is 1:1:0.5, the memory-computation integrated unit with two inputs and one output implements the "AND" logic. If the initial value of the output STT-MTJ is 1, the operating voltage applied between the voltage input terminal and the ground terminal is between -0.211V and 0.205V, and the critical dimension ratios of the two input STT-MTJs to the output STT-MTJ are 1:1:0.7, the two-input and single-output memory-computation integrated unit implements the "OR" logic.

3. The logic function reconfigurable memory - in - computing integrated circuit according to claim 2, characterized in that, The memory-computation integrated circuit with reconfigurable logic functions has 4 to the power of n reconfiguration possibilities, where n represents the number of two-input and single-output memory-computation integrated units.

4. The logic function reconfigurable memory-compute integrated circuit according to claim 1, characterized in that The switch is a single-pole single-throw electronic switch or a single-pole double-throw electronic switch.

5. The logic function reconfigurable memory-compute integrated circuit according to claim 1, wherein Including: An input stage, including the first STT-MTJ, the second STT-MTJ, the third STT-MTJ, the fourth STT-MTJ, the fifth STT-MTJ, the sixth STT-MTJ, the seventh STT-MTJ, and the eighth STT-MTJ, a total of 8 STT-MTJs, each STT-MTJ stores 1 bit of data; The first-stage output stage, including the ninth STT-MTJ, the tenth STT-MTJ, the eleventh STT-MTJ, and the twelfth STT-MTJ, a total of 4 STT-MTJs; The second-stage output stage, including the thirteenth STT-MTJ and the fourteenth STT-MTJ, a total of 2 STT-MTJs; The third-stage output stage, including the fifteenth STT-MTJ, a total of 1 STT-MTJ; And the first switch to the sixteenth switch, a total of 16 switches; Every two STT-MTJs in the input stage form a group, corresponding one-to-one with one STT-MTJ in the first-stage output stage, and a total of 4 two-input and single-output memory-computation integrated units are formed. Among them, The first STT-MTJ, the fourth STT-MTJ, and the ninth STT-MTJ form the first memory-computation integrated unit. The free layer sides of the first STT-MTJ and the fourth STT-MTJ are used as the voltage input terminals, connected to the first operating voltage. The reference layer sides of the first STT-MTJ and the fourth STT-MTJ are connected to the reference layer side of the ninth STT-MTJ through the first switch. The free layer side of the ninth STT-MTJ is grounded through the ninth switch; The second STT-MTJ, the third STT-MTJ, and the tenth STT-MTJ form the second memory-computation integrated unit. The free layer sides of the second STT-MTJ and the third STT-MTJ are used as the voltage input terminals, connected to the first operating voltage. The reference layer sides of the second STT-MTJ and the third STT-MTJ are connected to the reference layer side of the tenth STT-MTJ through the fourth switch. The free layer side of the tenth STT-MTJ is grounded through the twelfth switch; The fifth STT-MTJ, the eighth STT-MTJ, and the eleventh STT-MTJ form the third memory-computation integrated unit. The free layer sides of the fifth STT-MTJ and the eighth STT-MTJ are used as the voltage input terminals, connected to the first operating voltage. The reference layer sides of the fifth STT-MTJ and the eighth STT-MTJ are connected to the reference layer side of the eleventh STT-MTJ through the fifth switch. The free layer side of the eleventh STT-MTJ is grounded through the thirteenth switch; The sixth STT-MTJ, the seventh STT-MTJ, and the twelfth STT-MTJ form the fourth memory and computing integrated unit. The free layer sides of the sixth STT-MTJ and the seventh STT-MTJ serve as voltage input terminals and are connected to the first operating voltage. The reference layer sides of the sixth STT-MTJ and the seventh STT-MTJ are connected to the reference layer side of the twelfth STT-MTJ through the eighth switch, and the free layer side of the twelfth STT-MTJ is grounded through the sixteenth switch; In the first-stage output stage, every two STT-MTJs form a group and correspond one-to-one with one STT-MTJ in the second-stage output stage, together constituting 2 two-input single-output memory and computing integrated units. Among them, The ninth STT-MTJ, the tenth STT-MTJ, and the thirteenth STT-MTJ form the fifth memory and computing integrated unit. The reference layer sides of the ninth STT-MTJ and the tenth STT-MTJ serve as voltage input terminals. The reference layer side of the ninth STT-MTJ is connected to the second operating voltage through the second switch, and the reference layer side of the tenth STT-MTJ is connected to the second operating voltage through the third switch. The free layer side of the ninth STT-MTJ is connected to the free layer side of the thirteenth STT-MTJ through the tenth switch, and the free layer side of the tenth STT-MTJ is connected to the free layer side of the thirteenth STT-MTJ through the eleventh switch; The eleventh STT-MTJ, the twelfth STT-MTJ, and the fourteenth STT-MTJ form the sixth memory and computing integrated unit. The reference layer sides of the eleventh STT-MTJ and the twelfth STT-MTJ serve as voltage input terminals. The reference layer side of the eleventh STT-MTJ is connected to the second operating voltage through the sixth switch, and the reference layer side of the twelfth STT-MTJ is connected to the second operating voltage through the seventh switch. The free layer side of the eleventh STT-MTJ is connected to the free layer side of the fourteenth STT-MTJ through the fourteenth switch, and the free layer side of the twelfth STT-MTJ is connected to the free layer side of the fourteenth STT-MTJ through the fifteenth switch; Two STT-MTJs in the second-stage output stage and one STT-MTJ in the third-stage output stage form the seventh two-input single-output memory and computing integrated unit. Among them, The free layer sides of the thirteenth STT-MTJ and the fourteenth STT-MTJ serve as voltage input terminals. The reference layer sides of the thirteenth STT-MTJ and the fourteenth STT-MTJ are connected to the reference layer side of the fifteenth STT-MTJ, and the free layer side of the fifteenth STT-MTJ is grounded.

6. The compute-in-memory integrated circuit with reconfigurable logic functions according to claim 5, wherein If the first STT-MTJ stores data A, the second STT-MTJ stores the inversion of data A, the third STT-MTJ stores data D, the fourth STT-MTJ stores the inversion of data D, the fifth STT-MTJ stores data C, the sixth STT-MTJ stores the inversion of data C, the seventh STT-MTJ stores data B, the eighth STT-MTJ stores the inversion of data B, and the first computing-in-memory unit, the second computing-in-memory unit, the third computing-in-memory unit, and the fourth computing-in-memory unit are configured to implement the "AND" logic, and the fifth computing-in-memory unit, the sixth computing-in-memory unit, and the seventh computing-in-memory unit are configured to implement the "OR" logic, then the computing-in-memory circuit with reconfigurable logic functions is specifically used to implement the first-order Robert operator.

7. The logic function reconfigurable memory-computation integrated circuit according to claim 5, wherein If the first STT-MTJ stores the inversion of data C, the second STT-MTJ stores data A, the third STT-MTJ stores the inversion of data B, the fourth STT-MTJ stores data A, the fifth STT-MTJ stores data B, the sixth STT-MTJ stores the inversion of data A, the seventh STT-MTJ stores data C, the eighth STT-MTJ stores the inversion of data A, and the first computing-in-memory unit, the second computing-in-memory unit, the third computing-in-memory unit, the fourth computing-in-memory unit, the fifth computing-in-memory unit, and the sixth computing-in-memory unit are configured to implement the "NOR" logic, and the seventh computing-in-memory unit is configured to implement the "NAND" logic, then the computing-in-memory circuit with reconfigurable logic functions is specifically used to implement the gradient operator; If the first STT-MTJ stores the inversion of data D, the second STT-MTJ stores data C, the third STT-MTJ stores the inversion of data C, the fourth STT-MTJ stores data B, the fifth STT-MTJ stores the inversion of data B, the sixth STT-MTJ stores data A, the seventh STT-MTJ stores data D, the eighth STT-MTJ stores the inversion of data A, and the first computing-in-memory unit, the second computing-in-memory unit, the third computing-in-memory unit, the fourth computing-in-memory unit, the fifth computing-in-memory unit, and the sixth computing-in-memory unit are configured to implement the "NOR" logic, and the seventh computing-in-memory unit is configured to implement the "NAND" logic, then the computing-in-memory circuit with reconfigurable logic functions is specifically used to implement the basic operator.

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