Method for providing a mixed channel storage device

Abstract

Disclosed are methods for providing hybrid channel storage devices. The hybrid channel storage device is provided by processing a media interface command, and the provided media interface command processing method is characterized by comprising: acquiring a media interface command, identifying the type of an NVM chip to be accessed by the media interface; acquiring the characteristics of the NVM chip to be accessed according to the identified type; and generating a storage media access command for accessing the NVM chip according to the acquired characteristics.

Description

Technical Field

[0001] The present application relates to storage device technology, and more particularly to a method for providing a hybrid channel storage device. Background Art

[0002] Figure 1 A block diagram of a storage device is shown. Storage device 102 is coupled to a host to provide storage capabilities for the host. The host and storage device 102 can be coupled in various ways, including but not limited to connecting the host and solid-state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication networks, etc. The host can be an information processing device capable of communicating with the storage device in the above manner, such as a personal computer, tablet computer, server, portable computer, network switch, router, cellular phone, personal digital assistant, etc. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, or the like.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data in the DRAM 110. The FTL table and / or cached IO command data can be stored in the DRAM.

[0006] Control component 104 includes a flash memory interface controller (also known as a media interface controller or flash memory channel controller). The flash memory interface controller is coupled to NVM chip 105 and issues commands to NVM chip 105 in accordance with the interface protocol of NVM chip 105 to operate NVM chip 105, and receives command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle" and "ONFI." Chinese patent application number 201510253428.1, entitled "Microinstruction Sequence Execution Method and Apparatus Therefor," provides an example of a media interface controller that applies storage media access commands to the NVM chip by executing microinstructions. Examples of media interface controllers are provided in Chinese patent applications with application number 2020106080147 and patent name “Adaptive NVM reading method and device thereof”, Chinese patent application number 202010615178.2 and patent name “Intelligent read-redo method and media interface controller thereof”, Chinese patent application number 202010207004.2 and patent name “Media interface controller and storage controller for read command fusion”, Chinese patent application number 201810380329.3 and patent name “Method and device for out-of-order execution of NVM commands”, and Chinese patent application number 201610836531.3 and patent name “Method and device for generating NVM chip interface commands”.

[0007] The NVM chip includes one or more logic units (LUNs). The NVM chip package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within an NVM chip can execute commands and report status independently of each other.

[0008] The "Open NAND Flash Interface Specification (Revision 3.0)" available at http: / / www.micron.com / ~ / media / Documents / Products / Other%20Documents / ONFI3_0Gold.aspx provides information on the meanings of target, logical unit, and plane, which is part of the prior art. In this application, unless otherwise noted, the terms target and logical unit (LUN) are used interchangeably.

[0009] NVM chips typically store and read data in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages (also called physical pages). A physical page has a fixed size, such as 17,664 bytes. Physical pages can also have other sizes.

[0010] In storage devices, the Flash Translation Layer (FTL) maintains mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of the storage device as perceived by upper-layer software such as the operating system. Physical addresses are used to access the physical storage units of the storage device. Related technologies also utilize intermediate address formats for address mapping. For example, logical addresses are mapped to intermediate addresses, which are then further mapped to physical addresses.

[0011] The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is important metadata in storage devices. Typically, the data items in the FTL table record the address mapping relationship in units of data pages in the storage device.

[0012] Some storage devices' FTLs are provided by the host to which the storage device is coupled, with the host's memory storing the FTL table and the host's processor executing software to provide the FTL. Others are provided by a storage management device located between the host and the storage device.

[0013] Figure 2 A detailed block diagram showing the control components of a storage device.

[0014] The host accesses the storage device using I / O commands that comply with the storage protocol. Based on the I / O commands from the host, the control unit generates one or more storage commands and provides them to the media interface controller. Based on the storage commands, the media interface controller generates storage media access commands (e.g., program commands, read commands, erase commands) that comply with the NVM chip's interface protocol. The control unit also tracks the completion of all storage commands generated from an I / O command and indicates the results of the I / O command processing to the host.

[0015] See Figure 2 The control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage medium management unit. The host interface receives IO commands provided by the host and generates storage commands to provide to the storage command processing unit. Storage commands, for example, access storage space of the same size, such as 4KB. The data unit corresponding to the data accessed by a storage command recorded in the NVM chip is called a data frame. A physical page records one or more data frames. For example, if the physical page size is 17664 bytes and the data frame size is 4KB, then one physical page can store four data frames.

[0016] The storage media management unit maintains the translation of logical addresses to physical addresses for each storage command. For example, the storage media management unit includes an FTL table. For read commands, the storage media management unit outputs the physical address corresponding to the logical address accessed by the storage command. For write commands, the storage media management unit allocates an available physical address and records the mapping between the logical address accessed and the allocated physical address. The storage media management unit also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0017] The storage command processing unit operates the media interface controller to issue storage media access commands to the NVM chip based on the physical address provided by the storage media management unit. For clarity, commands sent by the storage command processing unit to the media interface controller are referred to as media interface commands, while commands sent by the media interface controller to the NVM chip are referred to as storage media access commands. Storage media access commands comply with the NVM chip's interface protocol.

[0018] Figure 3 Shows the media interface controller.

[0019] The media interface controller includes a microinstruction memory, a microinstruction execution unit, and a signal driver. The media interface controller is also coupled to the NVM chip. The media interface controller provides storage media access commands to the NVM chip and retrieves the results of processing the storage media access commands. The microinstruction memory stores microinstruction sequences.

[0020] The media interface controller receives the media interface command provided by the storage command processing ( Figure 3 (shown as CMD in the figure). The microinstruction sequence corresponds to a media interface command. The media interface controller obtains the corresponding microinstruction sequence based on the received media interface command and provides it to the microinstruction execution unit. The microinstruction execution unit executes the microinstruction sequence and drives the signal driver according to the signal indicated by the microinstruction sequence, generating a specified signal on the pins coupling the media interface to the NVM chip. By executing the microinstruction sequence, a signal sequence that complies with the NVM chip interface protocol is generated. The signal driver also collects signals from the pins, such as the DQ pins, to collect data read from the NVM chip.

[0021] There are many types of NVM chips. These chips come from different vendors, adhere to different NVM chip interface protocols (e.g., "Toggle," "ONFI," etc.), and offer different features (e.g., low latency, large capacity, high endurance, etc.) for different application scenarios.

[0022] The media interface controller couples the NVM chip via channels. To increase storage density and balance the controller chip's pin count, two or more NVM chips are typically coupled to a single channel (or coupled to a channel per LUN or Target). Multiple targets coupled to the same channel share a bus (including a control bus and a data bus) to reduce the number of pins required to couple the NVM chip to the media interface controller. A channel provides a dedicated chip enable (CE) signal to each target coupled to the channel, preventing signals from being transmitted to more than one target at any given time.

[0023] Each NVM chip coupled to the same channel is typically of the same type so that the media interface controller operates all NVM chips in the same manner. Summary of the Invention

[0024] Some application systems require different types of NVM chips to meet diverse performance requirements. For example, CDNs (Content Delivery Networks) require improved read performance, while enterprise applications demand higher data reliability. Within storage devices, there is also a growing demand for diverse NVM chip types. For example, critical metadata in a storage device requires low-latency access (read and / or write). Storage devices capable of distinguishing between hot and cold data require better retention for cold data and improved endurance and / or access latency for hot data. Consequently, there is a need to couple different types of NVM chips to the same control component within the storage device. Furthermore, it is desirable to couple different types of NVM chips to the same channel. However, NVM chips on the same channel share a bus. When these NVM chips are of different types, the method used to drive one NVM chip may not be effective for driving another, posing a challenge for the media interface controller.

[0025] Coupling different types of NVM chips on the same control unit also poses challenges for storage media management. It's necessary to distinguish the storage space provided by different NVM chips, while also keeping technical complexity low for the introduction of new features.

[0026] According to a first aspect of the present application, a first control component according to the first aspect of the present application is provided, including a media interface controller for coupling multiple NVM chips; the media interface controller couples the multiple NVM chips through multiple channels; a first channel among the multiple channels couples the multiple NVM chips; a first NVM chip of the multiple NVM chips has a first type, and a second NVM chip of the multiple NVM chips has a second type; wherein the first type is different from the second type.

[0027] According to the first control component of the first aspect of the present application, there is provided a second control component according to the first aspect of the present application, wherein the first type is an SLC type and the second type is a TLC type.

[0028] According to the first or second control component of the first aspect of the present application, a third control component according to the first aspect of the present application is provided, wherein a second channel among the multiple channels is coupled to a second plurality of NVM chips; a third NVM chip of the second plurality of NVM chips has a third type, and a fourth NVM chip of the second plurality of NVM chips has a fourth type; wherein the third type is different from the fourth type.

[0029] According to the first control component of the first aspect of the present application, there is provided a fourth control component according to the first aspect of the present application, wherein the media interface controller includes a signal driver, and signals are provided to the plurality of channels through the signal driver.

[0030] According to one of the first to fourth control components of the first aspect of the present application, a fifth control component according to the first aspect of the present application is provided, wherein the media interface controller also includes multiple NVM configuration register groups, each NVM configuration register group includes multiple registers storing characteristics of the NVM chip.

[0031] According to the fifth control component of the first aspect of the present application, a sixth control component according to the first aspect of the present application is provided, wherein the NVM configuration register group includes a time constraint configuration register, an address format configuration register, a data length configuration register and / or a command format configuration register.

[0032] According to the fifth or sixth control component of the first aspect of the present application, a seventh control component according to the first aspect of the present application is provided, wherein, according to the type of the NVM chip to be accessed, the characteristics of the type of the NVM chip to be accessed are obtained from the corresponding NVM configuration register group; and the signal driver provides a signal to the NVM chip to be accessed through a channel according to the obtained characteristics.

[0033] According to the seventh control component of the first aspect of the present application, an eighth control component according to the first aspect of the present application is provided, wherein the media interface controller also includes multiple cache units; the data read from the first NVM chip is stored in the first cache unit among the multiple cache units; and the data to be written to the second NVM chip is also stored in the first cache unit.

[0034] According to the eighth control component of the first aspect of the present application, there is provided a ninth control component according to the first aspect of the present application, wherein the first NVM chip serves as a cache for the second NVM chip.

[0035] According to one of the first to ninth control components of the first aspect of the present application, a tenth control component according to the first aspect of the present application is provided, wherein the medium interface controller includes a microinstruction storage unit, a microinstruction execution unit and a signal driver; the microinstruction execution unit executes a microinstruction sequence to operate the signal driver to provide signals to the multiple channels.

[0036] According to the tenth control component of the first aspect of the present application, an eleventh control component according to the first aspect of the present application is provided, wherein the microinstruction memory stores multiple microinstruction sequences; the multiple microinstruction sequences include a microinstruction sequence for processing medium interface commands and multiple microinstruction sequences for providing storage medium access commands to the NVM chip; the microinstruction sequence for processing the medium interface command is executed, and the microinstruction sequence for providing storage medium access commands to the NVM chip corresponding to the medium interface command is called.

[0037] According to the eleventh control component of the first aspect of the present application, a twelfth control component according to the first aspect of the present application is provided, wherein the multiple microinstruction sequences for providing storage medium access commands to the NVM chip include a microinstruction sequence for providing programming commands to the first type of NVM chip and a microinstruction sequence for providing programming commands to the second type of NVM chip.

[0038] According to the eleventh or twelfth control component of the first aspect of the present application, a thirteenth control component according to the first aspect of the present application is provided, wherein the microinstruction execution unit also includes multiple NVM configuration register groups, each NVM configuration register group includes multiple registers storing characteristics of the NVM chip; executing the microinstruction sequence for processing the medium interface command also sets a type tag; the microinstruction execution unit accesses one of the multiple NVM configuration register groups according to the type tag, and uses the characteristics of the NVM chip obtained by accessing one of the multiple NVM configuration register groups to operate the signal driver to provide signals to the multiple channels.

[0039] According to the thirteenth control component of the first aspect of the present application, a fourteenth control component according to the first aspect of the present application is provided, wherein the microinstruction execution unit also includes a microinstruction decoder and multiple signal generation units; the microinstruction decoder provides the microinstruction to one of the multiple signal generation units according to the meaning of the microinstruction; the microinstruction decoder also selects multiple registers of one of the multiple NVM configuration register groups according to the type tag and provides them to one or more of the multiple signal generation units; the signal generation unit operates the signal driver to provide a signal to one of the multiple channels according to the microinstruction provided by the microinstruction decoder and the characteristics obtained from one of the multiple NVM configuration register groups.

[0040] According to the fourteenth control component of the first aspect of the present application, a fifteenth control component according to the first aspect of the present application is provided, wherein the multiple signal generating units include a command signal generating unit, an address signal generating unit and / or a data transmission signal generating unit; the command signal generating unit generates a command header of a storage medium access command according to a microinstruction, and also obtains time constraint information from the time constraint configuration register of the NVM configuration register group to generate an ALE signal and / or a CLE signal on the channel.

[0041] According to the fourteenth or fifteenth control component of the first aspect of the present application, a sixteenth control component according to the first aspect of the present application is provided, wherein the address signal generation unit generates the address part of the storage medium access command according to the microinstruction, and also obtains the address format from the address format configuration register of the NVM configuration register group to generate a plurality of cycles of DQ signals on the channel.

[0042] According to one of the fourteenth to sixteenth control components of the first aspect of the present application, a seventeenth control component according to the first aspect of the present application is provided, wherein the data transmission signal generation unit generates the data part of the storage medium access command according to the microinstruction, and also obtains the data length from the data length configuration register of the NVM configuration register group to generate a DQ signal of a specified number of cycles on the channel.

[0043] According to one of the tenth to seventeenth control components of the first aspect of the present application, an eighteenth control component according to the first aspect of the present application is provided, wherein the media interface controller includes one or more cache units, the cache unit being used to cache data read from one of the multiple NVM chips or data to be written to one of the multiple NVM chips; the microinstruction execution unit executes a microinstruction sequence for a copy operation to provide a read command to the first NVM chip, records the read data in the first cache unit, and provides a programming command to the second NVM chip to write the data of the first cache unit into the second NVM chip.

[0044] According to the eighteenth control component of the first aspect of the present application, there is provided a nineteenth control component according to the first aspect of the present application, wherein the media interface controller calls a microinstruction sequence for a copy operation in response to recognizing a media interface command indicating a move operation.

[0045] According to the eighteenth or nineteenth control component of the first aspect of the present application, a twentieth control component according to the first aspect of the present application is provided, wherein the first NVM chip serves as a cache for the second NVM chip; the media interface controller also includes a block mapping table, the entries of the block mapping table associatively recording the blocks of the second NVM chip and one or more blocks of the first NVM chip.

[0046] According to the twentieth control component of the first aspect of the present application, a twenty-first control component according to the first aspect of the present application is provided, wherein in response to receiving a first media interface command instructing to write data to the first block of the second NVM chip, the block mapping table is accessed to obtain the second block of the first NVM chip associated with the first block; and the write data indicated by the first media interface command is written to the second block through a microinstruction sequence for providing a programming command to the first type of NVM chip.

[0047] According to the twenty-first control component of the first aspect of the present application, a twenty-second control component according to the first aspect of the present application is provided, wherein in response to receiving a first media interface command instructing to write data to the first block of the second NVM chip, the association between the first block and the second block of the first NVM chip is recorded in the block mapping table.

[0048] According to the twenty-first or twenty-second control component of the first aspect of the present application, a twenty-third control component according to the first aspect of the present application is provided, wherein the write data size indicated by the first medium interface command is the physical page size of the first block; when executing a microinstruction sequence for providing a programming command to the first type of NVM chip, the conversion method of the physical page address of the second NVM chip and the physical page address of the first NVM chip is obtained through the address format configuration register of the NVM configuration register group corresponding to the same type tag, and the physical page address of the second block is generated.

[0049] According to one of the twenty-first to twenty-third control components of the first aspect of the present application, a twenty-fourth control component according to the first aspect of the present application is provided, wherein, according to the association relationship between the first block and the second block recorded in the block mapping table, the data of the second block is copied to the first block by executing a microinstruction sequence for the copy operation; and the association relationship between the first block and the second block is cleared in the block mapping table.

[0050] According to one of the twenty-first to twenty-fourth control components of the first aspect of the present application, a twenty-fifth control component according to the first aspect of the present application is provided, wherein in response to receiving a second media interface command instructing to write data to the third block of the second NVM chip, the block mapping table is accessed to obtain that the third block has no record in the block mapping table; and the write data indicated by the second media interface command is written to the third block through a microinstruction sequence for providing a programming command to the second type of NVM chip.

[0051] According to one of the tenth to twenty-fifth control components of the first aspect of the present application, a twenty-sixth control component according to the first aspect of the present application is provided, wherein the medium interface controller includes a scheduler for scheduling multiple threads to be executed by the microinstruction execution unit, wherein the executed microinstruction sequence together with its status is called a thread; a first plurality of threads among the multiple threads correspond one-to-one to the LUNs of the multiple NVM chips, and each of the first plurality of threads corresponds to a microinstruction sequence for providing storage medium access commands to the NVM chip.

[0052] According to the twenty-sixth control component of the first aspect of the present application, a twenty-seventh control component according to the first aspect of the present application is provided, wherein the second thread of the multiple threads corresponds to the LUN of the first NVM chip to copy data and the LUN of the second NVM chip, and the second thread corresponds to the microinstruction sequence for the copy operation.

[0053] According to the twenty-sixth control component of the first aspect of the present application, a twenty-eighth control component according to the first aspect of the present application is provided, wherein the media interface controller schedules a first thread and a second thread in response to recognizing a media interface command indicating a move operation, and both the first thread and the second thread are assigned a first cache unit; the first thread reads data from the first NVM chip and records it in the first cache unit according to a microinstruction sequence for providing a read command to the NVM chip; and the second thread writes the data in the first cache unit to the second NVM chip according to a microinstruction sequence for providing a programming command to the NVM chip.

[0054] According to the twenty-eighth control component of the first aspect of the present application, a twenty-ninth control component according to the first aspect of the present application is provided, wherein in response to the data to be written to the second NVM chip not yet being recorded in the first cache unit, the second thread gives in; and / or in response to the data to be written to the second NVM chip being recorded in the first cache unit, the second thread is scheduled.

[0055] According to the second aspect of the present application, a storage device according to the second aspect of the present application is provided, comprising a control component and multiple NVM chips; wherein the control component is one of the first to twenty-ninth control components according to the first aspect of the present application.

[0056] According to a third aspect of the present application, a first media interface command processing method according to the third aspect of the present application is provided, including: obtaining a media interface command, identifying the type of NVM chip to be accessed by the media interface; obtaining characteristics of the NVM chip to be accessed based on the identified type; and generating a storage medium access command for accessing the NVM chip based on the obtained characteristics.

[0057] According to the first medium interface command processing method of the third aspect of the present application, a second medium interface command processing method according to the third aspect of the present application is provided, wherein in response to the type being the first type, a first microinstruction sequence corresponding to the first type is executed; the first microinstruction sequence obtains the characteristics during execution, and generates a storage medium access command for accessing the NVM chip based on the obtained characteristics.

[0058] According to the first medium interface command processing method of the third aspect of the present application, a third medium interface command processing method according to the third aspect of the present application is provided, wherein in response to the medium interface command indicating a first operation, a first microinstruction sequence corresponding to the first operation is executed; the first microinstruction sequence obtains the characteristics during execution, and generates a storage medium access command for accessing the NVM chip based on the obtained characteristics.

[0059] According to the second or third media interface command processing method of the third aspect of the present application, a fourth media interface command processing method according to the third aspect of the present application is provided, wherein, based on the identified type, the characteristics of the type of the NVM chip to be accessed are obtained from the NVM configuration register group corresponding to the type; wherein the NVM configuration register group includes a time constraint configuration register, an address format configuration register, a data length configuration register and / or a command format configuration register that store the characteristics of the NVM chip.

[0060] According to one of the second to fourth media interface command processing methods of the third aspect of the present application, a fifth media interface command processing method according to the third aspect of the present application is provided, wherein a microinstruction sequence for processing a media interface command is executed to analyze the media interface command and call the first microinstruction sequence; wherein the microinstruction sequence for processing a media interface command is also executed to identify the type of NVM chip to be accessed by the media interface; and the first microinstruction sequence is executed to obtain the characteristics of the type of NVM chip to be accessed from the NVM configuration register group corresponding to the type.

[0061] According to one of the second to fifth media interface command processing methods of the third aspect of the present application, a sixth media interface command processing method according to the third aspect of the present application is provided, wherein the first microinstruction sequence includes microinstructions for generating a command header of a storage medium access command, microinstructions for generating an address of a storage medium access command and / or microinstructions for generating data of a storage medium access command.

[0062] According to the sixth media interface command processing method of the third aspect of the present application, a seventh media interface command processing method according to the third aspect of the present application is provided, wherein the microinstructions for generating the command header of the storage medium access command are executed to generate the command header of the storage medium access command, and time constraint information is obtained from the time constraint configuration register of the NVM configuration register group to generate the command header ALE signal and / or CLE signal for the storage medium access command on the channel.

[0063] According to the sixth or seventh media interface command processing method of the third aspect of the present application, an eighth media interface command processing method according to the third aspect of the present application is provided, wherein the microinstruction for generating the address of the storage medium access command is executed, and the address format is obtained from the address format configuration register of the NVM configuration register group to generate a plurality of cycles of DQ signals for the address of the storage medium access command on the channel.

[0064] According to one of the sixth to eighth media interface command processing methods of the third aspect of the present application, a ninth media interface command processing method according to the third aspect of the present application is provided, wherein the microinstruction for generating data for a storage medium access command is executed, and the data length is obtained from the data length configuration register of the NVM configuration register group to generate a DQ signal of a specified number of cycles on the channel.

[0065] According to one of the first to ninth media interface command processing methods of the third aspect of the present application, a tenth media interface command processing method according to the third aspect of the present application is provided, wherein in response to obtaining a media interface command instructing to move data from a first type of NVM chip to a second type of NVM chip, a microinstruction sequence for a copy operation is executed to provide a read command to the first NVM chip, record the read data in a first cache unit, and provide a programming command to the second NVM chip to write the data in the first cache unit to the second NVM chip.

[0066] According to the tenth media interface command processing method of the third aspect of the present application, an eleventh media interface command processing method according to the third aspect of the present application is provided, wherein the first NVM chip serves as a cache for the second NVM chip; and the blocks of the second NVM chip and one or more blocks of the first NVM chip are recorded in association in the entries of the block mapping table.

[0067] According to the eleventh media interface command processing method of the third aspect of the present application, a twelfth media interface command processing method according to the third aspect of the present application is provided, wherein in response to receiving a first media interface command instructing to write data to the first block of the second NVM chip, the block mapping table is accessed to obtain the second block of the first NVM chip associated with the first block; and the write data indicated by the first media interface command is written to the second block through a microinstruction sequence for providing a programming command to the first type of NVM chip.

[0068] According to the twelfth media interface command processing method of the third aspect of the present application, a thirteenth media interface command processing method according to the third aspect of the present application is provided, wherein in response to receiving a first media interface command instructing to write data to the first block of the second NVM chip, the association of the first block with the second block of the first NVM chip is recorded in the block mapping table.

[0069] According to the twelfth or thirteenth media interface command processing method of the third aspect of the present application, a fourteenth media interface command processing method according to the third aspect of the present application is provided, wherein the write data size indicated by the first media interface command is the physical page size of the first block; when executing a microinstruction sequence for providing a programming command to the first type of NVM chip, the conversion method of the physical page address of the second NVM chip and the physical page address of the first NVM chip is obtained through the address format configuration register of the NVM configuration register group corresponding to the same type tag, and the physical page address of the second block is generated.

[0070] According to one of the twelfth to fourteenth media interface command processing methods of the third aspect of the present application, a fifteenth media interface command processing method according to the third aspect of the present application is provided, wherein, according to the association relationship between the first block and the second block recorded in the block mapping table, the data of the second block is copied to the first block by executing a microinstruction sequence for the copy operation; and the association relationship between the first block and the second block is cleared in the block mapping table.

[0071] According to one of the twelfth to fifteenth media interface command processing methods of the third aspect of the present application, a sixteenth media interface command processing method according to the third aspect of the present application is provided, wherein in response to receiving a second media interface command instructing to write data to the third block of the second NVM chip, the block mapping table is accessed to obtain that the third block has no record in the block mapping table; and the write data indicated by the second media interface command is written to the third block through a microinstruction sequence for providing a programming command to the second type of NVM chip.

[0072] According to one of the first to sixteenth media interface command processing methods of the third aspect of the present application, a seventeenth media interface command processing method according to the third aspect of the present application is provided, further comprising: scheduling multiple threads, wherein an executed microinstruction sequence together with its state is called a thread; a first plurality of threads among the multiple threads correspond one-to-one to a LUN of an NVM chip, and each of the first plurality of threads corresponds to a microinstruction sequence for providing a storage medium access command to the NVM chip.

[0073] According to one of the seventeenth media interface command processing methods of the third aspect of the present application, an eighteenth media interface command processing method according to the third aspect of the present application is provided, wherein the second thread of the multiple threads corresponds to the LUN of the first NVM chip to copy data and the LUN of the second NVM chip, and the second thread corresponds to the microinstruction sequence for the copy operation.

[0074] According to one of the seventeenth media interface command processing methods of the third aspect of the present application, a nineteenth media interface command processing method according to the third aspect of the present application is provided, wherein in response to identifying a media interface command indicating a move operation, a first thread and a second thread are scheduled, and both the first thread and the second thread are assigned a first cache unit; the first thread reads data from the first NVM chip and records it in the first cache unit according to a microinstruction sequence for providing a read command to the NVM chip; and the second thread writes the data in the first cache unit to the second NVM chip according to a microinstruction sequence for providing a programming command to the NVM chip.

[0075] According to one of the nineteenth media interface command processing methods of the third aspect of the present application, a twentieth media interface command processing method according to the third aspect of the present application is provided, wherein in response to the data to be written to the second NVM chip not yet being recorded in the first cache unit, the second thread gives way; and / or in response to the data to be written to the second NVM chip being recorded in the first cache unit, the second thread is scheduled.

[0076] According to the fourth aspect of the present application, an information processing device according to the fourth aspect of the present application is provided, wherein the information processing device includes a processor and a memory, wherein the processor stores a program, and when the program is executed by the processor, it implements one of the first to twentieth media interface command processing methods according to the third aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0078] Figure 1 A block diagram of a storage device of the prior art is shown;

[0079] Figure 2 A detailed block diagram showing the control components of a storage device;

[0080] Figure 3 The media interface controller is shown;

[0081] Figure 4A A mixed channel media interface controller according to the present application is presented;

[0082] Figure 4B Another mixed channel media interface controller according to the present application is shown;

[0083] Figure 5 A schematic diagram showing a programming operation implemented by a mixed channel media interface controller according to the present application is shown;

[0084] Figure 6A A schematic diagram of a microinstruction according to another embodiment of the present application is shown;

[0085] Figure 6B The present invention shows an NVM configuration register group according to another embodiment of the present application;

[0086] Figure 7 shows a block diagram of a microinstruction execution unit according to another embodiment of the present application;

[0087] Figure 8 A block diagram of a media interface controller according to another embodiment of the present application is shown;

[0088] Figure 9A A block diagram of a media interface controller according to yet another embodiment of the present application is shown;

[0089] Figure 9B A block diagram showing a media interface controller according to yet another embodiment of the present application; and

[0090] Figure 10 A block diagram of a media interface controller according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0091] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0092] Figure 4A A mixed channel media interface controller according to the present application is presented.

[0093] The signal driver of the media interface controller couples one or more channels ( Figure 4A 420 and 425). Each channel is coupled to one or more NVM chips. These NVM chips can be of the same or different types. For example, Figure 4A In the embodiment, the two NVM chips coupled to channel 420 are of type 1 and type 2, respectively, while the two NVM chips coupled to channel 425 are of type 3 and type 4, respectively. Still for example, type 1 is a low-latency NVM operating according to the Toggle standard, type 2 is a TLCNVM operating according to the Toggle standard, type 3 is a TLCNVM operating according to the ONFI standard, and type 4 is a TLCNVM operating according to the ONFI standard but working in SLC mode.

[0094] Figure 4B Yet another mixed-channel media interface controller according to the present application is presented.

[0095] same Figure 4A Compared with the mixed channel media interface controller, Figure 4B The microinstruction memory of the hybrid channel media interface controller stores multiple microinstruction sequences, including, for example, a microinstruction sequence for media interface command processing, a microinstruction sequence 410 for issuing a program command to a type 1 NVM chip, a microinstruction sequence 412 for issuing a program command to a type 2 NVM chip, a microinstruction sequence 414 for issuing a read command to a type 3 NVM chip, and a microinstruction sequence 416 for issuing an erase command to a type 4 NVM chip. The microinstructions in the microinstruction sequences (410, 412, 414, and 416) each indicate the required parameters to satisfy the type of NVM chip to be operated. It is understood that the microinstruction memory also stores microinstruction sequences for other operations.

[0096] In response to a storage command processing unit (see also Figure 2 ) provides a media interface command. The microinstruction execution unit executes a microinstruction sequence for media interface command processing to identify the NVM chip type and operation type indicated by the media interface command. It then calls the corresponding microinstruction sequence to drive the signal driver to generate a storage media access command to the target of the specified NVM chip. By providing corresponding microinstruction sequences for different types of NVM chips, when the microinstruction sequence is executed, a storage media access command corresponding to the NVM chip type is generated on the channel.

[0097] For example, the media interface command instructs the NVM chip of type 1 of programming channel 420, and the microinstruction sequence for executing the media interface command processing calls the microinstruction sequence 410 for issuing a program command to the NVM chip of type 1. For another example, the media interface command instructs the NVM chip of type 4 of erasing channel 425, and the microinstruction sequence for executing the media interface command processing calls the microinstruction sequence 416 for issuing an erase command to the NVM chip of type 4.

[0098] As another example, a media interface command indicates a variety of information, including the type of operation (e.g., read, program, erase, etc.), the address to be accessed (e.g., which NVM chip, which LUN, block number, page number, etc.), and an optional type tag. The type tag indicates, for example, a TLC operation, an MLC operation, or an SLC operation. Alternatively or further, the type tag indicates the use of the ONFI protocol or the use of the Toggle protocol. By executing a microinstruction sequence for processing the media interface command, a microinstruction sequence corresponding to processing the media interface command is identified. For example, if the type tag of the media interface command indicates an SLC operation, the microinstruction sequence 410 is called to generate a storage medium access command based on the media interface command; if the type tag of the media interface command indicates a TLC operation, the microinstruction sequence 412 is called to generate a storage medium access command based on the media interface command.

[0099] Figure 5 A schematic diagram showing a programming operation implemented by a mixed channel media interface controller according to the present application is shown.

[0100] As an example, the microinstruction memory stores a microinstruction sequence 510 for media interface command processing, a microinstruction sequence 512 for issuing a program command to an SLC type NVM chip, and a microinstruction sequence 514 for issuing a program command to a TLC type NVM chip.

[0101] In response to the storage command processing unit providing a media interface command to the media interface controller, a microinstruction sequence 510 for media interface command processing is executed. The microinstruction sequence 510 obtains the media interface command (520), identifies the NVM chip type and operation type indicated by the media interface command based on the content of the media interface command, and calls a corresponding microinstruction sequence (512 or 514) to drive the signal driver to generate a storage medium access command to the target of the specified NVM chip.

[0102] Optionally, when executing the microinstruction sequence 510, corresponding parameters are generated and the called microinstruction sequence is configured based on the NVM chip type and operation type indicated by the media interface command. For example, for the programming command of an SLC-type NVM chip, the amount of data to be transmitted is 4KB, while for the programming operation of a TLC-type NVM chip, the amount of data required to be transmitted is 16KB, 32KB, or 48KB. The parameters generated when executing the microinstruction sequence 510 indicate the amount of data to be transmitted. As another example, the programming command for an SLC-type NVM chip and the programming command for a TLC-type NVM chip have different command formats and / or command encodings, and the parameters generated when executing the microinstruction sequence 510 indicate the command format and / or command encoding to be used. As another example, the programming command for an SLC-type NVM chip and the programming command for a TLC-type NVM chip have different timing or constraints, such as having different signal setup times and / or hold times, and the parameters generated when executing the microinstruction sequence 510 indicate the timing or constraints to be used.

[0103] Still optionally, when executing the microinstruction sequence 510, the physical address of the NVM chip indicated by the media interface command for accessing the NVM chip is also checked or adjusted. For example, the programming order of multiple physical pages of a block of an NVM chip is inconsistent with its physical page number (for example, programming cannot be performed in ascending or descending order of physical page numbers, but rather in a specified order, such as programming each physical page in the order of physical page numbers 1-10-11-2-20). Accordingly, when executing the microinstruction sequence 510, the physical page number to be programmed is generated based on the physical address indicated by the media interface command. As another example, different types of NVM chips have different numbers of physical pages in their respective blocks. To facilitate storage medium management, the storage command processing unit manages the storage medium as a virtual NVM. The media interface command indicates the page address of the virtual NVM. The page of the virtual NVM may be composed of two or more real physical pages. Therefore, the microinstruction sequence 510 performs conversion between the page address of the virtual NVM and the real physical page number.

[0104] For example, if, when executing microinstruction sequence 510, the obtained media interface command is recognized as instructing to perform a programming operation on an SLC-type NVM chip, microinstruction sequence 512 is invoked and optionally provided with parameters required for programming the SLC-type NVM chip. In response, the microinstruction execution unit (see also FIG. 4 ) executes microinstruction sequence 512.

[0105] For example, in a programming operation for an SLC-type NVM chip, the amount of data to be written is 4KB. When microinstruction sequence 512 is executed, the 4KB of data to be written is obtained (the storage location of this data is provided by the media interface command) and stored in the programming data cache. Optionally, microinstruction sequence 512 only confirms the availability of the 4KB of data to be written without moving it to the cache, thereby reducing operations.

[0106] Executing the microinstruction sequence 512 also generates a signal indicating an SLC NVM chip program command to provide the program command along with the 4KB data to the SLC NVM chip.

[0107] The signal indicating the SLC NVM chip programming command generated by the execution microinstruction sequence 512 is compatible with the storage protocol supported by the SLC NVM chip and the timing and constraints of the storage protocol.

[0108] Still for example, if microinstruction sequence 510 recognizes that the acquired media interface command indicates to perform a programming operation on a TLC-type NVM chip, it calls microinstruction sequence 512 and optionally provides it with parameters required to perform programming of the TLC-type NVM chip. In response, the microinstruction execution unit (also see FIG. 4 ) executes microinstruction sequence 514.

[0109] For example, in a programming operation for a TLC-type NVM chip, the amount of data written is 48KB. When microinstruction sequence 514 is executed, the 48KB of data to be written is obtained (the storage location of the data is provided by the media interface command) and stored in the programming data cache. Optionally, the unit of data movement of microinstruction sequence 514 (including microinstruction sequence 512) is 4KB at a time. Accordingly, the microinstruction sequence completes the acquisition of the data to be written to the TLC NVM chip through 16 data moves. Optionally, the number of data moves (16 times) is indicated by a parameter of microinstruction sequence 510, or the microinstruction sequence 514 itself records the number of times.

[0110] Optionally, the microinstruction sequence 514 only confirms that the 48KB data to be written is available without moving it to the cache to reduce operations.

[0111] Executing the microinstruction sequence 514 also generates a signal indicating a TLC NVM chip program command to provide the program command along with the 48KB data to the TLC NVM chip.

[0112] Figure 6A A schematic diagram of microinstructions according to another embodiment of the present application is shown.

[0113] See also Figure 3 4 , the microinstruction sequence includes a plurality of microinstructions, and the media interface controller executes the microinstructions in the microinstruction sequence.

[0114] In order to support a mixed arrangement of multiple types of NVM chips in a single channel, a "type tag" is set in one, multiple, or all microinstructions (601). The type tag indicates the type of NVM chip operated by the microinstruction.

[0115] Figure 6A A table showing the meaning of the type tag is also provided. For example, a type tag with a value of "0x01" indicates that the type of NVM chip is a low-latency flash memory that complies with the Toggle protocol. A low-latency flash memory that complies with the Toggle protocol includes multiple features, such as its storage cells are of SLC type, the amount of data required to program it is 4KB, the time it takes to complete programming (in microseconds) after issuing a program command is typically queried, and its signals comply with the timing required by the Toggle protocol. For another example, a type tag with a value of "0x02" indicates that the type of NVM chip is a TLC flash memory that complies with the Toggle protocol. The multiple features of a TLC flash memory that complies with the Toggle protocol include, for example, its storage cells are of TLC type, the amount of data required to program it is 48KB, the time it takes to complete programming (in tens of microseconds) after issuing a program command is typically queried, and its signals comply with the timing required by the Toggle protocol. For another example, a type tag with a value of "0x03" indicates that the type of NVM chip is a TLC flash memory that complies with the ONFI protocol. Various characteristics of ONFI-compliant TLC flash memory include, for example, that its memory cells are TLC-type, the amount of data required for programming is 16KB or 32KB, the typical time it takes to complete programming after issuing a program command (tens of microseconds), and that its signals adhere to the timing requirements of the ONFI protocol. For another example, a type flag with a value of "0x04" indicates that the NVM chip type is ONFI-compliant TLC flash memory, but operates in SLC mode. Various characteristics of ONFI-compliant TLC flash memory operating in SLC mode include, for example, that its memory cells are SLC-type, the amount of data required for programming is 16KB, the typical time it takes to complete programming after issuing a program command (several microseconds), and that its signals adhere to the timing requirements of the ONFI protocol.

[0116] Various microinstructions are provided in Chinese Patent Application No. 201510253428.1, entitled "Microinstruction Sequence Execution Method and Apparatus Thereof," Chinese Patent Application No. 201610009789.6, entitled "Method and Apparatus for Checking Block Page Addresses," and Chinese Patent Application No. 201610836531.3, entitled "Method and Apparatus for Generating NVM Chip Interface Commands," which are incorporated herein by reference in their entirety. One or more existing microinstructions, as well as one or more future microinstructions, may additionally be provided with a "type tag" according to an embodiment of the present application to indicate the type of NVM chip to be operated.

[0117] The "type tag" of the microinstruction indicates the type of the NVM chip. It is also necessary to describe one or more characteristics required by one or more "type tags" for the media interface controller. According to an embodiment of the present application, the media interface controller also includes one or more NVM configuration register groups, each of which includes multiple registers for describing various characteristics of the corresponding NVM chip.

[0118] Figure 6B An NVM configuration register set according to yet another embodiment of the present application is shown.

[0119] Figure 6B For example, the "Type Tag" has four values: "0x00", "0x01", "0x02" and "0x03" (see also Figure 6A Each value of the “type tag” corresponds to one of the NVM configuration register groups (610, 620, 630, and 640). Each register in the NVM configuration register group is used to describe the characteristics of the NVM chip.

[0120] As an example, each NVM configuration register group includes four registers (including a time constraint configuration register, an address format configuration register, a data length configuration register, and a command format configuration register).

[0121] The time constraint configuration register records, for example, the setup time and hold time of one or more signals required by the Toggle or ONFI protocols. The address format configuration register records, for example, the format of the address in a storage medium access command, including the number of bus cycles occupied by address transmission on the DQ signal and the meaning of the address transmitted in each cycle. The data length configuration register records the length of data required to be transmitted for read and programming commands. The command format configuration register records, for example, the command code indicating a storage medium access command (for example, "0x80" represents the start of a programming command for a specific NVM chip type, while "0x10" represents the completion of data transmission for a programming command).

[0122] Thus, a set of NVM configuration registers can be obtained according to the "type tag" field of the microinstruction, and then a variety of configurable parameters to be used when generating storage medium access commands can be obtained, and storage medium access commands can be generated on the channel according to the instructions of the parameters.

[0123] Still optionally, the microinstruction indicates a "type tag" field. For a specific microinstruction, one or more configuration registers of the NVM configuration register group corresponding to the "type tag" field are used (without using all configuration registers). For example, for a microinstruction sequence (including one or more microinstructions) for generating an erase command, it is not necessary to use the data length configuration register in the NVM configuration register group (the erase command does not need to transmit data).

[0124] Figure 7 A block diagram of a microinstruction execution unit according to another embodiment of the present application is shown.

[0125] The microinstructions to be executed are provided to the microinstruction execution unit. The microinstruction execution unit includes a microinstruction decoding unit, a multiplexer, a selector, a plurality of NVM configuration register groups, and a plurality of signal generation units (e.g., a command signal generation unit, an address signal generation unit, a data transfer signal generation unit).

[0126] The microinstruction decoding unit provides the type tag field of the microinstruction to the selector. The selector is coupled to multiple NVM configuration register groups and, based on the value of the type tag field, selects and outputs one of the NVM configuration register groups. The selected NVM configuration register group is coupled to one or more signal generation units based on the characteristics described by each register. For example, time constraint information is used when generating the command code, address, and data of the storage medium access command, so the time constraint configuration register is coupled to the command signal generation unit, the address signal generation unit, and the data transmission signal generation unit; address format information is only used when generating the address of the storage medium access command, so the address format configuration register is only coupled to the address signal generation unit. Similarly, the data length register is only coupled to the data transmission signal generation unit.

[0127] The microinstruction decoding unit also couples the command signal generation unit, the address signal generation unit, and the data transmission signal generation unit through a multiplexer. Microinstructions with different meanings operate the corresponding signal generation units to operate the signal driver on the channel to generate a storage medium access command signal for the NVM chip.

[0128] For example, a microinstruction is used to generate a command header for a storage medium access command (taking a programming command as an example, the part representing "0x80h"). Such a microinstruction describes the values ​​of signals such as ALE, CLE, and DQ (for example, ALE is 0, CLE is 1, and DQ is "0x80h"). The microinstruction decoding unit provides such a microinstruction to the command signal generation unit through a multiplexer. The command signal generation unit also receives time constraint information provided by the time constraint configuration register from the selector. Based on the time constraint information, the command signal generation unit operates the signal driver on the channel to set the ALE, CLE, DQ and other signals to the specified level state at the moment when the time constraint is met.

[0129] For another example, a microinstruction is used to generate the address portion of a storage medium access command (representing the physical address to be accessed, using a programming command as an example). Such a microinstruction describes, for example, a value transmitted over multiple cycles on a DQ signal, or a reference indicating a storage location where a value transmitted over multiple cycles on a DQ signal is stored. The address also requires a format, such as the number of cycles the DQ signal is transmitted over, and which portion of the address the value to be transmitted in each cycle corresponds to. The microinstruction decoding unit provides such a microinstruction to the address signal generation unit via a multiplexer. The address signal generation unit also receives an address format from a selector, provided by an address format configuration register. Based on the address format, the address signal generation unit operates a signal driver to set signals such as DQ on the channel to specified values. The address signal generation unit also receives timing constraint information from a timing constraint configuration register and sets signals such as DQ to specified levels when the timing constraints are met. Optionally, the address indicated by the microinstruction is transformed based on the address format provided by the address format configuration register. For example, the programming sequence number indicated by the media interface command is transformed into a physical page number.

[0130] For another example, a microinstruction is used to generate the data portion of a storage medium access command (using a programming command as an example, representing data to be written to an NVM chip). Such a microinstruction describes, for example, a value transmitted over multiple cycles on a DQ signal, or a reference to a cache location storing the value transmitted over multiple cycles on a DQ signal. The transmitted data also requires a data length. For example, an SLC-type NVM chip corresponds to a programming data length of 4KB, while a TLC-type NVM chip corresponds to a programming data length of 48KB. The microinstruction decoding unit provides such a microinstruction to the data signal generation unit via a multiplexer. The data signal generation unit also receives the data length from a data length configuration register from a selector. Based on the data length and the data to be transmitted, the data transmission signal generation unit operates the signal driver to set the DQ and other signals on the channel to a specified value and generate a specified number of DQ signals (for example, to transmit 4096 bytes of data, 2048 or 4096 DQ signal transmission cycles are required). The address signal generation unit also receives timing constraint information from a timing constraint configuration register and sets the DQ and other signals to a specified level state when the timing constraint is met.

[0131] Optionally, the microinstruction execution unit also executes other microinstructions. Some microinstructions are used to determine the location of subsequent microinstructions (referred to as control microinstructions), while others are used to move data between memory and cache. These microinstructions do not operate signal drivers. Optionally, the control microinstruction determines the number of DQ signal transmission cycles required to transmit data to the NVM chip and obtains the required number of DQ signal transmission cycles from the data length configuration register based on the type flag field of the control microinstruction.

[0132] In an optional embodiment, a microinstruction for setting a type tag is provided instead of providing a type tag field in each microinstruction. Execution of the microinstruction for setting the type tag sets the microinstruction execution unit to use a specified NVM configuration register set, and the setting remains valid until the next change. Thus, the same microinstruction sequence is used to process, for example, storage medium access commands for different types of NVM chips, thereby reducing the number of microinstruction sequences that need to be stored. For example, a TLC-type NVM chip and an SLC-type NVM chip are coupled to the same channel. A programming operation needs to be performed on the SLC chip first, and then on the TLC chip. The media interface controller stores a microinstruction sequence for performing the programming operation. The microinstruction for setting the type tag first selects the NVM configuration register set corresponding to the SLC type, so that in the subsequent execution of the microinstruction sequence for performing the programming operation, the signal generation unit generates a signal on the channel based on the NVM configuration register set corresponding to the SLC type. Next, the NVM configuration register group corresponding to the TLC type is selected through the microinstruction for setting the type tag, so that in the subsequent execution of the microinstruction sequence for implementing the programming operation, the signal generation unit generates a signal on the channel according to the NVM configuration register group corresponding to the TLC type.

[0133] Figure 8 A block diagram of a media interface controller according to another embodiment of the present application is shown.

[0134] When different types of NVM chips are mixed on a channel, an application scenario arises in which a high-speed, low-storage-density NVM chip acts as a cache for a high-density NVM chip. In such an application scenario, there is a need to copy data from one NVM chip to another NVM chip, or from a high-speed, low-density storage unit (e.g., an SLC page) to a high-density storage unit (e.g., a TLC page) within the channel. Typically, the storage command processing unit of the control component issues a media interface command to the media interface controller to read data from the SLC page and temporarily store it in the storage unit of the control component; then, the storage command processing unit issues another media interface command to write the temporarily stored data to the TLC page. However, such an operation requires the copied data to be moved from the media interface controller to the outside of the media interface controller, and a longer data movement distance means higher power consumption and more time consumption.

[0135] according to Figure 8 In the illustrated embodiment, data copying between different physical pages within a channel is completed within the media interface controller.

[0136] Compared with the media interface controller shown in Figure 4, Figure 8The media interface controller also includes multiple cache units (810 and 812). The cache units (810 and 812) are architecturally visible operation objects that can be described by the media interface controller's microinstructions as source or destination addresses for data transfer. The cache units are sized to accommodate data corresponding to read or program commands from the NVM chip.

[0137] Channel 820 couples SLCNVM chip 840 and TLCNVM chip 842 , and channel 825 couples SLCNVM chip 844 and TLCNVM chip 846 .

[0138] In order to move the data of SLCNVM chip 840 to TLCNVM chip 842, according to Figure 8 In this embodiment, the media interface controller issues a read command to SLCNVM chip 840, with the destination address of the data read being cache unit 810. Next, the media interface controller issues a program command to TLCNVM chip 842, with the source address of the data to be written being cache 810 (the data to be moved, previously read from SLCNVM chip 840). Thus, the data being moved within the channel moves only within the media interface controller and is not transmitted outside of the media interface controller. Furthermore, the move operation is accomplished by combining the existing microinstruction sequence for reading data from the SLCNVM chip with the microinstruction sequence for programming data to the TLCNVM chip, eliminating the need to provide a new microinstruction sequence.

[0139] Optionally, the page size of the SLCNVM chip (e.g., 4KB) is different from that of the TLCNVM chip (e.g., 16KB). To move data, multiple read commands are used to read data from multiple pages (e.g., 4 pages) of the SLCNVM chip and store them in the cache unit. The data is then programmed into the TLCNVM chip using a single program command.

[0140] The cache units (810 and 812) also handle the common operations of programming data into and reading data from the NVM chip. To program data, a microinstruction sequence is executed to move the data to be programmed from the outside of the media interface controller to the cache unit. The data in the cache unit is then moved to the NVM chip via an operating signal driver. To read data, a microinstruction sequence is executed to move the data to be read from the NVM chip to the cache unit and then to the outside of the media interface controller.

[0141] Optionally, cache units are associated with channels. For example, cache unit 810 is dedicated to channel 820, while cache unit 812 is dedicated to channel 825. Thus, in order to copy data from SLCNVM chip 844 to TLCNVM chip 846, cache unit 812 associated with channel 825 is used to temporarily store the data to be copied.

[0142] Still optionally, the cache units are distributed among the channels, so that data can be copied between NVM chips located in different channels through the cache units of the media interface controller.

[0143] Still optionally, a media interface command provided to the media interface controller indicates a copy operation, where the copy operation indicates the physical address of the NVM chip to be read and the physical address of the NVM chip to be programmed. A microinstruction sequence for processing the media interface command (see also FIG4 ) identifies the media interface command indicating the copy operation and sequentially calls a microinstruction sequence for issuing a read command to the NVM chip and a microinstruction sequence for issuing a write command to the NVM chip. The two microinstruction sequences use the same cache unit to transfer the data to be copied.

[0144] Figure 9A A block diagram of a media interface controller according to still another embodiment of the present application is shown.

[0145] Figure 9A In the example, within the same channel, the SLCNVM chip is used as a write cache for the MLCNVM chip, while only the TLCNVM chip is used to provide the physical address space of the storage device. For example, the capacity of SLCNVM chips 940 and 944 is 16GB, and the capacity of MLCNVM chips 942 and 946 is 128GB. Although channels 920 and 925 are coupled to NVM chips with a total capacity of 288GB, the storage media management unit (also see Figure 2 ) uses a physical address space size of 256 GB (provided by MLC NVM chips 942 and 946), so the storage medium management unit does not need to care about the internal structure of the SLC NVM chip and the allocation of its storage resources.

[0146] according to Figure 9A In an embodiment, the storage command processing unit provides a media interface command to the media interface controller indicating attributes of data to be written, and the media interface controller determines whether to write the data indicated by the media interface into the SLCNVM chip or the MLCNVM chip based on the data attributes and the available space of the SLCNVM chip.

[0147] As an example, the media interface command indicates a programming operation and the data to be written is hot data (data to be frequently updated) or data that requires low processing delay. The media interface command also indicates that the physical address to be written is physical block 2 (also recorded as M2, where M indicates the MLCNVM chip) of the MLCNVM chip 942. The microinstruction sequence for media interface command processing (also see Figure 4) allocates an available physical block (for example, physical block 0, also recorded as S0, where S indicates the SLCNVM chip) from the SLCNVM chip 940 for the media interface command, and calls a microinstruction sequence that issues a programming command to the SLCNVM chip to write the data to physical block S0. Optionally, the microinstruction sequence also performs changes such as physical page addresses through the corresponding type of NVM configuration register group to issue a programming command to the SLCNVM chip 940.

[0148] In response to the physical block M2 being allocated the available physical block S0 from the SLCNVM chip 940, the microinstruction sequence for media interface command processing also records the association relationship between the physical block T2 and the physical block S0 in the block mapping table. Figure 9A In an embodiment, the media interface controller provides a block mapping table for each channel, wherein entries in the table associate physical blocks of the MLCNVM chip with physical blocks of the SLCNVM chip serving as its cache. It is understood that the physical blocks of each MLCNVM chip may correspond to the physical blocks of multiple SLCNVM chips; and the address format configuration register of the NVM configuration register group records the mapping method from the physical pages of the MLCNVM chip to the physical pages of the SLCNVM chip.

[0149] Figure 9A In the example, the entries in the block mapping table provide mapping at the physical block level. The number of physical blocks in the NVM chip is relatively small (compared to the number of physical pages), so the overall size of the block mapping table is not large and can be accommodated by the media interface controller. The storage media management unit (also see Figure 2 ) Maintain page-level mapping, for example, record the corresponding physical address for each 4KB segment of the logical address space. For large-capacity storage devices, page-level mapping requires a large amount of memory space.

[0150] Return to view Figure 9A In response to receiving another media interface command (denoted as MI-1), which instructs writing data to physical block 2 (M2) of MLCNVM chip 942. Regardless of whether the media interface command indicates hot data or data requiring low processing latency, the microinstruction sequence for media interface command processing (also see FIG. 4 ) identifies through the block mapping table that physical block M2 is mapped to physical block 0 (S0) of SLCNVM chip 940, and invokes the microinstruction sequence that issues a programming command to the SLCNVM chip to write data to physical block S0.

[0151] Alternatively or further, in response to receiving another media interface command (denoted as MI-2), which instructs to read data from physical block 2 (M2) of the MLCNVM chip 942. The microinstruction sequence for media interface command processing (also see Figure 4) identifies through the block mapping table that physical block M2 is mapped to physical block 0 (S0) of the SLCNVM chip 940, which calls the microinstruction sequence for issuing a read command to the SLCNVM chip to read data from physical block S0 in response to the media interface command (MI-2). It can be understood that during the execution of the microinstruction sequence for issuing a read command to the SLCNVM chip, the physical address indicated by the media interface command (MI-2) is converted into a physical address for the SLCNVM chip through the NVM configuration register group.

[0152] Furthermore, the storage medium management unit (see also Figure 2 ) In response to the processing of the media interface command (MI-1), the physical address used in the page-level mapping table is still the address of the physical block 2 from the MLCNVM chip 942, rather than the address of the SLCNVM chip 940. Figure 9A In an embodiment, the SLCNVM chip of each channel serves as a cache for the MLCNVM chip of the same channel, and the storage medium management unit only uses the physical address of the MLCNVM chip in the page-level mapping table instead of the physical address of the SLCNVM chip. It can be considered that the SLCNVM chip is invisible to the storage medium management unit.

[0153] Still optionally, due to the inconsistency of block sizes, blocks 0 and 1 (denoted as S0 and S1) of the SLCNVM chip 940 are mapped together to block 2 (M2) of the MLCNVM chip 942, wherein the combined capacity of blocks S0 and S1 is not less than the capacity of block M2. In response to blocks S0 and S1 being full, the media interface controller also copies the data of blocks S0 and S1 to block M2, for example, by combining Figure 8The embodiment shows a method of copying data. For example, the microinstruction memory of the media interface controller also stores a microinstruction sequence for managing the cache. In response to the multiple physical blocks of the SLCNVM chip mapped to the physical blocks of the MLCNVM chip being full, in response to the SLCNVM chip being full (no available physical blocks, and all used physical blocks are full), periodically, or when the channel 920 is idle, the microinstruction sequence for managing the cache is executed or the microinstruction sequence for the copy operation is called to implement the copy from the SLC NVM chip 940 to the MLCNVM chip 942. After the copy is completed, the one or more physical blocks of the copied SLCNVM chip are erased, and the block mapping table is also updated, and the physical blocks of the copied SLCNVM chip are deleted from the block mapping table. Since it is deleted from the block mapping table, next, if a media interface command indicating a read operation is received, the microinstruction sequence for media interface command processing will query the block mapping table and will recognize that the data to be read is recorded in the MLCNVM chip rather than the SLCNVM chip, and thus call the microinstruction sequence to issue a read command to the MLCNVM chip. And optionally, the microinstruction sequence for media interface command processing further sets a type tag field of the called microinstruction sequence to indicate the type of the NVM chip to be accessed.

[0154] Figure 9B A block diagram of a media interface controller according to yet another embodiment of the present application is shown.

[0155] Figure 9B In the example, the storage medium management unit knows the internal structure of the SLCNVM chip and the allocation of its storage resources. Therefore, the physical address of the SLCNVM chip will exist in the page-level mapping table maintained by the storage medium management unit. Optionally, the page-level mapping table also marks the NVM chip type or characteristics of each physical address (for example, the physical address is provided by the MLCNVM chip or the SLCNVM chip). Figure 9B Figure 2 shows the physical address space managed by the storage medium management unit. The physical address space ranges from physical address P0 to physical address Pn. Physical addresses P0-Pm are provided by the SLCNVM chip, while physical addresses Pm+1 to Pn are provided by the MLCNVM chip. Figure 9B In the physical address space table, the second column indicates which physical block provides the physical address of the row.

[0156] The storage command processing unit then provides the media interface controller with a media interface command indicating a physical address. The microinstruction sequence for media interface command processing (see also FIG4 ) invokes the corresponding microinstruction sequence to issue a storage media access command to the NVM chip based on the physical address indicated by the media interface command. This eliminates the need for the media interface controller to maintain a mapping between the physical blocks of the SLCNVM chip and the MLCNVM chip.

[0157] Figure 10 A block diagram of a media interface controller according to another embodiment of the present application is shown.

[0158] The media interface controller includes a microinstruction memory, a microinstruction execution unit, a signal driver, a scheduler, and a status register. A sequence of microinstructions executed by the microinstruction execution unit together with its status data is called a thread. The scheduler is coupled to the status register, the microinstruction memory, and the microinstruction execution unit, and the microinstruction execution unit is coupled to the signal driver. In this embodiment, threads correspond one-to-one to LUNs of, for example, an NVM chip. Each thread is used to process storage medium access commands that access one LUN. For a media interface command indicating a copy operation, it accesses two different LUNs, and the NVM chips to which these two LUNs belong may be of different types. According to an embodiment of the present application, a single thread processes the media interface command indicating a copy operation. The status register stores status data of one or more threads. The thread also has a cache unit.

[0159] The running thread has control of the media interface controller. The thread yields by executing the yield microinstruction. When the thread yields, its status data is recorded in the status register. And in response, such as Figure 10 As shown, the scheduler selects one of one or more threads for execution by the microinstruction execution unit (this process is called scheduling, or scheduling a thread). The scheduled thread obtains its status data from the status register. For example, based on the media interface command to access a certain LUN, the scheduler schedules the thread corresponding to that LUN, so that the thread processes the media interface command during execution. Still using this example, when thread A yields, it is processing media interface command C but has not yet completed it. When the scheduler schedules thread A again, based on the obtained status information, thread A is able to resume processing media interface command C from the point where it yielded.

[0160] See Figure 10, the media interface controller includes channels (1020 and 1025). Channel 1020 couples SLCNVM chip 1040 and TLCNVM chip 1042. SLCNVM chip 1040 includes two LUNs (respectively denoted as LUN (B) and LUN (C)). SLCNVM chip 1040 includes two LUNs (respectively denoted as LUN (A) and LUN (C)). As an example, three threads (respectively denoted as thread A, thread B, and thread C) are running in the media interface controller, each using a cache unit (respectively denoted as cache unit A, cache unit B, and cache unit C). Thread A is accessing LUN (A), thread B is accessing LUN (B), and thread C is copying data from LUN (C) of SLCNVM chip 1040 to LUN (C) of TLCNVM chip 1042.

[0161] Thread C executes its microinstruction sequence, issuing a read command to LUN (C) of SLCNVM chip 1040 via the signal driver, moving the read data to cache unit C. It then issues a program command to LUN (C) of TLCNVM chip 1042 via the signal driver, writing the data in cache unit C to LUN (C) of TLCNVM chip 1042. During this process, thread C can yield. By using a single thread to access both LUNs to process the copy command, cache unit C remains owned by thread C during the yield period and is not used by other threads, ensuring that the copied data is not corrupted.

[0162] Although preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this application. Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if such changes and modifications fall within the scope of the claims of this application and their equivalents, then this application is intended to include such changes and modifications.

Claims

1. A method for processing a media interface command, characterized in that: The method is applied to a media interface controller, wherein the media interface controller is coupled to a plurality of NVM chips via a plurality of channels, wherein a first NVM chip of the plurality of NVM chips is of a first type, and a second NVM chip of the plurality of NVM chips is of a second type; wherein the first type is different from the second type; the media interface controller includes a plurality of microinstruction sequences, wherein the plurality of microinstruction sequences includes a microinstruction sequence corresponding to each NVM chip type and used to provide various storage medium access commands to the NVM chip; and the method includes: Obtaining a media interface command, executing a microinstruction sequence for media interface command processing to identify the type of NVM chip to be accessed by the media interface; wherein the type of NVM chip includes an NVM operating according to the Toggle standard or the ONFI standard; According to the identified type, selecting and executing a microinstruction sequence corresponding to the type from the multiple microinstruction sequences to obtain a feature of the NVM chip to be accessed; A storage medium access command for accessing the NVM chip is generated according to the acquired feature.

2. The method according to claim 1, characterized in that In response to the type being a first type, executing a first microinstruction sequence corresponding to the first type; The first microinstruction sequence obtains the feature during execution, and generates a storage medium access command for accessing the NVM chip according to the obtained feature.

3. The method according to claim 2, characterized in that The first microinstruction sequence includes a microinstruction for generating a command header of a storage medium access command, a microinstruction for generating an address of the storage medium access command, and / or a microinstruction for generating data of the storage medium access command; Execute the microinstruction for generating the command header of the storage medium access command to generate the command header of the storage medium access command, and also obtain time constraint information from the time constraint configuration register of the NVM configuration register group to generate the command header ALE signal and / or CLE signal for the storage medium access command on the channel.

4. The method according to any one of claims 1 to 3, characterized in that In response to obtaining a media interface command instructing to move data from a first type NVM chip to a second type NVM chip, executing a microinstruction sequence for a copy operation to provide a read command to the first NVM chip, record the read data in a first cache unit, and provide a program command to the second NVM chip to write the data in the first cache unit into the second NVM chip; The first NVM chip serves as a cache for the second NVM chip; The blocks of the second NVM chip and one or more blocks of the first NVM chip are recorded in association in entries of the block mapping table.

5. The method according to claim 4, characterized in that In response to receiving a first media interface command instructing to write data to a first block of the second NVM chip, accessing the block mapping table to obtain a second block of the first NVM chip associated with the first block; The write data indicated by the first media interface command is written into the second block by a microinstruction sequence for providing a programming command to the first type NVM chip.

6. The method according to claim 5, characterized in that The write data size indicated by the first medium interface command is the physical page size of the first block; When executing a microinstruction sequence for providing a programming command to the first type of NVM chip, a conversion method between a physical page address of the second NVM chip and a physical page address of the first NVM chip is obtained through an address format configuration register of an NVM configuration register group corresponding to the same type tag, and a physical page address of the second block is generated.

7. The method according to claim 5 or 6, characterized in that In response to receiving a second media interface command instructing to write data to a third block of the second NVM chip, accessing the block mapping table reveals that there is no record of the third block in the block mapping table; and writing the write data indicated by the second media interface command into the third block via a microinstruction sequence for providing a programming command to the second type of NVM chip.

8. The method according to any one of claims 1 to 3, characterized in that Also includes: Scheduling multiple threads, where the sequence of microinstructions executed along with their state is called a thread; A first plurality of threads among the plurality of threads corresponds one-to-one to a LUN of the NVM chip, each of the first plurality of threads corresponding to a microinstruction sequence for providing a storage medium access command to the NVM chip; A second thread of the plurality of threads corresponds to a LUN of the first NVM chip and a LUN of the second NVM chip where data is to be copied, and the second thread corresponds to a microinstruction sequence for the copy operation.

9. The method according to claim 8, characterized in that In response to recognizing a media interface command indicating a move operation, scheduling a first thread and a second thread, wherein both the first thread and the second thread are assigned a first cache unit; The first thread reads data from the first NVM chip and stores the data in the first cache unit according to a microinstruction sequence for providing a read command to the NVM chip; The second thread writes the data of the first cache unit into the second NVM chip according to a microinstruction sequence for providing a programming command to the NVM chip.

10. An information processing device comprising a processor and a memory, characterized in that: The processor stores a program, and when the program is executed by the processor, the medium interface command processing method according to any one of claims 1 to 9 is implemented.

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