A device and method for a reconstruction-calculation-quantization method of a storage device

Abstract

A device is disclosed. The device may include an input buffer that receives a first low bit width message. A reconstruction circuit may implement a reconstruction function on the first low bit width message to generate a first high bit width message. A calculation circuit may implement a calculation function on the first high bit width message to generate a second high bit width message. A quantization circuit may implement a quantization function on the second high bit width message to generate a second low bit width message. A decision buffer may then store the second low bit width message. The reconstruction function and the quantization function may vary depending on the iteration and layer of the device.

Description

[0001] Related application data

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 083,862 filed on September 25, 2020, U.S. Provisional Patent Application Serial No. 63 / 128,841 filed on December 21, 2020, and U.S. Provisional Patent Application Serial No. 17 / 204,936 filed on March 17, 2021, all of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to storage devices and, more particularly, to improved estimation of codewords. Background Art

[0004] Estimating information bits from encoded codewords stored in a storage device, also known as decoding, can be computationally difficult. Dedicated circuitry for decoding can use resources that might be better used for other purposes. But with limited resources allocated to the decoder, the performance of the decoder may be reduced—that is, the decoder may require more time to make its estimates—which may slow down other processes within the storage device that may rely on those codewords. Limited resources allocated to decoding may also cause the decoder to estimate the original information bits inaccurately: that is, more decoding failures.

[0005] There remains a need to decode information faster and more accurately without requiring significant additional resources. Summary of the invention

[0006] Embodiments of the present disclosure include a low-density parity check (LDPC) decoder. The LDPC decoder can use a reconstruction-computation-quantization (RCQ) method, where each layer in the decoder potentially implements a different reconstruction function and quantization function. In this way, improved decoder performance can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings described below are examples of how embodiments of the present disclosure may be implemented and are not intended to limit the embodiments of the present disclosure. Various embodiments of the present disclosure may include elements not shown in a particular drawing and / or may omit elements shown in a particular drawing. The accompanying drawings are intended to provide illustrations and may not be drawn to scale.

[0008] Figure 1A system including a storage device that can use a reconstruction-compute-quantization (RCQ) method in a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder according to an embodiment of the present disclosure is shown.

[0009] Figure 2 The embodiment according to the present disclosure is shown Figure 1 Details of the machine.

[0010] Figure 3 1 shows an embodiment according to the present disclosure, when implemented as a solid state drive (SSD), Figure 1 Details of the storage device.

[0011] Figure 4 The embodiment according to the present disclosure is shown Figure 3 The overall layout of QC-LDPC codes in SSD.

[0012] Figure 5 The embodiment according to the present disclosure is shown Figure 3 Overall layout of the RCQ method in QC-LDPC codes in SSD.

[0013] Figure 6 The embodiment according to the present disclosure is shown Figure 4 The architecture of the decoder.

[0014] Figure 7 FIG. 1 shows a table storing a reconstruction function and a quantization function according to an embodiment of the present disclosure. Figure 6 of memory.

[0015] Figure 8 shows a comparison using Figure 4 A graph showing the error rate of the decoder compared to other decoders.

[0016] Fig. 9 shows a comparison using Figure 4 A graph showing the average iteration time of the decoder compared with other decoders.

[0017] Figure 10A-10B The use of the embodiment according to the present disclosure is shown Figure 6 Flowchart of an example process for a decoder. DETAILED DESCRIPTION

[0018] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. In the following detailed description, many specific details are set forth to enable a thorough understanding of the present disclosure. However, it should be understood that one of ordinary skill in the art may practice the present disclosure without these specific details. In other examples, well-known methods, processes, components, circuits, and networks are not described in detail to avoid unnecessarily obscuring aspects of the embodiments.

[0019] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first module can be referred to as the second module, and similarly, the second module can be referred to as the first module, without departing from the scope of this disclosure.

[0020] The terms used in the description disclosed herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the description of the present disclosure and the appended claims, the singular forms of "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more related listed items. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof. The components and features of the accompanying drawings are not necessarily drawn to scale.

[0021] Quasi-cyclic low-density parity-check (QC-LDPC) codes are a family of structured low-density parity-check (LDPC) codes, which are themselves various linear block codes characterized by a parity-check matrix H consisting of square sub-matrices that are either zero matrices or cyclic permutations (also called circulants) of the identity matrix. QC-LDPC codes can be used in solid-state drives (SSDs) or other storage devices because they can reduce data processing latency and improve throughput.

[0022] The QC-LDPC code can be represented by the U×W matrix H p In a compact way. H p Each element in is either 0 or σ i , respectively represent the zero matrix and the circulant determinant with cyclic shift i. If the size of the square submatrix is ​​m×m, then equation (1) should hold:

[0023]

[0024] Unlike flooding scheduled decoding, layered decoding can utilize already updated messages and therefore converge faster. One implementation of layered decoding is horizontal layered decoding. By dividing the check nodes into U consecutive groups, QC-LDPC codes can be compatible with horizontal layered decoding. Using QC-LDPC with horizontal layered decoding may result in each variable node being connected to at most one check node in each layer.

[0025] The MinSum decoder is a low-complexity decoder for QC-LDPC codes that can be used. In the i-th iteration, the horizontally hierarchical MinSum decoder can update the soft information of the variable node h connected to the check node l by:

[0026]

[0027]

[0028]

[0029] As an alternative to the MinSum decoder, a reconstruction-computation-quantization (RCQ) decoder can be used for both variable node and check node operations. The decoder can contain three parts:

[0030] 1. Reconstruction function R(·): R(·) can receive low-bit external messages u from the nodes it is connected to. i , and u i Mapped to the internal high bit message r i .

[0031] 2. Calculation function From the high bit message r i Calculate the high bit output r out .

[0032] 3. Quantization function Q(·): Q(·) can convert r out Quantized into low-bit external message u iut And u out Passed to connected nodes.

[0033] If the computation module implements belief propagation, such a decoder can be called belief propagation RCQ (bpRCQ); if the computation module implements MinSum, such a decoder can be called MinSum RCQ (msRCQ). The triplet (z) containing the precision of the external message, the internal message of the check node, and the internal message of the variable node e,z c ,z v ) can be used to describe the accuracy of the RCQ decoder. Finally, ∞ can be used to represent floating point operations.

[0034] In contrast to the RCQ decoder, a layered RCQ (L-RCQ) decoder can be described. The structure of the L-RCQ decoder can be different from the basic structure of the RCQ decoder because the function and Can be layer-specific and iteration-specific. A variable node quantization function that can be used to represent layer l in iteration i; can be similarly understood as a variable node reconstruction function representing layer l in iteration i. The layer-specific parameters of the L-RCQ decoder can be selected so that the probability density of the output messages from each layer can be tracked.

[0035] In order to construct the parameters of each layer in the L-msRCQ decoder, the probability density function (pdf) of the output message in each layer should be known. Layered mutual-information-maximization discrete density evolution (L-MIM-DDE) can be used for this purpose. In L-MIM-DDE, the joint probability between the code bits and the output message T from the check nodes and variable nodes can be tracked in each iteration. X={0,1},T={0,...,2 n -1} can be used to represent the probability distribution of the check node output messages of layer l in iteration i. Similarly, It can be used to represent the probability distribution of variable node output messages of layer l in iteration i.

[0036] If the size of the layer is equal to the lifting size m, then it can be p Calculate L-MIM-DDE. Layer l can be equivalent to H p The degree of the check node l can be expressed as To express.

[0037] L-MIM-DDE can be implemented using an Additive White Gaussian Noise (AWGN) channel. Hierarchical dynamic quantization (HDQ) can be used to implement MIM quantization of channel observations. ch (X,T),X={0,1},T={0,...,2n -1} can be used to represent the quantized channel probability distribution.

[0038] In iteration i and layer l, the probability distribution of the output message from the variable node can be calculated as:

[0039]

[0040] The binary operator can be used to calculate the sum of the log-likelihood ratios (LLRs) of two input messages:

[0041]

[0042] Equation (6) does not assume that all incoming messages from different layers have the same probability. Instead, Equation (6) can utilize the updated messages in a timely manner: when k < l, Equation (6) can utilize the updated messages, and when k > l, Equation (6) can use the old messages. Therefore, Equation (6) can solve the problem of information mismatch.

[0043] Since the L-RCQ decoder can use layer-specific RCQ parameters, all messages assigned to different variable nodes connected to the same layer can have the same probability distribution. Then it can be calculated as:

[0044]

[0045] Finally, HDQ quantizes and can be calculated as:

[0046]

[0047] Because the L-MIM-DDE can be implemented using a symmetric AWGN channel. If is used to represent the LLR of the message t from the variable node connected to layer l in iteration i, then can be calculated as:

[0048]

[0049] Due to symmetry, has the following properties:

[0050] Monotonically increasing: when t 1 > t 2 then,

[0051] Symmetry:

[0052] Based on the above two properties, the MinSum operation can be implemented for their labels:

[0053] MS(t 1 ,t 2 )=l -1 [min(|l(t 1 )|,|l(t 2 )|)·sgn(l(t 1 ))·sgn(l(t 1 ))] Equation (10)

[0054] Among them, l -1 (m) identifies the label whose LLR is m.

[0055] Since all messages from different variable nodes in each layer are assumed to have the same probability density, It can be calculated as:

[0056]

[0057] For msRCQ decoder:

[0058]

[0059] Since equation (12) does not increase the cardinality of the output message, we can deduce and An example of the pseudo code of L-MIM-DDE is shown below. A one step annealing (OSA) algorithm can be a coarse quantization algorithm that reduces the computation required for HDQ.

[0060]

[0061] Algorithm 1

[0062] In one embodiment of the code, the following properties may be used: n=37632, r=0.8707, m=128, and I T = 20. 5-bit L-msRCQ can be compared with 5-bit msRCQ, BP and fixed point offset MinSum decoders. All decoders can be implemented with horizontal hierarchical scheduling with a layer size of 128.

[0063] 5-bit L-msRCQ seems to perform better than 5-bit msRCQ and 10-bit Offset MinSum. In addition to error correction performance, L-msRCQ seems to have a lower average iteration time than msRCQ. When becomes high, the average iteration time of the L-msRCQ decoder using belief propagation is comparable to that of the 10-bit offset MinSum. The better frame error rate (Frame Error Rate, FER) and lower average iteration time of L-msRCQ can be a matter of layered msRCQ parameter design that tracks the probability density of messages in each layer. Finally, Table 1 can summarize the FER and average iteration time of the three decoders, and it seems to show that among the three decoders, the L-RCQ decoder has the best performance.

[0064] OffsetMinSum RCQ L-RCQ Bit width 10 5 5 Average iteration time 7.5 12.5 7.5

[0065] Table 1: Performance comparison between the studied decoders

[0066] Figure 1 A system including a storage device that can use a reconstruction-computation-quantization (RCQ) method in a quasi-cyclic low-density parity check (LDPC) decoder according to an embodiment of the present disclosure is shown. Figure 1 In the embodiment of the present invention, the machine 105 may include a processor 110, a memory 115, and a storage device 120. The processor 110 may be any kind of processor. (For ease of illustration, the processor 110 and other components discussed below are shown outside the machine: embodiments of the present disclosure may include these components inside the machine.) Although Figure 1 A single processor 110 is shown, but the machine 105 may include any number of processors, each of which may be a single-core or multi-core processor, each of which may implement a Reduced Instruction Set Computer (RISC) architecture or a Complex Instruction Set Computer (CISC) architecture (among other possibilities), and which may be mixed in any desired combination.

[0067] The processor 110 may be coupled to a memory 115. The memory 115 may be any kind of memory, such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), permanent random access memory, ferroelectric random access memory (FRAM), or non-volatile random access memory (NVRAM), such as magnetoresistive random access memory (MRAM), etc. The memory 115 may also be any desired combination of different memory types and may be managed by a memory controller 125. The memory 115 may be used to store what may be referred to as "short-term" data: that is, data that is not expected to be stored for a long period of time. Examples of short-term data may include temporary files, data used locally by an application (which may be copied from other storage locations), etc.

[0068] The processor 110 and the memory 115 may also support an operating system under which various applications may run. These applications may issue requests (also referred to as commands) to read data from or write data to the memory 115 or the storage device 120. The storage device 120 may be used, for example, to store initial parameters for initializing a simulation (or a range of values ​​for the initial parameters, and what type of behavior the range of values ​​represents). The storage device 120 may be accessed using a device driver 130. Although Figure 1 The general term "storage device" is used, but embodiments of the present disclosure may include any storage device format that can utilize a low-density parity check (LDPC) decoder using a reconstruction-computation-quantization (RCQ) method, examples of which may include hard disk drives and solid-state drives (SSDs). Any reference to "SSD" below should be understood to include such other embodiments of the present disclosure.

[0069] Figure 2 The embodiment according to the present disclosure is shown Figure 1 Details of the machine 105. Figure 2 In the embodiment of the present invention, generally, the machine 105 includes one or more processors 110, which may include a memory controller 125 and a clock 205, which may be used to coordinate the operation of the machine components. The processor 110 may also be coupled to a memory 115, which may include, for example, a random access memory (RAM), a read-only memory (ROM), or other state preservation medium. The processor 110 may also be coupled to a storage device 120 and a network connector 210, which may be, for example, an Ethernet connector or a wireless connector. The processor 110 may also be connected to a bus 215, to which a user interface 220 and input / output (I / O) interface ports that may be managed using an I / O engine 225, as well as other components, may be attached.

[0070] Figure 3 It is shown that according to an embodiment of the present disclosure, when implemented as an SSD, Figure 1 Details of the storage device 120. Figure 3 In the embodiment, the SSD 120 may include an interface 305. The interface 305 may be used to connect the SSD 120 to the Figure 1 The SSD 120 may include more than one interface 305: for example, one interface may be used for block-based read and write requests, and another interface may be used for key-value read and write requests. Figure 3 It is recommended that interface 305 is Figure 1The physical connection between SSD 120 and machine 105 can be represented by interfaces 305, but interfaces 305 can also represent protocol differences that can be used across a common physical interface. For example, SSD 120 can be connected to machine 105 using a U.2 or M.2 connector, but can support both block-based requests and key-value requests: processing different types of requests can be performed by different interfaces 305.

[0071] SSD 120 may also include a host interface layer 310, which may manage interface 305. If SSD 120 includes more than one interface 305, a single host interface layer 310 may manage all interfaces, SSD 120 may include a host interface layer for each interface, or some combination thereof may be used.

[0072] SSD 120 may also include an SSD controller 315, various channels 320-1, 320-2, 320-3, and 320-4, and various flash memory chips 325-1, 325-2, 325-3, 325-4, 325-3, 325-6, 325-7, and 325-8 may be arranged along these channels. SSD controller 315 may manage sending read requests and write requests to flash memory chips 325-1 to 325-8 along channels 320-1 to 320-4. Figure 3 Four channels and eight flash die are shown, but embodiments of the present disclosure may include any number (one or more, without limitation) of channels including any number (one or more, without limitation) of flash die.

[0073] Within each flash chip, space can be organized into blocks, which can be further subdivided into pages, and can be grouped into superblocks. A page is typically the smallest unit of data that can be read or written on an SSD. The page size can vary as desired: for example, a page can be 4KB of data. If less than a full page is to be written, the remaining space is "unused".

[0074] Although pages can be written to and read from, SSDs do not typically allow data to be overwritten: that is, existing data cannot be replaced "in place" with new data. Instead, when data is to be updated, the new data is written to a new page on the SSD, and the original page is invalidated (marked as ready to be erased). As a result, SSD pages typically have one of three states: free (ready to be written to), valid (contains valid data), and invalid (no longer contains valid data, but unusable until erased) (the exact names of these states can vary).

[0075] While pages can be written and read individually, blocks are the basic unit of data that can be erased. That is, pages are not erased individually: all pages in a block are typically erased at the same time. For example, if a block contains 256 pages, all 256 pages in a block are erased at the same time. This arrangement may cause some management issues for the SSD: if you choose to erase a block that still contains some valid data, you may need to copy the valid data to a free page elsewhere on the SSD before erasing the block. (In some embodiments of the present disclosure, the unit of erasure may be different from a block: for example, it may be a super block, where the super block may be a collection of multiple blocks.)

[0076] SSD controller 315 may include flash translation layer 330 (for storage devices that do not use flash memory, flash translation layer 330 may be more generally referred to as a logical to physical translation layer) and error correction code 335. Flash translation layer 330 may handle LBA or other logical IDs (such as Figure 1 The error correction code 335 may apply (i.e., create and / or use) error correction codes to data written to and / or read from the flash memory chips 325-1 to 325-8. Figure 3 One flash translation layer 330 is shown, but embodiments of the present disclosure may include any number (one or more, without limitation) of flash translation layers 330. Figure 3 One error correction code 335 is shown, but embodiments of the present disclosure may include any number (one or more, without limitation) of error correction codes 335 .

[0077] Although direct computation of codewords (or performing error correction using codewords directly) is possible, implementing such functions in hardware may use a large amount of resources (such as Figure 3 space on a printed circuit board within the SSD 120). In order to reduce the resources required to implement error correction, other methods may be used. One method that may be used is an iterative method. In an iterative method, the problem is not solved directly (possibly using complex formulas), but rather it is solved sequentially (possibly using simple formulas). For example, consider the problem of identifying the point where a complex curve intersects the x-axis (called the x-intercept). Although it is possible to use algebra to obtain the equation defining the curve and solve for where the x-intercept is, it may be very difficult to teach a computer or circuit to perform such a calculation. On the other hand, given the equation defining the function, calculating y=f(x) may be simple. If the derivative of the function (denoted as f′) is also easy to determine, then locating the x-intercept of the function f(x) is easily defined:

[0078] 1) Select point x 0 .

[0079] 2) Calculate the value y 0 =f(x 0 ).

[0080] 3) Calculate the value y′ 0 =f′(x 0 )(It means that at point (x 0 ,y 0 ) is the slope of the tangent line to the curve at ).

[0081] 4) Use the value x 0 ,y 0 and y′ 0 , we can calculate the point through which (x 0 ,y 0 ) with slope y′ 0 line.

[0082] 5) Find the x-intercept of the line just identified.

[0083] This process can then be repeated, replacing the point x with the most recently determined x-intercept. 0 Hopefully, each iteration of this sequence will result in a point on the curve that is closer to the x-intercept of the curve.

[0084] If the distance points located in successive iterations of the sequence eventually become close enough (within some amount, usually labeled Λ or ε) that the answers are considered effectively equivalent, the process is said to converge. Note that the circuitry involved in computing the value of the function or its derivative and in identifying the line that passes through a particular point with a particular slope is relatively simple (usually simpler than the circuitry involved in computing a direct solution to the problem). Thus, the problem of finding the x-intercept of a curve can be solved using fewer resources than attempting a direct solution to the problem. The tradeoff is that while a direct solution can identify the x-intercept immediately, using an iterative method such as the one described above may require any number of iterations before the sequence converges to a solution (if in fact the sequence even converges at all), and may therefore require more time.

[0085] In the same way, using an iterative approach to decode a codeword may use fewer resources, but may require multiple iterations to complete the calculations (i.e., for the decoder to identify a solution). Using an iterative approach, fewer resources—less circuitry and / or lower data bit widths—may be used when decoding a codeword.

[0086] But when an iterative approach is used rather than a direct approach, additional considerations may arise. The first consideration may be the number of iterations required to solve the problem. The number of iterations is not necessarily predictable: that is, the number of iterations may depend on the problem being solved. Consider again the iterative solution of finding the x-intercept of a curve. If each iteration is only a small improvement over the previous iteration as an approximation to the x-intercept, then many iterations may be required, whereas if the curve is approximately a straight line, then the x-intercept can be located quickly. A second consideration is the time required to complete the iterations to the solution. For example, if a single iteration of one algorithm will take, say, 10 seconds, while a single iteration of another algorithm will take, say, only 1 second, then 10 iterations of the second algorithm may be completed in the same time as a single iteration of the first algorithm. The algorithm with the smaller average iteration time may be superior to the algorithm with the larger average iteration time.

[0087] Of course, it may be important to balance the average iteration time and the resources used to implement the iterative algorithm. In some embodiments, faster performance may be desired, while in other embodiments, using fewer resources may be desired.

[0088] Figure 4 The embodiment according to the present disclosure is shown Figure 3 The overall layout of the QC-LDPC code in the SSD 120. Figure 4 , an error correction code 335 is shown. The error correction code 335 may include a QC-LDPC 405. The QC-LDPC may implement multiple layers, as shown by layer 410. The QC-LDPC 405 may include an encoder 415 (for generating error correction codewords) and a decoder 420 (for attempting to perform error correction using the error correction codewords).

[0089] Layers such as layer 410 represent a variation of the concept of iteration. Using layers 410, different functions may be used as part of a decoder (which may also be referred to as a device): the individual function(s) to be used may depend on the layer. On the other hand, iteration may represent a sequence using each layer 410 in a specified order. Thus, when discussing decoding a codeword using decoder 420, the method may involve both iterations and layers.

[0090] Figure 5 The embodiment according to the present disclosure is shown Figure 3 The overall layout of the RCQ method in the QC-LDPC code in SSD 120. Figure 5 In the example, various low bit width messages 505 may be input. The reconstruction circuit 510 may be applied to each input low bit width message 505. Figure 5Multiple copies of the reconstruction circuit 510 are shown, but in implementation, there may be only one reconstruction circuit 510, which may be repeated as needed for each input message 505, or there may be multiple reconstruction circuits 510, as desired.) The reconstruction circuit 510 may then generate a high bit width message 515 for each input low bit width message 505.

[0091] Various high bit width messages 515 may be input to a calculation circuit 520. The calculation circuit 520 (which may implement a function described as C(·) or F(·), and may also be described using other names, depending on the implementation) may then perform a function on the high bit width messages 515. For example, the calculation circuit 520 may generate a sum of the high bit width messages 515, or may implement a minimum function of the high bit width messages 515. Embodiments of the present disclosure may also use the calculation circuit 520 to implement other functions. The calculation circuit 520 may then generate a high bit width message 525.

[0092] The quantization circuit 530 may take the high bit width message 525 and quantize the high bit width message 525 to generate a low bit width message 535 .

[0093] In some embodiments of the present disclosure, the low bit width messages 505 and 535 may be 5 bits wide, while the high bit width messages 515 and 525 may be 10 bits wide. However, in other embodiments of the present disclosure, the low bit width messages 505 and 535 and the high bit width messages 515 and 525 may have other bit widths. However, consistent with the general meanings of "low" and "high", some embodiments of the present disclosure may include low bit width messages 505 and 535 having fewer bits than high bit width messages 515 and 525 (although other embodiments of the present disclosure may have more bits in the low bit width messages 505 and 535 than in the high bit width messages 515 and 525).

[0094] exist Figure 5 , the reconstruction circuit 510 is shown as implementing the function And the quantization circuit 530 is shown as implementing the function The subscript v can refer to Figure 4 The decoder 420 of FIG. 4 may be implemented using two nodes (a variable node and a check node). In some embodiments of the present disclosure, each node may perform its own reconstruction and quantization: Thus, the subscript v may reflect the fact that the reconstruction circuit 510 and the quantization circuit 530 are shown for variable nodes in the decoder 420. However, the reconstruction circuit and the quantization circuit for the check nodes may operate similarly (although using different functions for reconstruction and quantization).

[0095] function and The superscripts (l, i) in may reflect the fact that the specific reconstruction function and quantization function may depend on the iteration (i) and layer (l) at which the function is applied. and can vary per layer (but while each layer can use a different function, the function can be the same for corresponding layers across iterations). In other words, for example, and They can all be different functions, but and can be the same function. In other embodiments of the present disclosure, the function and can vary based on the layer and iteration of the sequence being executed. In other words, for example, and They can all be different functions.

[0096] function and Any desired technique may be used to determine. In some embodiments of the present disclosure, a layered mutual information maximization discrete density evolution (L-MIM-DDE) (or more generally, density evolution) technique may be used to design the function and As described in Algorithm 1 above.

[0097] Figure 6 The embodiment according to the present disclosure is shown Figure 4 The architecture of the decoder 420. Figure 6 In FIG. 4 , decoder 420 may include variable nodes 605 and check nodes 610. Variable nodes 605 may perform a basic implementation of the RCQ method, while check nodes 610 perform verification that the calculation was performed correctly.

[0098] Decoder 420 may include an input buffer 615 to receive, for example, Figure 4 The QC-LDPC 405 receives the low bit width message and uses the message to perform decoding. Then, the variable node 605 can use the reconstruction circuit 510, the calculation circuit 520 (in Figure 6 ) and quantization circuit 530 moves between low bit width and high bit width messages and performs calculations on the high bit width messages.

[0099] Variable node 610 is shown as including S h . S h can represent “soft” information about one or more coded bits. In each iteration, S h Can be used to make decisions about the coded bit(s).

[0100] The check node 610 may include its own reconstruction circuit 620 and quantization circuit 625, as well as computation circuit 630 (shown implementing a minimal function) to perform computations on high bit width messages. The check node 610 typically operates on low bit width messages: the reconstruction circuit 620 and quantization circuit 625 may map between label messages and likelihood ratio (LLR) messages used in the variable node 605. However, although Figure 6 The computation circuit 630 is shown as using the same bit width as the low bit width message in the variable node 605, but embodiments of the present disclosure may include a check node 610 using another bit width, such as a high bit width or yet another bit width.

[0101] Ultimately, once the message has converged to a solution, the output can be transmitted back to the requester (which can be, for example, Figure 4 The decoded / decoded bits may be the best approximation of the input data received by the decoder 420. That is, assuming that the data received by the decoder 420 may be erroneous, the output of the decoder 420 may be the input data corrected for the errors by the decoder 420.

[0102] The decoder 420 may also include a memory 640. The memory 640 may be used to store various functions used in different layers and different iterations of the function. and Please note that although Figure 6 Memory 640 is shown as part of decoder 420, but memory 640 may be located in Figure 3 other location in the SSD 120, or even Figure 1 Memory 115.

[0103] Although the function and can be implemented as a mathematical function that can operate on any possible input value, but in some embodiments of the present disclosure, the function and can be implemented as a lookup table. That is, given a particular low bit width message, the function The corresponding high bit width message can be stored, and given a specific high bit width message, the function can store the corresponding low bit width message. Therefore, the function and may not be a continuous function and may not even be defined for any input not listed in the lookup table. Figure 7As shown, these lookup tables may be stored in memory 640 .

[0104] Figure 7 FIG. 1 shows a table storing a reconstruction function and a quantization function according to an embodiment of the present disclosure. Figure 6 Memory 640. Figure 7 In FIG. 704 , tables 705 and 710 are shown. Table 705 stores the reconstruction function Table 710 shows the quantization function

[0105] exist Figure 7 , the table is organized in rows, each row representing a layer. In some embodiments of the present disclosure, the same function can be used for a specific layer across different iterations. In these embodiments of the present disclosure, each entry in tables 705 and 710 can be simply a definition of an appropriate function. However, in other embodiments of the present disclosure, different functions can be used not only in each layer, but also in each iteration. In these embodiments of the present disclosure, each row in tables 705 and 710 actually includes a table for the layer. Therefore, table 715 shows an expansion of the reconstruction function of layer 1. It can be seen that table 715 can show multiple entries, pairing low bit width messages with high bit width messages. For example, entry 720-1 pairs low bit width message 1,1 with high bit width message 1,1, entry 720-2 pairs low bit width message 1,2 with high bit width message 1,2, and entry 720-3 pairs low bit width message 1,i with high bit width message 1,i. In table 715, the identifier "1,1" can be understood as identifying layer 1, iteration 1, the identifier "1,2" can be understood as identifying layer 1, iteration 2, and the identifier "1,i" can be understood as identifying layer 1, iteration i. Entries of quantization functions can be managed similarly.

[0106] Although Figure 7 It is recommended that tables 705 and 710 be stored in layers, but embodiments of the present disclosure may organize tables 705 and 710. For example, if embodiments of the present disclosure use different functions in corresponding layers in different iterations, tables 705 and 710 may be organized by iteration and then by layer.

[0107] Figure 8 shows a comparison using Figure 4 A graph showing the error rates of decoder 420 and other decoders. Figure 8 In FIG. 4 , the decoder 420 identified as the 5-bit L-RCQ compares the 5-bit RCQ and the 10-bit MinSum. Figure 8 The graph of the frame error rate (FER) and the channel condition (denoted as E b / N 0 ) for comparison. b / N0 The larger the value of, the cleaner the channel can be, which indicates that the error rate can be low and the decoder can perform decoding more easily. Given a target FER, with a lower E b / N 0 A decoder that operates on a value may be superior because such a decoder can perform decoding even when the channel noise is large. It can be seen that the error rate of decoder 420 is always better than other decoders, even when compared with decoders using higher bit widths (e.g., 10-bit MinSum).

[0108] Fig. 9 shows a comparison using Figure 4 A curve diagram of the average iteration time of decoder 420 and other decoders. Fig. 9 In , the average iteration time is measured in time units, but it cannot be measured in seconds or fractions thereof: for example, the average iteration time can be measured in processor cycles. Figure 8 Same, Figure 4 The decoder 420 of is at least as good as the other decoders (and provides better average iteration time than 5-bit RCQ).

[0109] from Figure 8-Figure 9 It can be seen that when Figure 4 When the decoder 420 compares the 5-bit RCQ and the 10-bit MinSum, Figure 4 The decoder 420 is superior in at least one performance metric.

[0110] Figure 10A-10B The use of the embodiment according to the present disclosure is shown Figure 6 A flowchart of an example process of a decoder. Fig. 10A , at block 1005, Figure 4 The decoder 420 may receive an input message, which may be a low bit width message. At block 1010, Figure 5 The reconstruction circuit 510 can be used to construct a high bit width message from a low bit width message. At block 1015, Figure 5 The calculation circuit 520 can calculate another high bit width message from the first high bit width message. At block 1020, Figure 5 The quantization circuit 530 may quantize a high bit width message into a low bit width message.

[0111] At block 1025 ( Fig. 10B ), Figure 4 The decoder 420 of may check whether all layers of the iteration have been completed, and at block 1030, Figure 4 The decoder 420 may check at the end of an iteration, Figure 4The decoder 420 of has converged to a solution. If all layers are not completed, or if the message has not converged to a solution, the process can return to block 1010 for another layer / iteration. Otherwise, at block 1035, Figure 4 The decoder 420 may output the final message.

[0112] exist Figure 10A-10B In the drawings, some embodiments of the present disclosure are shown. However, those skilled in the art will recognize that other embodiments of the present disclosure are possible by changing the order of the blocks, by omitting blocks, or by including links not shown in the drawings. Any component or any combination of components described (for example, in a system diagram) can be used to perform one or more operations of the flowchart. The above operations are example operations and may involve various additional steps that are not explicitly covered. In addition, the time sequence of the operations may vary. All these variations of the flowchart are considered embodiments of the present disclosure, whether explicitly described or not.

[0113] Embodiments of the present disclosure provide technical advantages over the prior art. By using a function that varies with both layers and iterations and A decoder implemented by the method can perform with an average iteration time at least equal to that of the other decoders and with a bit width at least equal to that of the other decoders. Although the decoder may not be better than the other decoders when only one criterion is considered, the decoder is better than the other decoders according to at least one criterion when all criteria are considered.

[0114] The following discussion is intended to provide a brief summary description of one or more suitable machines in which specific aspects of the present disclosure may be implemented. One or more machines may be controlled at least in part by input from traditional input devices (such as keyboards, mice, etc.), instructions received from another machine, interaction with a virtual reality (VR) environment, biofeedback, or other input signals. As used herein, the term "machine" is intended to broadly cover a single machine, a virtual machine, or a system of communicatively coupled machines, virtual machines, or devices operating together. Exemplary machines include computing devices such as personal computers, workstations, servers, portable computers, handheld devices, phones, tablets, etc., and transportation equipment such as private or public transportation, such as cars, trains, taxis, etc.

[0115] One or more machines may include embedded controllers, such as programmable or non-programmable logic devices or arrays, application specific integrated circuits (ASICs), embedded computers, smart cards, etc. One or more machines may utilize one or more connections to one or more remote machines, such as through a network interface, modem, or other communication coupling. The machines may be interconnected through physical and / or logical networks, such as an intranet, the Internet, a local area network, a wide area network, etc. Those skilled in the art will appreciate that network communications may utilize a variety of wired and / or wireless short-range or long-range carriers and protocols, including radio frequency (RF), satellite, microwave, Institute of Electrical and Electronics Engineers (IEEE) 802.11, Bluetooth, optical, infrared, cable, laser, etc.

[0116] Embodiments of the present disclosure may be described by reference or in conjunction with related data including functions, procedures, data structures, applications, etc., which, when accessed by a machine, causes the machine to perform a task or define an abstract data type or a low-level hardware context. The related data may be stored in, for example, volatile and / or non-volatile memories, such as RAM, ROM, etc., or in other storage devices and their related storage media, including hard disks, floppy disks, optical storage devices, tapes, flash memories, memory sticks, digital video disks, biological storage devices, etc. The related data may be transmitted in a transmission environment including a physical and / or logical network in the form of packets, serial data, parallel data, propagated signals, etc., and may be used in a compressed or encrypted format. The related data may be used in a distributed environment and may be stored locally and / or remotely for machine access.

[0117] Embodiments of the present disclosure may include a tangible, non-transitory machine-readable medium including instructions executable by one or more processors, the instructions including instructions for performing elements of the present disclosure as described herein.

[0118] The various operations of the above methods may be performed by any suitable means capable of performing these operations, such as various (multiple) hardware and / or software components, circuits and / or (multiple) modules. Software may include an ordered list of executable instructions for implementing logical functions and may be embodied in any "processor readable medium" for use by or in conjunction with an instruction execution system, apparatus or device (such as a single-core or multi-core processor or a system containing a processor).

[0119] The blocks or steps and functions of the methods or algorithms described in conjunction with the embodiments disclosed herein may be directly embodied in hardware, software modules executed by a processor, or a combination of the two. If implemented in software, the function may be stored as one or more instructions or codes on or transmitted through a tangible non-transitory computer-readable medium. The software module may reside in a random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD ROMs, or any other form of storage medium known in the art.

[0120] The principles of the present disclosure have been described and illustrated with reference to the illustrated embodiments, and it will be appreciated that the illustrated embodiments may be modified in arrangement and detail and may be combined in any desired manner without departing from these principles. And, although the foregoing discussion has focused on specific embodiments, other configurations may also be considered. Specifically, even if expressions such as "according to embodiments of the present disclosure" are used herein, these phrases are meant to generally refer to the possibilities of the embodiments and are not intended to limit the present disclosure to specific embodiment configurations. As used herein, these terms may refer to the same or different embodiments that may be combined into other embodiments.

[0121] The foregoing illustrative embodiments should not be construed as limiting the disclosure thereof. Although several embodiments have been described, those skilled in the art will readily appreciate that many modifications to these embodiments are possible without materially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

[0122] The embodiments of the present disclosure may extend to the following statements, but are not limited thereto:

[0123] Statement 1. An embodiment of the present disclosure includes an apparatus comprising:

[0124] an input buffer for receiving a first low bit width message;

[0125] A reconstruction circuit, performing a reconstruction function on the first low bit width message to generate a first high bit width message;

[0126] a calculation circuit that performs a calculation function on the first high bit width message to generate a second high bit width message;

[0127] a quantization circuit that applies a quantization function to the second high bit width message to generate a second low bit width message; and

[0128] a decision buffer for storing the second low bit width message,

[0129] The reconstruction function and the quantization function vary according to at least one of an iteration and a layer of the device.

[0130] Statement 2. Embodiments of the present disclosure include an apparatus according to Statement 1, wherein the apparatus is part of a linear block code circuit.

[0131] Statement 3. Embodiments of the present disclosure include a device according to Statement 2, wherein the linear block code circuit is part of a memory device.

[0132] Statement 4. Embodiments of the present disclosure include a device according to Statement 3, wherein the storage device comprises a solid state drive (SSD).

[0133] Statement 5. Embodiments of the present disclosure include a device according to Statement 1, wherein the device includes at least two layers.

[0134] Statement 6. An embodiment of the present disclosure includes the apparatus of Statement 5, wherein the reconstruction circuit, the computation circuit, and the quantization circuit are used for at least two layers in an iteration.

[0135] Statement 7. An embodiment of the present disclosure includes an apparatus according to Statement 6, wherein:

[0136] The reconstruction circuit implementing the reconstruction function, the calculation circuit, and the quantization circuit implementing the quantization function generate a first decoding; and

[0137] The reconstruction circuit implementing a second reconstruction function, the calculation circuit, and the quantization circuit implementing a second quantization function generate a second decoding.

[0138] Statement 8. An embodiment of the present disclosure includes an apparatus according to Statement 7, wherein the reconstruction circuit implementing a third reconstruction function, the calculation circuit, and the quantization circuit implementing a third quantization function generate a third decoding based at least on a comparison of the first decoding and the second decoding.

[0139] Statement 9. An embodiment of the present disclosure includes the apparatus of Statement 7, wherein the reconstruction circuit implementing the reconstruction function, the computation circuit, and the quantization circuit implementing the quantization function generate the first decoding in a first layer; and

[0140] The reconstruction circuit implementing the second reconstruction function, the computation circuit, and the quantization circuit implementing the second quantization function generate the second decoding in a second layer.

[0141] Statement 10. An embodiment of the present disclosure includes the apparatus of Statement 7, wherein the reconstruction circuit implementing the reconstruction function, the computation circuit, and the quantization circuit implementing the quantization function generate the first decoding in a first iteration; and

[0142] The reconstruction circuit implementing the second reconstruction function, the computation circuit, and the quantization circuit implementing the second quantization function generate the second decoding in a second iteration.

[0143] Statement 11. An embodiment of the present disclosure includes an apparatus as recited in Statement 6, wherein, based at least on a comparison of the first decoding and the second decoding, the second low bit-width message is the first decoding.

[0144] Statement 12. An embodiment of the present disclosure includes an apparatus as recited in Statement 6, wherein, based at least on a comparison of the first decoding and the second decoding, the second high bit-width message is the first decoding.

[0145] Statement 13. An embodiment of the present disclosure includes an apparatus according to Statement 1, wherein:

[0146] Implementing the reconstruction function using a first lookup table; and

[0147] The quantization function is implemented using a second lookup table.

[0148] Statement 14. An embodiment of the present disclosure includes an apparatus according to Statement 13, wherein:

[0149] The storage device comprises the device and a memory; and

[0150] The memory includes the first lookup table and the second lookup table.

[0151] Statement 15. An embodiment of the present disclosure includes an apparatus according to Statement 1, wherein:

[0152] The reconstruction function is based on a density evolution technique; and

[0153] The quantization function is based on a density evolution technique.

[0154] Statement 16. An embodiment of the present disclosure includes an apparatus according to Statement 1, wherein:

[0155] The first low bit width message is a first 5-bit message;

[0156] The second low bit width message is a second 5-bit message;

[0157] The first high bit width message is a first 10-bit message; and

[0158] The second high bit width message is a second 10-bit message.

[0159] Statement 17. An embodiment of the present disclosure includes a method comprising:

[0160] receiving, at a device, a first low bit width message;

[0161] reconstructing a first high bit width message from said first low bit width message using a reconstruction function;

[0162] calculating a calculation function on the first high bit width message to generate a second high bit width message; and

[0163] quantizing the second high bit width message using a quantization function to produce a second low bit width message,

[0164] The reconstruction function and the quantization function vary according to at least one of an iteration and a layer of the device.

[0165] Statement 18. An embodiment of the present disclosure includes the method according to Statement 17, further comprising repeating the reconstruction, calculation and quantization operations for at least two layers in an iteration based at least in part on a comparison of a first decoding from a first layer and a second decoding from a second layer.

[0166] Statement 19. An embodiment of the present disclosure includes a method according to Statement 18, wherein the first decoding includes the first low bit width message and the second decoding includes the second low bit width message.

[0167] Statement 20. An embodiment of the present disclosure includes the method of Statement 18, wherein the first decoding includes the first high bit width message and the second decoding includes the second high bit width message.

[0168] Statement 21. An embodiment of the present disclosure includes the method of Statement 18, further comprising repeating the reconstruction, calculation, and quantization operations for at least two iterations based at least in part on a comparison of a first decoding from a first iteration and a second decoding from a second iteration.

[0169] Statement 22. An embodiment of the present disclosure includes a method according to Statement 21, wherein the first decoding includes the first low bit width message and the second decoding includes the second low bit width message.

[0170] Statement 23. An embodiment of the present disclosure includes a method according to Statement 21, wherein the first decoding includes the first high bit width message and the second decoding includes the second high bit width message.

[0171] Statement 24. An embodiment of the present disclosure includes the method according to Statement 17, further comprising:

[0172] At least one of the second low bit-width message or the second high bit-width message is output from the device.

[0173] Statement 25. Embodiments of the present disclosure include the method of Statement 17, wherein the device is part of a linear block code circuit.

[0174] Statement 26. Embodiments of the present disclosure include the method of Statement 25, wherein the linear block code circuit is part of a memory device.

[0175] Statement 27. Embodiments of the present disclosure include the method of Statement 26, wherein the storage device comprises a solid state drive (SSD).

[0176] Statement 28. Embodiments of the present disclosure include the method according to Statement 17, wherein:

[0177] Implementing the reconstruction function using a first lookup table; and

[0178] The quantization function is implemented using a second lookup table.

[0179] Statement 29. Embodiments of the present disclosure include the method according to Statement 17, wherein:

[0180] The reconstruction function is based on a density evolution technique; and

[0181] The quantization function is based on a density evolution technique.

[0182] Statement 30. Embodiments of the present disclosure include the method according to Statement 17, wherein:

[0183] The first low bit width message is a first 5-bit message;

[0184] The second low bit width message is a second 5-bit message;

[0185] The first high bit width message is a first 10-bit message; and

[0186] The second high bit width message is a second 10-bit message.

[0187] Statement 31. Embodiments of the present disclosure include an article of manufacture comprising a non-transitory storage medium having stored thereon instructions that, when executed by a machine, cause:

[0188] receiving, at a device, a first low bit width message;

[0189] reconstructing a first high bit width message from said first low bit width message using a reconstruction function;

[0190] calculating a calculation function on the first high bit width message to generate a second high bit width message; and

[0191] quantizing the second high bit width message using a quantization function to produce a second low bit width message,

[0192] The reconstruction function and the quantization function vary according to at least one of an iteration and a layer of the device.

[0193] Statement 32. An embodiment of the present disclosure includes an article according to Statement 31, wherein the non-temporary storage medium also stores instructions, which, when executed by a machine, cause: at least in part based on a comparison of a first decoding from the first layer and a second decoding from the second layer, repeating the reconstruction, calculation and quantization operations for at least two layers in an iteration.

[0194] Statement 33. An embodiment of the present disclosure includes an article of manufacture according to Statement 32, wherein the first decoding includes the first low bit-width message and the second decoding includes the second low bit-width message.

[0195] Statement 34. An embodiment of the present disclosure includes an article of manufacture according to Statement 32, wherein the first decoding includes the first high bit width message and the second decoding includes the second high bit width message.

[0196] Statement 35. An embodiment of the present disclosure includes an article according to Statement 32, wherein the non-transitory storage medium also has instructions stored thereon, which, when executed by a machine, cause: at least in part based on a comparison of a first decoding from a first iteration and a second decoding from a second iteration, repeating the reconstruction, calculation, and quantization operations for at least two iterations.

[0197] Statement 36. An embodiment of the present disclosure includes an article of manufacture according to Statement 35, wherein the first decoding includes the first low bit-width message and the second decoding includes the second low bit-width message.

[0198] Statement 37. An embodiment of the present disclosure includes an article of manufacture according to Statement 35, wherein the first decoding includes the first high bit width message and the second decoding includes the second high bit width message.

[0199] Statement 38. Embodiments of the present disclosure include an article of manufacture according to Statement 31, the non-transitory storage medium further having stored thereon instructions that, when executed by a machine, cause:

[0200] At least one of the second low bit-width message or the second high bit-width message is output from the device.

[0201] Statement 39. Embodiments of the present disclosure include an article of manufacture according to Statement 31, wherein the device is part of a linear block code circuit.

[0202] Statement 40. Embodiments of the present disclosure include the article of manufacture of Statement 39, wherein the linear block code circuit is part of a memory device.

[0203] Statement 41. Embodiments of the present disclosure include an article of manufacture according to Statement 40, wherein the storage device comprises a solid state drive (SSD).

[0204] Statement 42. Embodiments of the present disclosure include an article according to Statement 31, wherein:

[0205] Implementing the reconstruction function using a first lookup table; and

[0206] The quantization function is implemented using a second lookup table.

[0207] Statement 43. Embodiments of the present disclosure include an article according to Statement 31, wherein:

[0208] The reconstruction function is based on a density evolution technique; and

[0209] The quantization function is based on a density evolution technique.

[0210] Statement 44. Embodiments of the present disclosure include an article according to Statement 31, wherein:

[0211] The first low bit width message is a first 5-bit message;

[0212] The second low bit width message is a second 5-bit message;

[0213] The first high bit width message is a first 10-bit message; and

[0214] The second high bit width message is a second 10-bit message.

[0215] Therefore, in view of the various permutations of the embodiments described herein, this detailed description and the accompanying materials are intended to be illustrative only and should not be taken as limiting the scope of the present disclosure. Therefore, what is claimed as disclosed is all such modifications that may fall within the scope and spirit of the appended claims and their equivalents.

Claims

1. A device, include: an input buffer for receiving a first low bit width message; A reconstruction circuit, performing a reconstruction function on the first low bit width message to generate a first high bit width message; a calculation circuit that performs a calculation function on the first high bit width message to generate a second high bit width message; a quantization circuit that applies a quantization function to the second high bit width message to generate a second low bit width message; and a decision buffer for storing the second low bit width message, The reconstruction function and the quantization function vary according to at least one of an iteration and a layer of the device.

2. The device according to claim 1, in, The device is part of a linear block code circuit.

3. The device according to claim 1, in, The reconstruction circuit, the calculation circuit and the quantization circuit are used for at least two layers in an iteration.

4. The device according to claim 3, in: The reconstruction circuit implementing the reconstruction function, the calculation circuit, and the quantization circuit implementing the quantization function generate a first decoding; and The reconstruction circuit implementing a second reconstruction function, the calculation circuit, and the quantization circuit implementing a second quantization function generate a second decoding.

5. The device according to claim 4, in, Based at least on a comparison of the first decoding and the second decoding, the second low bit-width message is the first decoding.

6. The device according to claim 4, in, The reconstruction circuit implementing the reconstruction function, the calculation circuit, and the quantization circuit implementing the quantization function generate the first decoding in a first layer; and The reconstruction circuit implementing the second reconstruction function, the computation circuit, and the quantization circuit implementing the second quantization function generate the second decoding in a second layer.

7. The device according to claim 4, in, The reconstruction circuit implementing the reconstruction function, the calculation circuit, and the quantization circuit implementing the quantization function generate the first decoding in a first iteration; and The reconstruction circuit implementing the second reconstruction function, the computation circuit, and the quantization circuit implementing the second quantization function generate the second decoding in a second iteration.

8. The device according to claim 1, in: Implementing the reconstruction function using a first lookup table; and The quantization function is implemented using a second lookup table.

9. The device according to claim 8, in: The storage device comprises the device and a memory; and The memory includes the first lookup table and the second lookup table.

10. The device according to claim 1, in: The reconstruction function is based on a density evolution technique; and The quantization function is based on a density evolution technique.

11. A method, include: receiving, at a device, a first low bit width message; reconstructing a first high bit width message from said first low bit width message using a reconstruction function; calculating a calculation function on the first high bit width message to generate a second high bit width message; as well as quantizing the second high bit width message using a quantization function to produce a second low bit width message, The reconstruction function and the quantization function vary according to at least one of an iteration and a layer of the device.

12. The method of claim 11, further comprising repeating the reconstruction, calculation, and quantization operations for at least two layers in an iteration based at least in part on a comparison of a first decoding from a first layer and a second decoding from a second layer.

13. The method according to claim 12, in, The first decoding includes the first low bit width message, and the second decoding includes the second low bit width message.

14. The method of claim 12, further comprising repeating the reconstruction, calculation, and quantization operations for at least two iterations based at least in part on a comparison of a first decoding from a first iteration and a second decoding from a second iteration.

15. The method according to claim 14, in, The first decoding includes the first low bit width message, and the second decoding includes the second low bit width message.

16. The method according to claim 11, further comprising: include: At least one of the second low bit-width message or the second high bit-width message is output from the device.

17. The method according to claim 11, in: Implementing the reconstruction function using a first lookup table; and The quantization function is implemented using a second lookup table.

18. The method according to claim 11, in: The reconstruction function is based on a density evolution technique; and The quantization function is based on a density evolution technique.

19. An article of manufacture comprising a non-transitory storage medium having stored thereon instructions which, when executed by a machine, cause: receiving, at a device, a first low bit width message; reconstructing a first high bit width message from said first low bit width message using a reconstruction function; calculating a calculation function on the first high bit width message to generate a second high bit width message; as well as quantizing the second high bit width message using a quantization function to produce a second low bit width message, The reconstruction function and the quantization function vary according to at least one of an iteration and a layer of the device.

20. The article according to claim 19, in: The reconstruction function is based on a density evolution technique; and The quantization function is based on a density evolution technique.

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