Extended effective TLP fragmentation in LBA environments

Abstract

This disclosure relates entirely to effective transport layer packet (TLP) fragmentation in a data storage device. For an unaligned read from a host stream, a sufficient amount of data to be aligned is transferred from the host to the storage device, while the remainder of the data is stored in a cache on the data storage device for later delivery to the storage device. For an unaligned write to a host stream, the unaligned data is written to the cache, and the cache is later flushed to the host device. In both cases, although the total data will be unaligned, a portion of the data is placed in the cache, aligning the data not placed in the cache. The data in the cache is delivered at a later point in time.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 083,647, filed September 25, 2020, which is incorporated herein by reference. Background Technology Technical Field

[0004] The implementation scheme disclosed herein relates to effective transport layer packet (TLP) fragmentation in data storage devices.

[0005] Description of related fields

[0006] Metadata is additional data allocated based on each logical block. There are no requirements on how host devices use metadata areas. One of the most common uses of metadata is to deliver end-to-end protection information.

[0007] Metadata can be transmitted between the controller and the host device in one of two ways. The mechanism used is selected when the namespace is formatted. One mechanism for transmitting metadata is as a contiguous section of a logical block associated with the metadata. The metadata is transmitted at the end of the associated logical block, thus forming an extended logical block, such as... Figure 1 As shown.

[0008] Extended Logical Block Address (LBA) format presents significant challenges in supporting out-of-order data transmission. Figure 2 The problem is illustrated in a simple example. In this example, the memory page size represents the size of each buffer in the host device's DRAM and is set to 4KB. The LBA size is also set to 4KB, while the metadata size is 16 bytes. The host device sends read / write commands, and the total transfer size is three LBAs, meaning the following should be transferred on the PCIe bus: LBA A, metadata A, LBA B, metadata B, LBA C, and metadata C. Figure 2 As shown, this command requires four host device buffers. The first buffer holds LBA A. The second buffer holds metadata A plus the first part of LBA B. The third buffer holds the tail of LBA B, metadata B, and the first part of LBA C. The last buffer holds the tail of LBA C and metadata C.

[0009] In out-of-order data transfer, the data storage device may need to transfer LBA B and metadata B first. In this case, unoptimized packets will be sent via the PCIe bus for unaligned transmission. Later, the data storage device may need to transfer LBA A and metadata A. Similarly, the data storage device will send unoptimized packets to transfer metadata only from the second buffer.

[0010] Therefore, there is a need in this field for transport layer packet (TLP) fragmentation optimization. Summary of the Invention

[0011] This disclosure relates entirely to effective transport layer packet (TLP) fragmentation in a data storage device. For an unaligned read from a host stream, a sufficient amount of data to be aligned is transferred from the host to the storage device, while the remainder of the data is stored in a cache on the data storage device for later delivery to the storage device. For an unaligned write to a host stream, the unaligned data is written to the cache, and the cache is later flushed to the host device. In both cases, although the total data will be unaligned, a portion of the data is placed in the cache, aligning the data not placed in the cache. The data in the cache is delivered at a later point in time.

[0012] In one embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive a read request from a host; determine that the read request from the host exceeds a maximum payload size (MPS); align the address and size of the request with the MPS to create an aligned request; allocate cache buffer storage space for the read request from the host; send the aligned request to the host device; receive return data of the MPS exceeding the aligned request; and store the return data in the allocated cache.

[0013] In another embodiment, a data storage device includes: one or more memory devices; an interface module; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive a host request through the interface module; determine that the host request is misaligned; and retrieve data from a cache.

[0014] In another embodiment, a data storage device includes: one or more memory devices; an interface means for determining an unaligned access request from a host device; and a controller coupled to the one or more memory devices. Attached Figure Description

[0015] Therefore, a detailed understanding of the foregoing features of this disclosure, a more specific description of this disclosure, and the foregoing brief overview can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should therefore not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.

[0016] Figure 1This is a schematic diagram of Extended Logical Block Address (LBA).

[0017] Figure 2 This is a schematic diagram of a data buffer example.

[0018] Figure 3 This is a schematic diagram of a storage system based on an implementation plan.

[0019] Figure 4 This is a flowchart illustrating a method for processing write commands according to one implementation scheme.

[0020] Figure 5 This is a flowchart illustrating a method for processing read commands according to one implementation scheme.

[0021] Figure 6A and 6B This is a flowchart illustrating a method for cache refresh according to several implementation schemes.

[0022] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0023] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, consider any combination of the following features and elements (whether or not related to different embodiments) to achieve and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, achieving a particular advantage through a given embodiment is not a limitation of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are illustrative only and should not be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0024] This disclosure relates entirely to effective transport layer packet (TLP) fragmentation in a data storage device. For an unaligned read from a host stream, a sufficient amount of data to be aligned is transferred from the host to the storage device, while the remainder of the data is stored in a cache on the data storage device for later delivery to the storage device. For an unaligned write to a host stream, the unaligned data is written to the cache, and the cache is later flushed to the host device. In both cases, although the total data will be unaligned, a portion of the data is placed in the cache, aligning the data not placed in the cache. The data in the cache is delivered at a later point in time.

[0025] Figure 1 This is a diagram illustrating Extended Logical Block Addresses (LBAs). Metadata is additional data allocated based on each logical block, where metadata can be information about associated user data. For example, metadata can convey end-to-end protection information for associated user data. In one example, metadata may be transmitted between the data storage device's controller and the host device as part of a contiguous portion of a logical block. Metadata may be transmitted at the end of an associated logical block, where the logical block and associated metadata form an extended logical block.

[0026] An extended LBA includes a first data buffer comprising a first Physical Region Page (PRP) PRP1 and a second PRP PRP2. Each LBA in the extended LBA includes associated metadata. For example, the metadata of a first LBA n is associated with the data of a first LBA n data, and the metadata of a second LBA n+1 is associated with the data of a second LBA n+1 data. It should be understood that an extended LBA can have any suitable number of LBA data and LBA metadata pairs, and the numbers shown are not intended to be limiting but are provided as examples of possible implementations.

[0027] Figure 2 This is a schematic diagram of a data buffer example. Figure 1 Its various aspects can be similar to Figure 2 Example of a data buffer. When an extended LBA is transferred to the host, each LBA data size can be approximately 4KB, and each LBA metadata size can be approximately 16 bytes. Furthermore, the extended LBA can be stored in one or more buffers before being transferred to the host device via the data bus. In one example, each of the one or more buffers has a size of approximately 4KB. For example, each buffer in a PCIe architecture can have a maximum payload size (MPS), where MPS represents the size of each buffer. It should be understood that while a PCIe architecture is illustrated, other architectures are also relevant, and the implementation described herein is applicable to other architectures.

[0028] When the host device sends a read / write command and the total transfer size is 3 LBAs, the 3 LBAs and their associated LBA metadata form an extended LBA. Due to the buffer MPS, four buffers 202a, 202b, 202c, and 202d are required to transfer the 3 LBAs and their associated LBA metadata. The 3 LBAs include first user data 204a, second user data 204b, 204ba, and third user data 204c, 204ca. The first buffer 202a includes the first user data 204a. For illustrative purposes, the term "user data" may refer interchangeably to LBA data, such as... Figure 1 The first LBA n data. The second buffer 202b includes first metadata 206a associated with the first user data 204a and a first portion of the second user data 204b. Because the second buffer 202b has a size of approximately 4KB and the associated metadata is written sequentially to one or more buffers, the second user data cannot be completely stored in the second buffer 202b.

[0029] Therefore, the second portion of the second user data 204ba is stored in the third buffer 202c. The second metadata 206b is stored sequentially after the second portion of the second user data 204ba. Similarly, since the third buffer 202c has a size of approximately 4KB, the first portion of the third user data 204c is stored in the third buffer 202c, and the second portion of the third user data 204ca is stored in the fourth buffer 202d. The third metadata 206c is stored sequentially in the fourth buffer 202d after the second portion of the third user data 204ca.

[0030] When data is transferred sequentially from the first data to the last data, the transfer to and from the host device can be seamless. However, during out-of-order data transfer, the data storage device may need to transfer the second user data 204b, 204ba and the second metadata 206b instead of the first user data 204a and the first metadata 206a. When data is transferred out of order, unoptimized data packets associated with the unaligned transfer are issued via the PCIe bus. Furthermore, when the first user data 204a and the first metadata 206a are transferred, the data storage device issues an unoptimized data packet for transferring the first metadata 206a from the second buffer 202b, without the first portion of the second user data 204b.

[0031] Figure 3This is a schematic diagram of a storage system 300 according to one embodiment. Storage system 300 includes a host device 302 that interacts with a device controller 304 of a data storage device. For example, host device 302 may use NAND 326, or in some embodiments, non-volatile memory included in the data storage device, to store and retrieve data. In some examples, storage system 300 may include multiple data storage devices that can operate as a storage array. For example, storage system 300 may include multiple data storage devices configured to collectively serve as a low-cost / independent disk (RAID) redundant array of high-capacity storage devices for host device 302.

[0032] Device controller 304 includes a host interface module (HIM) 306, a data path 312, an error correction code (ECC) module 314, one or more processors 318, a flash interface module (FIM) 316, and a dynamic random access memory (RAM) controller 320. The dynamic RAM (DRAM) controller 320 interacts with DRAM 322, which includes a user data cache buffer 324 for each command. In this description, for illustrative purposes, the user data cache buffer 324 for each command may be referred to as cache buffer 324.

[0033] In some implementations, the DRAM controller 320 may be a static RAM (SRAM) controller that interacts with the SRAM. The FIM 316 may be configured to schedule the storage and retrieval of data from locations within the NAND 326. The one or more processors may be configured to generate and execute system commands to store, access, and operate on data in the NAND 326. The ECC module 314 may generate ECC data for user data stored in the NAND 326, where the ECC data may be part of metadata associated with the user data.

[0034] When host device 302 sends a read / write command to device controller 304, HIM 306 receives the read / write command. HIM 306 includes PCIe 308 and NVMe 310. PCIe 308 and NVMe 310 can be configured to operate according to their respective protocols. For example, each buffer (such as...) Figure 2The sizes of buffers 202a, 202b, 202c, and 202d are configured by host device 203 during the initialization phase. In some implementations, the buffer sizes are approximately 4KB, 8KB, 16KB, 32KB, etc. It should be understood that the listed sizes are not intended to be limiting, but rather to provide examples of possible implementations. Data transfer is considered aligned when the data transfer size satisfies the formula N*MPS (where N is an integer value) and the address of the first buffer is aligned to MPS (e.g., PCIe address % MPS = 0). Data transfer is considered unaligned when the data transfer does not satisfy the formula N*MPS or the address of the first buffer is not aligned to MPS. Neither of these conditions is met when metadata is present. Although the metadata is small (e.g., 16 bytes), the metadata can cause unalignment.

[0035] Aligned transfers bypass the cache (i.e., the buffer) and can interact directly with host device 302 according to the previously described method. More specifically, data is sensed by NAND, and the readiness status of the data may not be sequential. Considering the example above, LBA B may be ready first. In this case, LBA B, along with metadata B, should be transferred first. For that particular block, the data storage device determines aligned and unaligned blocks based on PCIe MPS parameters. Blocks fully aligned with the PCIe MPS bypass the cache, while unaligned blocks interact with the cache. In other words, data transfer bypasses the cache when the size of an aligned transfer is equal to the MPS of the PCIe parameters configured by host device 203 during the initialization phase. However, unaligned transfers are classified as cacheable data. Unaligned transfers are transferred to DRAM controller 320, where the DRAM controller stores the unaligned transfers in cache buffer 324 of DRAM 322. For each incomplete command, the allocated buffer storage space of cache buffer 324 is allocated to the incomplete command.

[0036] To better understand how data storage devices handle aligned and unaligned transfers, consider the following example for a system with the following parameters: memory page size of 4KB, LBA size of 4LB, metadata size of 16 bytes, and PCIe MPS of 512 bytes. For host commands, the host provides a host write command (PCIe read stream). The command size is 3 LBAs. The first buffer is 4KB in size, the second buffer is 4KB in size, the third buffer is 4KB in size, and the fourth buffer is 4KB in size, but only 48 bytes are valid. The total transfer size for the 3 LBAs will be 3 x (LBA size + metadata size) = 12KB + 48 bytes. When the data storage device decides to transfer the second LBA first, the second buffer will be the first buffer needed. Therefore, due to the 4KB size of the second buffer minus the 16 bytes reserved for the metadata of the first LBA, the second buffer will have 4KB - 16 bytes of availability. Therefore, in order to transmit the second LBA, a next buffer (i.e., the third buffer) is also needed to store the tail of the second LBA (i.e., 16 bytes) and the second LBA metadata (i.e., 16 bytes). In other words, the next buffer (i.e., the third buffer) requires 16 bytes for the second LBA.

[0037] Defining which buffers are aligned with the PCIe MPS can occur while continuing with the example above of nine buffers used for transmission. The first buffer is 512-16 bytes (496 bytes) in size. The second through eighth buffers are 512 bytes in size. The ninth buffer is 32 bytes in size. Therefore, the first and ninth buffers are not aligned, while the second through eighth buffers are aligned. Thus, the first and ninth buffers interact with the cache, and will be stored in the cache. Therefore, the data storage device will be aligned as follows: the first aligned buffer will be the second buffer with 512 bytes, and the third buffer with 512 bytes will be the last aligned buffer. The required data is used by the controller, while additional data is stored in two cache buffers and will be used as needed. These two cache buffers will be needed when transmitting the first and third LBAs, as cache hits will occur in those scenarios.

[0038] During a PCIe read stream, the logical block address and requested size are aligned to the MPS. A transfer aligned to the MPS is sent from device controller 304 to host device 302. When the returned data exceeds the MPS of the alignment request, the returned data (i.e., the extended LBA) is stored in the allocated cache buffer space of cache buffer 324 of DRAM 322. The request data for the read command is returned to host device 302, while the remaining data is stored in the allocated cache buffer space of cache buffer 324. When another read command for the remaining data is received, the remaining data is returned directly from the allocated cache buffer space of cache buffer 324 to host device 302. However, during a PCIe write stream, unaligned data is written to cache buffer 324. When the remaining data associated with the unaligned data is written to cache buffer 324, cache buffer 324 is flushed to host device 302.

[0039] Figure 4 This is a flowchart illustrating a method 400 for processing write commands according to one implementation scheme. Figure 3 The storage system 300 may be similar in various aspects to the implementation described herein. At block 402, the device controller (such as...) Figure 3 The device controller 304 receives data from the internal host (such as...). Figure 3 The host device (302) reads a request (i.e., a data storage device write command). The maximum size of the read request is equal to the value of the Maximum Read Request Size (MRRS) PCIe parameter. At box 404, the controller determines whether the read requested from the host is a cache hit. A cache hit means that the data stored in the cache (such as...) Figure 3 The data from the previous read request is stored in the cache buffer 324. If a cache hit occurs at box 404, the data is read from the cache at box 406.

[0040] However, if no cache hit occurs at box 404, then at box 408, the controller determines whether the read requested from the host has cache line granularity. Cache line granularity refers to whether the read is aligned with or not with the MPS. If the read has cache line granularity at box 408, then at box 410, the read is determined to be a non-cacheable request, and the data associated with the read request is directly transferred to the host device if the cache is bypassed.

[0041] If the read request from the host at box 408 does not have cache line granularity, then at box 412, the controller requests alignment with the cache line when considering the attributes of the write command. First, the request address and size are aligned with the MPS by expanding the request while maintaining the write command boundaries. At box 414, a cache buffer is allocated. At box 416, the aligned request is transmitted to the host device. At box 418, the returned data is stored in the cache buffer, while the relevant data is transmitted to the host device at box 420. When the device controller receives a request to read another portion of the cache line, the remaining data stored in the cache buffer can be transmitted later. When a request to read another portion of the cache line is received, the controller determines a cache hit at box 404 and reads the relevant data from the cache buffer.

[0042] Figure 5 This is a flowchart illustrating a method 500 for processing a read command according to one implementation scheme. Figure 3 The storage system 300 may be similar in various aspects to the implementation described herein. At block 502, the device controller (such as...) Figure 3 The device controller 304 receives data from the internal host (such as...). Figure 3 The host device 302) writes a request (i.e., a data storage device read command). The maximum size of the write request is equal to the value of the MPS PCIe parameter. At box 504, the controller determines whether a cache hit exists, where a cache hit means determining whether the data associated with the write request is stored in a cache buffer (such as...). Figure 3 In the cache buffer (324).

[0043] If a cache hit occurs at box 504, data is written to the cache at box 506, where writing data to the cache means reading the relevant data from the cache to the host device. However, if no cache hit occurs at box 504, the controller determines at box 508 whether the write request has cache line granularity. If the write request has cache line granularity at box 508, the controller determines at box 510 that the write request is a non-cacheable request, and the write request interacts directly with the host. However, if the write request does not have cache line granularity at box 508, a cache buffer is allocated at box 512. When the write request does not have cache line granularity, the host request is considered unaligned. At box 514, the data of the write request is written to the cache buffer. When the cache buffer is fully filled or the read command completes, the data in the cache buffer is flushed to the host device.

[0044] Figure 6A and 6BThis is a flowchart illustrating cache refresh methods 600 and 650 according to several implementations. Cache refresh method 600 begins at block 602, where the controller receives a request to the host device to complete an entry, such as when... Figure 4 Write command or Figure 5 When the read command completes, at box 604, the device controller flushes the relevant cache buffer with the completion command, and at box 606, releases the cache buffer to a cache buffer pool that can be allocated to store cached data. At box 608, the device controller publishes a completion entry to the host device. At box 610, the device controller asserts an interrupt to the host upon enablement.

[0045] Method 650 for cache flushing can be an optional method of cache flushing. At box 652, the data storage device has fully accessed a specific cache buffer, instead of flushing all cache buffers associated with the command at box 604. At box 654, the device controller flushes the cache entry buffer associated with a specific cache line. At box 656, the cache buffer is released. Unlike method 600, where the entire cache buffer is flushed and released, method 650 can optionally flush and release specific cache buffers. After completing the steps at box 656, method 650 can return to method 600 at box 608.

[0046] By storing data in a cache buffer for unaligned host requests, and delivering optimized packets only via the PCIe bus, the overall performance of the data storage device is improved.

[0047] In one embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive a read request from a host; determine that the read request from the host exceeds a maximum payload size (MPS); align the address and size of the request with the MPS to create an aligned request; allocate cache buffer storage space for the read request from the host; send the aligned request to the host device; receive return data of the MPS exceeding the aligned request; and store the return data in the allocated cache. The controller is further configured to deliver the return data from the allocated cache storage space to the one or more memory devices. The controller is further configured to request the return data from the allocated cache buffer storage space. The return data is delivered to the one or more memory devices in response to the request. The controller is further configured to determine whether the read request from the host is a cache hit. The controller is further configured to read data from the allocated cache when the read request from the host is a cache hit. The controller is further configured to determine whether the read request from the host is at the cache line granularity. The controller is further configured to, when it is determined that the read request from the host is at the cache line granularity, process the read request from the host without using the cache buffer for storage.

[0048] In another embodiment, a data storage device includes: one or more memory devices; an interface module; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive a host request through the interface module; determine that the host request is unaligned; and retrieve data from a cache. The host request is a write operation to the host request. The controller is further configured to determine whether the host request is a cache hit. The controller is further configured to write data to the cache in response to determining that the host request is a cache hit. The controller is further configured to determine whether a cache line granularity exists in the host request. The controller is further configured to interact directly with the host when a cache line granularity is determined to exist. The controller is further configured to allocate cache buffer storage and write data to the allocated cache buffer storage. The controller also includes a random access memory (RAM) controller coupled to the interface module. The data storage device also includes a RAM device coupled to the RAM controller, wherein the cache is located in the RAM device.

[0049] In another embodiment, a data storage device includes: one or more memory devices; interface means for determining an unaligned access request from a host device; and a controller coupled to the one or more memory devices. The data storage device further includes: means for receiving a request to publish a completion entry to the host device; and means for flushing all cache buffers associated with the command and publishing the completion entry to the host device. The data storage device also includes: means for releasing the associated cache buffers; and means for publishing the completion entry to the host device.

[0050] While the foregoing describes embodiments of this disclosure, other and additional embodiments of this disclosure may be contemplated without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: One or more memory devices; and A controller, coupled to the one or more memory devices, wherein the controller is configured to: Receive read requests from the host; It was determined that the read request from the host exceeded the maximum payload size (MPS). Align the address and size of the request with the MPS to create an aligned request; Allocate cache buffer storage space for the read request from the host; Send the alignment request to the host device; Receive return data associated with the alignment request from the host device, wherein the return data extends beyond the MPS and wherein the return data is continuous; as well as The returned data is stored in the allocated cache buffer storage space.

2. The data storage device of claim 1, wherein the controller is further configured to deliver the returned data from the allocated cache storage space to the one or more memory devices.

3. The data storage device of claim 2, wherein the controller is further configured to request the returned data from the allocated cache buffer storage space.

4. The data storage device of claim 3, wherein the returned data is delivered to the one or more memory devices in response to the request.

5. The data storage device of claim 1, wherein the controller is further configured to determine whether the read requested from the host is a cache hit.

6. The data storage device of claim 5, wherein the controller is further configured to read data from the allocated cache when the read requested from the host is a cache hit.

7. The data storage device of claim 1, wherein the controller is further configured to determine whether the read requested from the host is at the cache line granularity.

8. The data storage device of claim 7, wherein the controller is further configured to process the read requested from the host without using the cache buffer storage when it is determined that the read requested from the host is at the cache line granularity.

9. A data storage device, the data storage device comprising: One or more memory devices; Interface module; and A controller, coupled to the one or more memory devices, wherein the controller is configured to: Receive host requests through the interface module; It is determined that the host request is misaligned, wherein the host request is larger than the maximum payload size (MPS); and Data is retrieved from a cache, wherein the data stored in the cache is associated with a previously unaligned host request greater than the MPS, and wherein the data associated with the previously unaligned host request is contiguous.

10. The data storage device according to claim 9, wherein the host request is a write to a host request.

11. The data storage device of claim 9, wherein the controller is further configured to determine whether the host request is a cache hit.

12. The data storage device of claim 11, wherein the controller is further configured to write data to the cache in response to determining that the host request is a cache hit.

13. The data storage device of claim 9, wherein the controller is further configured to determine whether cache line granularity exists in the host request.

14. The data storage device of claim 13, wherein the controller is further configured to interact directly with the host when it is determined that cache line granularity exists.

15. The data storage device of claim 9, wherein the controller is further configured to allocate cache buffer storage and write data to the allocated cache buffer storage.

16. The data storage device of claim 9, wherein the controller further comprises a random access memory (RAM) controller coupled to the interface module.

17. The data storage device of claim 16, further comprising a RAM device coupled to a RAM controller, wherein the cache is located in the RAM device.

18. A data storage device, the data storage device comprising: One or more memory devices; and A controller, coupled to the one or more memory devices, wherein the controller is configured to: The request from the host device is determined to be an unaligned access request, wherein the unaligned access request is greater than the maximum payload size (MPS). The request is associated with the unaligned access request, wherein the address and size of the requested data are aligned with the MPS; Receive requested data from the host device or the one or more memory devices, wherein the received requested data is greater than the MPS, and wherein the received requested data is continuous; as well as The received requested data is stored in a cache buffer allocated for data larger than the MPS.

19. The data storage device of claim 18, wherein the controller is further configured to: Receive a request to publish the completed entry to the host device; and Refresh all cache buffers associated with the command and publish the completion entry to the host device.

20. The data storage device of claim 18, wherein the controller is further configured to: Release the relevant cache buffers; and The completed entry will be published to the host device.

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