An automatic mapping method based on topology structure dynamic analysis

Abstract

This invention provides an automatic mapping method based on dynamic topology analysis, comprising the following steps: obtaining the logical connection relationship of display devices from a database; dynamically calibrating the display area using four-point coordinates according to the actual screen size; dividing the display area into row and column grids by automatically searching the hierarchy of the topology connection relationship and the type and quantity of devices contained in each level; automatically generating a corresponding graphic based on the topology connection relationship; setting the center coordinate of each switch as the center coordinate position of the unit grid by the division of the display area and the number of switches in the LL layer of the corresponding station area, thus determining the one-to-one correspondence between the coordinates of all switches in the LL layer and the center coordinates of the grid; automatically deducing the coordinates of the upper and lower levels corresponding to the coordinates of each switch in the LL layer based on the determined coordinates of each switch in the LL layer and the upper and lower level correlations in the station area; and displaying the topology line based on four-point coordinate positioning.

Description

Technical Field

[0001] This invention relates to the technical field of power grid system data processing, and in particular to an automatic mapping method based on dynamic topology analysis. Background Technology

[0002] Traditionally, equipment information and topology connections in distribution substations are mostly stored in paper form. Due to insufficient automation, electronic information maintenance is lacking. Over time, this can lead to discrepancies between the actual field connections and the existing stored data, causing interference with system maintenance.

[0003] With the continuous improvement of the level of the power Internet of Things, the scale of intelligent transformation of distribution substations is expanding day by day. There is an urgent need for and the ability to realize topology search, dynamic coloring and automatic mapping functions on the visualization master station system. This will change the fact that the topology diagram of low-voltage distribution substations is mainly stored in paper documents, and avoid the defects of untimely equipment information maintenance and inconsistent and unintuitive display.

[0004] Patent application CN111292391A discloses an automatic low-voltage distribution area map generation device and method. The device includes a data loading component, a distribution area map layout and wiring component, and a distribution area map storage component. The data loading component is connected to a power grid GIS platform and is used to load low-voltage distribution area map data from the power grid GIS platform and generate an intermediate memory data structure. The distribution area map layout and wiring component, based on the intermediate memory data structure, creates the distribution area map organization structure and all line equipment entity objects in the distribution area map, and establishes association relationships with the distribution area map and internal wiring diagram source objects in the low-voltage distribution area map data to generate the low-voltage distribution area map. The drawback of this method is that it cannot display changes in real-time, does not reflect actual operating conditions, and has low scalability for real-time display of multi-dimensional information. Summary of the Invention

[0005] To address the aforementioned technical issues, this invention proposes an automatic mapping method based on dynamic topology analysis. Using a device logical connection model as a carrier, it acquires the logical connection relationships of the display devices, automatically deduces the boundaries of the map display area, and achieves virtual meshing of the display area based on topology hierarchical analysis. It supports a one-to-one mapping between the center coordinates of various display devices and the center coordinates of the virtual mesh. Based on this, it automatically deduces the positioning coordinates of the line connections between the upper and lower levels of the device. A dynamic topology coloring algorithm is used to achieve linked display of devices and lines, and it also supports manual adjustment of the formed topology connection diagram.

[0006] The purpose of this invention is to provide an automatic mapping method based on dynamic topology analysis, which includes obtaining the logical connection relationships of display devices from a database, and further includes the following steps:

[0007] Step 1: Dynamically define the display area using four coordinates based on the actual screen size;

[0008] Step 2: By automatically searching the hierarchy of topological connections and the types and quantities of devices contained in each level, the display area is divided into rows and columns, and a topological connection graph is generated through automatic calculation.

[0009] Step 3: By dividing the display area and the number of switches in the LL layer of the corresponding station area, the center coordinate of each switch is set as the center coordinate position of the unit grid. Then, the coordinates of all switches in the LL layer are determined one-to-one with the center coordinates of the grid. The LL layer is the layer with the most devices.

[0010] Step 4: Based on the determined coordinates of each switch in the LL layer and its hierarchical relationship within the station area, automatically deduce the coordinates of the upper and lower levels corresponding to the coordinates of each switch in the LL layer.

[0011] Step 5: Display the topology based on four-point coordinate positioning.

[0012] Preferably, step 1 includes automatically calculating and allocating the display area adaptively based on the actual size of the screen.

[0013] In any of the above schemes, it is preferred that the actual content frame displayed in the display area is determined by points P1, P2, P3 and P4, where P1 = [K1, K2], P2 = [K3, K2], P3 = [K1, K4], P4 = [K3, K4], K1, K2, K3 and K4 are constants, and K1 and K3 are less than the width Pixel1 of the screen resolution, and K2 and K4 are less than the height Pixel2 of the screen resolution.

[0014] In any of the above schemes, step 2 preferably includes displaying the content of the single-unit area topology within the effective area. The size of the grid allocated to the single-unit area depends on the number of switches in the corresponding layer of the topology level of the single-unit area, and the topology layer with the largest topology level is divided into grids.

[0015] In any of the above schemes, it is preferred that the grid division method includes a row grid determination method and a column grid determination method.

[0016] In any of the above schemes, it is preferred that the row grid determination method is to set the number of layers of the single unit area to L layers, and the pixel value occupied by the number of rows of the row grid is int[(K4-K2) / L].

[0017] In any of the above schemes, it is preferred that the column grid determination method is to set the number of switches of the layer corresponding to the single unit area as the total number of switches of the LL layer, and the corresponding switch value is: Q = sum(LL), that is, the total number of switches of the LL layer is Q, and the number of grid pixels occupied by a single column pixel is int[(K3-K1) / Q].

[0018] In any of the above schemes, it is preferred that the automatic deduction method includes at least one of the following: special coordinate processing method, coordinate deduction method of LL layer, coordinate deduction method of the layer above LL layer, coordinate deduction method of the layer below LL layer, and supplementary method of interconnection switch for different transformer areas.

[0019] In any of the above schemes, it is preferred that the special coordinate processing method includes marking the coordinates of the unique switch of the first layer at the center of the network area, with coordinates [(K3-K1) / 2, K2].

[0020] In any of the above schemes, the preferred method for coordinate derivation of the LL layer includes, for the connections within a single area, placing the connections' switches in adjacent positions by pre-binding relationships with relevant connections' switches in the database, including the following sub-steps:

[0021] Step 401: Align the other switches in the collection unit, including the tie switch, with the tie switch as the left and right starting point respectively.

[0022] Step 402: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right.

[0023] Step 403: By using the one-to-one mapping relationship between the switch coordinates of LL and the grid center, deduce from bottom to top to determine the coordinates of the previous parent node of LL;

[0024] Step 404: Calculate the coordinates of all associated parent nodes of the LL layer through iterative calculation;

[0025] Step 405: Using the results of the topology calculation of LL, deduce from top to bottom to determine the coordinates of the next layer of LL;

[0026] Step 406: Calculate the coordinates of all associated child nodes of the next level in the LL layer through iterative calculation.

[0027] In any of the above schemes, preferably, step 403 includes setting the coordinates of the parent node switch of the upper layer of the LL layer to (X, Y), the column coordinates of the parent node switch to Y = Y_LL - int[(K4-K2) / L], and the row coordinates of the parent node switch to X = (X_LL_max - X_LL_min) / 2. Then the coordinates of the parent node are calibrated as: ((X_LL_max - X_LL_min) / 2, Y_LL - (int[(K4-K2) / L]), where X_LL is the row coordinate of the switch to be calculated in the LL layer, Y_LL is the column coordinate of the switch to be calculated in the LL layer, X_LL_max is the row coordinate of the rightmost switch on the same output line in the LL layer, and X_LL_min is the row coordinate of the leftmost switch on the same output line in the LL layer.

[0028] In any of the above schemes, preferably, step 405 includes setting the number of outgoing switches in the next layer of a certain node in layer LL to be W, with the coordinates sequentially being (X1, Y1), ..., (X... w Y w The column coordinate of the switch is Y. w =Y_LL+int[(K4-K2) / L]; When W is odd, the row coordinate of the switch is X. i =X_LL-((W-2*(i-1)-1) / 2)*(K3-K1) / Q, where W is even and i < W / 2, X i =X_LL-((W-2*(i-1)) / 2)*(K3-K1) / Q, when W is even and i≥W / 2, X i =X_LL-((W-2*(i-1)) / 2-1)*(K3-K1) / Q; where 1≤i≤W.

[0029] In any of the above schemes, it is preferred that the coordinate derivation method of the layer above the LL layer includes special processing of the communication switch of the layer above the LL layer, and the corresponding communication switch is found by searching the communication relationship table in the communication switch database.

[0030] In any of the above schemes, the coordinate derivation method of the layer above the LL layer further includes placing the switches of the connections within a single area in adjacent positions, including the following sub-steps:

[0031] Step 411: Place the connecting switch in an adjacent position, and mark the other switches with the connecting switch as the left and right starting points respectively to generate two aggregation units.

[0032] Step 412: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right.

[0033] In any of the above schemes, step 411 preferably includes sorting. When the switch coordinates of the collection unit with the connecting switch are derived from the switch coordinates of the LL child node, the sorting will be arranged in the corresponding order around the coordinates. The connecting switches are the left and right starting points of the two collection units respectively.

[0034] In any of the above schemes, the preferred method for coordinate derivation of the next layer below the LL layer includes finding the corresponding communication switch by searching the database communication switch relationship table, and placing the communication switches in adjacent positions for communication within a single area, including the following sub-steps:

[0035] Step 421: Place the connecting switch in an adjacent position, and mark the other switches with the connecting switch as the left and right starting points respectively to generate two aggregation units.

[0036] Step 422: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right.

[0037] In any of the above schemes, preferably, step 421 further includes sorting. When the switch coordinates of the aggregation unit with the connecting switch are derived from the switch coordinates of the LL child node, the sorting will be arranged in the corresponding order around the coordinates. The connecting switches are the left and right starting points of the two aggregation units respectively.

[0038] In any of the above schemes, the preferred method is that the automatic deduction method further includes calculating the switching coordinates of the entire station area by continuously deducing the logic of the layer above and the layer below the LL layer through recursive relationships.

[0039] In any of the above schemes, the preferred method for supplementing the interconnection switches in different transformer areas includes, when displaying a single transformer area, identifying the interconnection switch as a special type of switch in the database. This mainly includes the hierarchical information of the interconnection switch, and the specific coordinates will be adjusted according to the coordinates of the hierarchical level. The bus tie switch is placed in the rightmost cell of the grid and marked with the interconnection switch marker color.

[0040] In any of the above schemes, step 5 includes determining the coordinates of the switch nodes within the single-area display mode, and solidifying the operating lines of the parent and child nodes one by one through coordinates based on the relationship between the upper and lower levels.

[0041] In any of the above schemes, preferably, the solidification method includes setting the parent node and child node switches to 1 input and M outputs, with the parent node A having coordinates (X, Y) and the child nodes having coordinates [(X1, Y1), (X2, Y2), ..., (X...]. M Y M The lines of parent and child nodes are uniformly formatted using four-point coordinates.

[0042] In any of the above schemes, it is preferable that, when M is an odd number, all lines of the parent node switch and the child node switch are determined one by one as follows:

[0043] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-1) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-1) / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0044] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-3) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-3) / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0045] ……,

[0046] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-2i-1) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-2i-1) / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0047] ……,

[0048] {[X, Y], [X, Y+(K4-K2) / 2L], [X+M-1)) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X+(M-1) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}.

[0049] In any of the above schemes, it is preferable that, when M is an even number, all lines of the parent node switch and the child node switch are determined one by one as follows:

[0050] {[X, Y], [X, Y+(K4-K2) / 2L], [XM / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [XM / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0051] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-2) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-2) / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0052] ……,

[0053] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-2i+2) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-2i+2) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}, when i<=M / 2;

[0054] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-2i) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-2i) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}, when i>M / 2;

[0055] ……,

[0056] {[X, Y], [X, Y+(K4-K2) / 2L], [X+M / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X+M / 2*(K3-K1) / Q, Y+(K4-K2) / L]}.

[0057] This invention proposes an automatic mapping method based on dynamic analysis of topology structure. It achieves multi-dimensional linkage between the logical connection relationship of equipment topology and the main station display system. It automatically draws the latest topology structure diagram using the existing topology structure, breaking through the traditional isolation of information and organically connecting all relevant information around the topology. Finally, it forms a dynamic display with organic integration of multi-dimensional information and linkage between relevant information, which can effectively improve the system visualization level, intuitively reflect the actual working conditions on site, and improve the efficiency of operation and maintenance personnel in locating problems. Attached Figure Description

[0058] Figure 1 This is a flowchart of a preferred embodiment of the automatic graph generation method based on dynamic topology analysis according to the present invention.

[0059] Figure 2 This is a schematic diagram illustrating an embodiment of the adaptive display area of ​​the automatic mapping method based on dynamic topology analysis according to the present invention.

[0060] Figure 3 This is a schematic diagram illustrating an embodiment of the automatic mapping method for a single-station area according to the present invention based on dynamic topology analysis.

[0061] Figure 4 This is a local connectivity diagram of an embodiment of the solidification method of the automatic graph generation method based on dynamic topology analysis according to the present invention.

[0062] Figure 5 This is a local connectivity diagram of another embodiment of the solidification method of the automatic graph generation method based on dynamic topology analysis according to the present invention. Detailed Implementation

[0063] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0064] Example 1

[0065] like Figure 1 As shown, step 100 is executed to retrieve the logical connection relationships of the display devices from the database. The specific standard format definition is shown in Table 1.

[0066] name type Notes id int topological_id int Topology ID device_num varchar Equipment Number device_name varchar Equipment Name device_type varchar Equipment type substation_id int Belonging to the district ID substation_num varchar Substation number substation_name varchar Name of the area to which it belongs level int hierarchy parent_device_num varchar Parent node number create_time datetime Creation time

[0067] Table 1. Device Logical Connection Relationship Table

[0068] Execute step 110, dynamically defining the display area using four coordinates based on the actual screen size. The display area is automatically calculated and allocated according to the actual screen size. For example, based on the screen resolution (Pixel 1 x Pixel 2, e.g., Pixel 1 = 1920, Pixel 2 = 1080), the actual displayed content is bounded within P1 = [K1, K2], P2 = [K3, K2], P3 = [K1, K4], P4 = [K3, K4]. K1, K2, K3, and K4 are constants and can be flexibly configured (e.g., K1 = 160, K2 = 100, K3 = 1800, K4 = 960). K1 and K3 are smaller than the width (Pixel 1) of the screen resolution, and K2 and K4 are smaller than the height (Pixel 2) of the screen resolution. The content is displayed within the rectangle defined by the four coordinates or with minor extensions to ensure the overall display effect. Figure 2 As shown. By flexibly configuring the above parameters, the specific configuration can be made according to different screen sizes to obtain the position of the display area.

[0069] Step 120 involves automatically searching for the hierarchy of topological connections and the types and quantities of devices at each level. Within the display area, rows and columns are divided into grids, and a topological connection diagram is generated through automatic calculation. By configuring a single-unit display area on a single screen, the content of the single-unit topological display is presented within the effective area (e.g., ...). Figure 3As shown, the size of the grid allocated to a single transformer area depends on the number of switches in the corresponding layer of the transformer area's topology hierarchy. The grid is then divided based on the topology layer with the highest topology level. The size of the grid allocated to transformer area A depends on the number of switches in the corresponding layer of transformer area A's topology hierarchy (e.g., the first, second, third, and fourth layers). Generally, the grid is divided based on the largest topology level in the actual application scenario. Single transformer area interconnection switches only have intra-area interconnection and inter-area interconnection switch modes; generally, the number of interconnection switches is relatively small or nonexistent. The area allocation adaptively adjusts as the number of switches in transformer area A changes.

[0070] Mesh generation methods include row mesh determination methods and column mesh determination methods.

[0071] The row grid is determined by setting the number of layers in the single station area to L, and the pixel value occupied by the number of rows of the row grid is int[(K4-K2) / L]. Scattered pixel deviations can be ignored through viewpoint robustness.

[0072] The column grid determination method is as follows: the number of switches in the layer corresponding to a single station area is set to the total number of switches in layer LL, and the corresponding switch value is: Q = sum(LL), that is, the total number of switches in layer LL is Q, and the number of grid pixels occupied by a single column pixel is int[(K3-K1) / Q]. Scattered pixel deviations can be ignored due to viewpoint robustness. The switch layout in station area A can be divided into more symmetrical sections to closely resemble actual application scenarios.

[0073] Step 130 involves dividing the display area and determining the number of switches in the corresponding LL layer of each station area. The center coordinates of each switch are then set as the center coordinates of the unit grid. This establishes a one-to-one correspondence between the coordinates of all switches in the LL layer and the grid center coordinates. The LL layer contains the most devices. Based on the grid division, the coordinates of the four points (in order from left to right and top to bottom) of the area occupied by station area A in the grid must first be determined:

[0074] [K1,K2] [K3,K2]

[0075] [K1,K4] [K3,K4]

[0076] By dividing the area and the number of switches in the corresponding LL of the substation, the center coordinates of each switch are set as the center coordinates of the cell grid. Then the coordinates of all switches in the LL layer can be determined one-to-one with the center coordinates of the grid.

[0077] Step 140 is executed, and the coordinates of the upper and lower levels corresponding to the coordinates of each switch in the LL layer are automatically deduced based on the determined coordinates of each switch in the LL layer and the upper and lower level correlations in the station area.

[0078] The automatic simulation method includes at least one of the following: special coordinate processing method, coordinate simulation method of LL layer, coordinate simulation method of the layer above LL layer, coordinate simulation method of the layer below LL layer, and supplementary method of interconnection switch for different transformer areas.

[0079] 1. Special coordinate processing method

[0080] The coordinates of the unique switch in the first layer are marked at the center of the network region, with coordinates [(K3-K1) / 2, K2].

[0081] 2. Coordinate derivation method for LL layer

[0082] For communication within a single area, the communication switches are pre-bound according to the database, and the communication switches are placed in adjacent positions. This includes the following sub-steps:

[0083] Step 401: Mark the other switches in the collection unit, including the tie switch, sequentially with the tie switch as the left and right starting point (e.g., Z1, Z2, Z3, Z4 is one collection unit, Z5, Z6, Z7 is another collection unit, Z4, Z5 is the tie switch, then the arrangement order of the two collection units is: Z1, Z2, Z3, Z4, Z5, Z6, Z7).

[0084] Step 402: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right.

[0085] Step 403: By mapping the switch coordinates of LL to the grid center one-to-one, deduce from bottom to top to determine the coordinates of the previous parent node of LL; Assume that the coordinates of the parent node switch of the previous layer of LL are (X, Y), where the column coordinate Y is the width of the grid minus (K4-K2) / L based on the child node, that is, Y = Y_LL - (K4-K2) / L; The row coordinates of the parent node switch are: X = (X_LL_max - X_LL_min) / 2, then the coordinates of the parent node are: ((X_LL_max - X_LL_min) / 2, Y_LL - (K4-K2) / L), where X_LL is the row coordinate of the switch to be calculated in LL layer, Y_LL is the column coordinate of the switch to be calculated in LL layer, X_LL_max is the row coordinate of the rightmost switch under the same output line in LL layer, and X_LL_min is the row coordinate of the leftmost switch under the same output line in LL layer;

[0086] Step 404: Calculate the coordinates of all associated parent nodes of the LL layer through iterative calculation;

[0087] Step 405: Using the topology calculation results of LL, deduce from top to bottom to determine the coordinates of the next layer of LL; assuming that there are W outgoing switches in the next layer of a certain node in LL, then the coordinates are (X1, Y1), ..., (X... w Y w The column coordinate of the switch is Y. w =Y_LL+int[(K4-K2) / L], which means adding a grid with a width of (K4-K2) / L to the LL layer;

[0088] When W is odd, the row coordinate of the switch is X. i =X_LL-((W-2*(i-1)-1) / 2)*(K3-K1) / Q,

[0089] When W is even and i < W / 2, X i =X_LL-((W-2*(i-1)) / 2)*(K3-K1) / Q,

[0090] When W is even and i ≥ W / 2, X i =X_LL-((W-2*(i-1)) / 2-1)*(K3-K1) / Q;

[0091] Where 1≤i≤W;

[0092] Step 406: Calculate the coordinates of all associated child nodes of the next level in the LL layer through iterative calculation.

[0093] 3. Coordinate derivation method of the layer above the LL layer

[0094] The special handling of the interconnection switches on the upper layer of the LL layer involves searching the interconnection relationship table in the interconnection switch database to find the corresponding interconnection switch. For interconnections within a single area, the interconnection switches are placed in adjacent positions. This includes the following sub-steps:

[0095] Step 411: Place the connecting switches in adjacent positions. Then, sequentially coordinate the other switches with the connecting switches as their left and right starting points, generating two aggregation units (e.g., U1, U2, U3, U4 form one aggregation unit, U5, U6, U7 form another aggregation unit, and U4, U5 are connecting switches; the arrangement order of the two aggregation units is: U1, U2, U3, U4, U5, U6, U7). Through sorting, when the coordinates of the switches in an aggregation unit with connecting switches are derived from the LL child nodes, the sorting will complete the corresponding order around those coordinates, with the connecting switches being the left and right starting points of the two aggregation units respectively.

[0096] Step 412: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right.

[0097] 4. Coordinate derivation method for the layer below the LL layer

[0098] By searching the database's interconnection switch relationship table, the corresponding interconnection switches are identified. For interconnections within a single area, the interconnection switches are placed in adjacent positions, including the following sub-steps:

[0099] Step 421: Place the connecting switches in adjacent positions. Then, sequentially coordinate the other switches with connecting switches as their left and right starting points, generating two aggregation units (e.g., G1, G2, G3, G4 form one aggregation unit, G5, G6, G7 form another aggregation unit, and G4, G5 are connecting switches; the order of the two aggregation units is: G1, G2, G3, G4, G5, G6, G7). Through sorting, when the coordinates of a aggregation unit with a connecting switch are derived from the LL child nodes, the sorting will complete the corresponding order around those coordinates, with the connecting switches serving as the left and right starting points of the two aggregation units respectively.

[0100] Step 422: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right.

[0101] By using recursive relationships and continuously deducing the logic of the layer above and below the LL layer, the switching coordinates of the entire station area can be calculated.

[0102] 5. Supplementary methods for interconnection switches in different transformer areas

[0103] When displayed in a single area, the tie switch is identified as a special type of switch in the database. This mainly includes the tie switch's hierarchical information. The specific coordinates will be adjusted according to the coordinates of the hierarchical level. The bus tie switch is placed in the rightmost cell of the grid and marked with the tie switch marker color.

[0104] Step 150 is executed to display the topology based on four-point coordinate positioning. For the single-area display mode, the coordinates of the switch nodes within the area are determined. Through hierarchical relationships, the operating routes of parent and child nodes are fixed one by one using coordinates. The fixing method includes setting the parent and child node switches to 1 input and M outputs, with the parent node A having coordinates (X, Y) and the child nodes having coordinates [(X1, Y1), (X2, Y2), ..., (X...]. M Y MThe lines of parent and child nodes are uniformly formatted using four-point coordinates.

[0105] When M is an odd number, all lines of the parent node switch and child node switch are determined one by one as follows:

[0106] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-1) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-1) / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0107] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-3) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-3) / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0108] ……,

[0109] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-2i-1) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-2i-1) / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0110] ……,

[0111] {[X, Y], [X, Y+(K4-K2) / 2L], [X+M-1)) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X+(M-1) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}.

[0112] When M is an even number, all lines of the parent node switch and child node switch are determined one by one as follows:

[0113] {[X, Y], [X, Y+(K4-K2) / 2L], [XM / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [XM / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0114] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-2) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-2) / 2*(K3-K1) / Q, Y+(K4-K2) / L]},

[0115] ……,

[0116] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-2i+2) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-2i+2) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}, when i<=M / 2;

[0117] {[X, Y], [X, Y+(K4-K2) / 2L], [X-(M-2i) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(M-2i) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}, when i>M / 2;

[0118] ……,

[0119] {[X, Y], [X, Y+(K4-K2) / 2L], [X+M / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X+M / 2*(K3-K1) / Q, Y+(K4-K2) / L]}.

[0120] Example 2

[0121] An automatic mapping method based on dynamic topology analysis also includes a visualization method based on interactive information linkage.

[0122] Prerequisite basic guarantee conditions:

[0123] 1. After the program starts, it will initially collect the opening and closing information of all switches in the affected transformer areas to display the initial effect.

[0124] 2. The validity of specific gate position change information carried in the data needs to be determined according to the corresponding strategy. For details, please refer to the specific constraints related to whether the gate position information and the opening and closing reporting time are invalid.

[0125] 3. Each operation involves only one switch opening or closing, and only affects all circuits associated with that switch. Specifically, when a circuit is de-energized, the switch will trip due to voltage loss. Therefore, when a higher-level switch opens, its downstream switches and their circuits will also turn gray.

[0126] 4. For cross-regional or single-regional communication, the communication is initiated only if one location is considered. If one location is locked, communication with other locations will be disconnected.

[0127] Based on the hierarchical relationship of the topology, the storage format is as follows: [First-level switch number, on / off attribute] -> [Second-level switch number, on / off attribute] -> [Third-level switch number, on / off attribute] -> ... -> [Final-level switch number, on / off attribute], where 1 indicates closed and 0 indicates open.

[0128] Special settings for various communication switches:

[0129] AB area mother connection:

[0130] [Transformer Area A First-Level Switch Number, Bus Tie Switch Number, "Switch Attribute Value", Transformer Area B First-Level Switch Number]

[0131] AB area branch liaison:

[0132] [N1 level switch number for transformer area A, sub-connection switch number, "switch attribute value", N1 level switch number for transformer area B]

[0133] [N2 level switch number for transformer area A, sub-connection switch number, "switch attribute value", N2 level switch number for transformer area B]

[0134] Contact within area A:

[0135] [Transformer Area A, M1 Level Switch Number, Connecting Switch Number, Switch Attribute Value, Transformer Area A, M1 Level Switch Number]

[0136] [Transformer Area A, M2 Level Switch Number, Connecting Switch Number, Switch Attribute Value, Transformer Area A, M2 Level Switch Number]

[0137] Method for determining changes in line conditions based on switch opening and closing information:

[0138] Detection of non-tethering switches

[0139] (1) Received closing information from a non-tethering switch:

[0140] If the non-connecting switch is closed, the opening and closing status of all switches passing through the lower-level nodes of the switch will be checked step by step. If there is an open switch in the lower node, the open switch and the lines below it in the lower node will remain unchanged, and all switches and lines from the closing switch to the open switch will turn red; otherwise, they will be red.

[0141] (2) Received tripping information from a non-tethering switch:

[0142] Check if there is a connecting switch among the downstream switches of this switch.

[0143] If there is no connecting switch, the switch and all its associated downstream switches and lines will be grayed out, but the opening and closing status of the downstream switches will not be changed.

[0144] If a tie switch exists, and the upstream switch of the tie switch is the downstream switch of the trip switch, then only the section of the line from the trip switch to the upstream switch of the tie switch will be grayed out, while other switches and lines will remain unchanged.

[0145] Note: Due to the interlocking relationship, even if there is a tie switch at the lower level, the tie switch is open because the line was previously closed.

[0146] Determination of the contact switch

[0147] (1) Mother contact status

[0148] The status of the bus tie switch closing can be queried through the records:

[0149] If the first-level switch of transformer area A is in the open state and the first-level switch of transformer area B is in the closed state, it indicates that after the bus joint shutdown, transformer area B will switch power to transformer area A. Then, check whether the switches of all lines involving the first-level switches below the first-level switch of transformer area A are open. If there is a switch open, the corresponding open switch and all its downstream switches and lines will turn gray, and the red will extend to the upper port of the open switch; otherwise, it will turn red.

[0150] Note: Due to interlocking, the other two scenarios do not exist. Full closing followed by bus tie is not permitted; if the circuit is fully open, the bus tie becomes meaningless.

[0151] (2) The tripping status of the bus tie switch can be queried through the records:

[0152] If the first-level switch of transformer area A is open and the first-level switch of transformer area B is closed, it indicates that under the bus tie-down state, transformer area B switches power to transformer area A. After the bus tie-down switch is opened, the entire transformer area of ​​transformer area A turns gray.

[0153] Note: Due to the interlocking relationship, the other two cases are ignored.

[0154] Regarding the sub-tether switch situation

[0155] (1) The status of the sub-interconnecting switch closing can be queried through the records:

[0156] If the Nth-level switch of transformer area A is open and the Nth-level switch of transformer area B is closed, it indicates that after the sub-switching, transformer area B will transfer power to transformer area A. Then, check all lines of the Nth-level switches below the Nth-level switch of transformer area A to see if the switches are open: if there are open switches, the corresponding open switch and all its downstream switches and lines will turn gray, and the red will extend to the upper port of the open switch; otherwise, it will turn red.

[0157] Note: Due to interlocking, the other two scenarios do not exist. Full closing followed by sub-connection is not permitted; if all circuits are open, the sub-connection becomes meaningless.

[0158] (2) The status of the sub-connector switch tripping can be queried through the records:

[0159] If the Nth-level switch of transformer area A is in the open state and the Nth-level switch of transformer area B is in the closed state, it indicates that under the sub-connection switch state, transformer area B transfers power to transformer area A. After the sub-connection switch is opened, the corresponding Nth-level switch and lower switches and lines of transformer area A turn gray.

[0160] Note: Due to the interlocking relationship, the other two cases are ignored.

[0161] For communication within area A

[0162] (1) Status of interconnection connection within area A:

[0163] If the left-side switch of level M in transformer area A is open and the right-side switch of level M in transformer area A is closed, it indicates that under the combined shutdown state within transformer area A, the right side of transformer area A is transferring power to the left side of transformer area A. All lines of the left-side switch of the corresponding level M switch in transformer area A are checked level by level to see if there is an open switch: if there is an open switch, the corresponding open switch and all its downstream switches and lines will turn gray, and the red will extend to the upper port of the open switch; otherwise, it will turn red.

[0164] If the left-side switch of level M in transformer area A is closed and the right-side switch of level M in transformer area A is open, it indicates that under the combined closing state within transformer area A, the left side of transformer area A is transferring power to the right side of transformer area A. All lines of the right-side switch of the corresponding level M switch in transformer area A are checked level by level to see if there is an open switch: if there is an open switch, the corresponding open switch and all its downstream switches and lines will turn gray, and the red will extend to the upper port of the open switch; otherwise, it will turn red.

[0165] (2) Connection disconnection status within area A:

[0166] If the left-side switch of the Mth level in transformer area A is in the open state and the right-side switch of the Mth level in transformer area A is in the closed state, it indicates that under the internal joint switch state of transformer area A, transformer area A is transferring power from the right side to the left side of transformer area A. After the internal connecting switch is opened, the switches and lines below the left-side switch of the corresponding Mth level in transformer area A will turn gray.

[0167] If the left-hand switch of the Mth level in transformer substation A is closed and the right-hand switch of the Mth level in transformer substation A is open, it indicates that under the internal joint switch state of transformer substation A, transformer substation A is transferring power from the left to the right. After the internal connecting switch is opened, the switches and lines below the right-hand switch of the Mth level in transformer substation A will turn gray.

[0168] Note: Due to the interlocking relationship, the other two cases are ignored.

[0169] Example 3

[0170] An automatic mapping method based on dynamic topology analysis also includes a method for manually adjusting the automatic graph-model matching.

[0171] For the topology structure, a combination of "pre-determined + calculated" methods is mainly used. The pre-determined topology (manually input into the database according to the actual scenario, with a structure completely consistent with the topology table structure in the calculated table, facilitating later merging of the two tables) serves two main purposes: First, when the data accumulation is insufficient and the automatically calculated topology is not yet ready for display, the pre-determined topology is invoked; second, when the data accumulation is sufficient, there may still be a few cases of no power or sporadic power consumption, which are weak conditions during the calculation process. In these cases, the hierarchical relationship of the switches corresponding to the weak conditions in the pre-determined topology is used as a necessary supplement to the new topology display. In particular, considering the possibility of continuous changes to on-site switches, as the data volume increases, the calculated topology is still the standard, and the reference to the pre-determined topology conditions is avoided as much as possible.

[0172] At the same time, based on the automatically generated topology structure, it supports manual partial page modification and addition functions, that is, setting some partial information, the format of which is completely consistent with the database topology relationship records, and when the front end displays the topology relationship, some of the newly added parts will also be displayed.

[0173] Example 4

[0174] This embodiment proposes a method for fixing the running paths of parent and child nodes.

[0175] Assume the parent and child nodes have a 1-in, 6-out switch configuration, where the coordinates of parent node A are (X, Y), and the coordinates of child nodes B, C, D, E, F, and G are (X1, Y1, X2, Y2, X3, Y3, X4, Y4, X5, Y5, X6, Y6). The local connection relationships are as follows: Figure 4 As shown.

[0176] The lines of parent and child nodes uniformly adopt the four-point coordinate format. In special cases, the coordinates can be specially processed, with the format: {[x1, y1],[x2, y2],[x3, y3],[x4, y4], and other expandable attributes, such as the location of the terminal, additional line indication, etc.}.

[0177] For the specific coordinates mentioned above, the following instantiation can be performed:

[0178] The linear coordinates from A to B are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X-(W-1) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L],[X-(W-1) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}

[0179] The linear coordinates from A to C are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X-(W-3) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L],[X-(W-3) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}

[0180] The linear coordinates from A to D are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X-(W-5) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L],[X-(W-5) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}

[0181] The linear coordinates from A to E are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X-(W-7) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L],[X-(W-7) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}

[0182] The linear coordinates from A to F are represented as: {[X, Y], [X, Y + (K4 - K2) / 2L], [X - (W - 9) / 2 * (K3 - K1) / Q, Y + (K4 - K2) / 2L], [X - (W - 9) / 2 * (K3 - K1) / Q, Y + (K4 - K2) / L]}

[0183] The linear coordinates from A to G are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X-(W-11) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L],[X-(W-11) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}.

[0184] Example 5

[0185] This embodiment proposes another method for solidifying the running paths of parent and child nodes.

[0186] Assume the parent node switch and child node switches are configured with 1 input and 5 outputs, where the coordinates of parent node A are (X, Y), and the coordinates of child nodes B, C, D, E, and F are (X1, Y1, X2, Y2, X3, Y3, X4, Y4, X5, Y5). The local connection relationships are as follows: Figure 5 As shown.

[0187] For the specific coordinates mentioned above, the following instantiation can be performed:

[0188] The linear coordinates from A to B are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X-(W-1) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L],[X-(W-1) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}

[0189] The linear coordinates from A to C are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X-(W-3) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L],[X-(W-3) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}

[0190] The linear coordinates of A->D are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X, Y+(K4-K2) / 2L],[X, Y+(K4-K2) / L]}. The special feature is that X = X3, but it can also be treated as a general four-point coordinate system.

[0191] The linear coordinates from A to E are represented as: {[X, Y],[X, Y+(K4-K2) / 2L],[X-(W-7) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L],[X-(W-7) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}

[0192] The linear coordinates from A to F are represented as: {[X, Y], [X, Y+(K4-K2) / 2L], [X-(W-9) / 2*(K3-K1) / Q, Y+(K4-K2) / 2L], [X-(W-9) / 2*(K3-K1) / Q, Y+(K4-K2) / L]}.

[0193] To better understand this invention, specific embodiments have been described in detail above, but these are not intended to limit the invention. Any simple modifications made to the above embodiments based on the technical essence of this invention still fall within the scope of this invention. Each embodiment in this specification focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

Claims

1. An automatic mapping method based on dynamic topology analysis, comprising obtaining the logical connection relationships of display devices from a database, characterized in that, It also includes the following steps: Step 1: Dynamically define the display area using four coordinates based on the actual screen size; Step 2: By automatically searching the hierarchy of topological connections and the types and quantities of devices contained in each level, the display area is divided into rows and columns, and a topological connection graph is generated through automatic calculation. Step 3: By dividing the display area and the number of switches in the LL layer of the corresponding station area, the center coordinate of each switch is set as the center coordinate position of the unit grid. Then, the coordinates of all switches in the LL layer are determined one-to-one with the center coordinates of the grid. The LL layer is the layer with the most devices. Step 4: Based on the determined coordinates of each switch in the LL layer and its hierarchical relationship within the transformer area, automatically deduce the coordinates of the upper and lower levels corresponding to the coordinates of each switch in the LL layer. The coordinate deduction method for the LL layer includes, for connections within a single transformer area, placing the connections' switches in adjacent positions by pre-binding relationships with relevant connection switches in the database. This includes the following sub-steps: Step 401: Align the other switches in the collection unit, including the tie switch, with the tie switch as the left and right starting point respectively. Step 402: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right. Step 403: By using the one-to-one mapping relationship between the switch coordinates of LL and the grid center, deduce from bottom to top to determine the coordinates of the previous parent node of LL; Step 404: Calculate the coordinates of all associated parent nodes of the LL layer through iterative calculation; Step 405: Using the results of the topology calculation of LL, deduce from top to bottom to determine the coordinates of the next layer of LL; Step 406: Calculate the coordinates of all associated child nodes of the next level in the LL layer through iterative calculation; Step 5: Display the topology based on four-point coordinate positioning. For the single-area display mode, the coordinates of the switch nodes within the area are determined. Through the hierarchical relationship, the operating lines of the parent and child nodes are fixed one by one using coordinates. The fixing method includes setting the parent and child node switches as 1 input and M outputs, with the coordinates of the parent node A being (X, Y) and the coordinates of the child nodes being [(X1, Y1), (X2, Y2), ..., (X... M Y M The lines of parent and child nodes are uniformly formatted using four-point coordinates.

2. The automatic mapping method based on dynamic topology analysis as described in claim 1, characterized in that, The actual content frame displayed in the display area is determined by points P1, P2, P3, and P4, where P1 = [K1, K2], P2 = [K3, K2], P3 = [K1, K4], P4 = [K3, K4], K1, K2, K3, and K4 are constants, and K1 and K3 are less than the width Pixel1 of the screen resolution, and K2 and K4 are less than the height Pixel2 of the screen resolution.

3. The automatic mapping method based on dynamic topology analysis as described in claim 2, characterized in that, The automatic simulation method includes at least one of the following: special coordinate processing method, coordinate simulation method for LL layer, coordinate simulation method for the layer above LL layer, coordinate simulation method for the layer below LL layer, and supplementary method for interconnection switches in different transformer areas.

4. The automatic mapping method based on dynamic topology analysis as described in claim 3, characterized in that, The special coordinate processing method includes marking the coordinates of the unique switch in the first layer at the center of the network area, with coordinates [(K3-K1) / 2, K2].

5. The automatic mapping method based on dynamic topology analysis as described in claim 4, characterized in that, Step 403 includes setting the coordinates of the parent node switch of the layer above the LL layer to (X, Y), the column coordinate of the parent node switch to Y = Y_LL - int[(K4 - K2) / L]; the row coordinate of the parent node switch to X = (X_LL_max - X_LL_min) / 2, then the coordinates of the parent node are: ((X_LL_max - X_LL_min) / 2, Y_LL - (int[(K4 - K2) / L]), where X_LL is the row coordinate of the switch to be calculated in the LL layer, Y_LL is the column coordinate of the switch to be calculated in the LL layer, X_LL_max is the row coordinate of the rightmost switch under the same output line in the LL layer, and X_LL_min is the row coordinate of the leftmost switch under the same output line in the LL layer.

6. The automatic mapping method based on dynamic topology analysis as described in claim 5, characterized in that, Step 405 includes setting the number of outgoing switches in the next layer of a certain node in layer LL to be W, with the coordinates sequentially as (X1, Y1), ..., (X... w Y w The column coordinate of the switch is Y. w =Y_LL+int[(K4-K2) / L]; When W is odd, the row coordinate of the switch is X. i =X_LL-((W-2*(i-1)-1) / 2)*(K3-K1) / Q, When W is even and i < W / 2, X i =X_LL-((W-2*(i-1)) / 2)*(K3-K1) / Q, When W is even and i ≥ W / 2, X i =X_LL-((W-2*(i-1)) / 2-1)*(K3-K1) / Q; Where 1≤i≤W.

7. The automatic mapping method based on dynamic topology analysis as described in claim 3, characterized in that, The coordinate derivation method for the layer above the LL layer also includes placing the switches of the interconnections in adjacent positions for interconnections within a single area, including the following sub-steps: Step 411: Place the connecting switch in an adjacent position, and mark the other switches with the connecting switch as the left and right starting points respectively to generate two aggregation units. Step 412: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right.

8. The automatic mapping method based on dynamic topology analysis as described in claim 3, characterized in that, The coordinate derivation method for the next layer below the LL layer includes finding the corresponding communication switch by searching the database communication switch relationship table, and placing the communication switches in adjacent positions for communication within a single area, including the following sub-steps: Step 421: Place the connecting switch in an adjacent position, and mark the other switches with the connecting switch as the left and right starting points respectively to generate two aggregation units. Step 422: Complete the communication aggregation units in all single-unit areas of this layer in a loop, and then calibrate the other aggregation units without communication switches in the order of the remaining grid from left to right.

9. The automatic mapping method based on dynamic topology analysis as described in claim 3, characterized in that, The method for supplementing interconnecting switches in different transformer areas includes identifying the interconnecting switches as a special type of switch in the database when displaying a single transformer area. This mainly includes the hierarchical information of the interconnecting switches, and the specific coordinates will be adjusted according to the coordinates of the hierarchical level. The bus interconnecting switch is placed in the rightmost cell of the grid and marked with the interconnecting switch marker color.

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