Apparatus and method for chip id generation

Abstract

The application provides a chip ID generation device and method. The chip ID generation device comprises: N chip pin connection terminals configured to be connected with chip pins; and a chip ID generation circuit configured to generate a chip ID according to different connection modes of the N chip pin connection terminals and chip input signals, wherein N is a natural number greater than or equal to 2.

Description

TECHNICAL FIELD

[0001] The present application relates to chip ID generation, and in particular, to a device and method for generating chip IDs according to the connection mode of chip pins and distinguishing chips. BACKGROUND

[0002] With the increasing complexity of various applications, more and more chips are used in a system. The number of chips used in a handheld system (such as a mobile phone) can be dozens to hundreds. Most of the chips work under the control of a controller according to system instructions. In order to control these chips separately, these chips must have different ID address values. In this way, they can be placed on the same system communication bus at the same time. In some application scenarios, multiple identical chips need to be used under the same communication bus, so the control of the chips must be separate. In this case, the IDs of the two or more chips must be different to achieve separate control. In order to achieve the above function, the usual practice is to use an extra pin (generally referred to as a user ID (userID) pin) when designing the chip. By grounding or connecting the pin to a high level or leaving it floating, the chip's internal decoding circuit obtains different IDs of the chip to distinguish different chips. Figure 1 is a schematic diagram showing the pin connection mode of a radio frequency switch chip. Referring to Figure 1 , a SP4T switch chip of a radio frequency switch chip is taken as an example for illustration. However, those skilled in the art should understand that the example is only used for illustration and does not limit the scope of the present application. Figure 1 In the example, there are two identical radio frequency switch chips on the communication bus. The two chips are distinguished by Figure 1 different connection modes of the UserID pins of the radio frequency switch chips in the example.

[0003] However, with the increasing size of various electronic products, the number of pins used by the chips is also decreasing. Still taking the SP4T switch chip shown in Figure 1 as an example, its package pin is shown in Figure 2 .

[0004] Figure 2 is a schematic diagram showing the pin distribution of a radio frequency switch chip. Referring to the chip pin diagram shown in Figure 2 , all 9 pins have been set. If a new UserID pin is required, the size of the chip needs to be increased.

[0005] Therefore, it is necessary to provide a method and device for distinguishing different ID addresses of chips while maintaining the size of the package and the number of package pins. SUMMARY

[0006] One aspect of the present invention provides a chip ID generation device, comprising: N chip pin connection terminals configured to be connected to chip pins; and a chip ID generation circuit configured to generate a chip ID based on different connection methods between the N chip pin terminals and chip input signals, wherein N is a natural number greater than or equal to 2.

[0007] One aspect of the present invention provides a chip ID generation device, wherein the chip pin connection terminals include data line connection terminals and clock signal connection terminals.

[0008] One aspect of the present invention provides a chip ID generation apparatus, wherein the chip ID generation circuit includes two level detection circuits, which are respectively connected to a data line connection terminal and a clock signal connection terminal and are configured to detect pulse signals input from chip pins.

[0009] One aspect of the present invention provides a chip ID generation apparatus, wherein the chip ID generation circuit is configured to determine the chip pin connected to the level detection circuit that first detects the pulse signal as a data line pin, and set the chip ID according to the determination result.

[0010] One aspect of the present invention provides a chip ID generation apparatus, wherein the chip ID generation circuit includes two counters, each of which is connected to a corresponding level detection circuit and configured to count the number of pulse signals detected by the corresponding level detection circuit.

[0011] One aspect of the present invention provides a chip ID generation device, wherein the chip ID generation circuit is configured to determine whether the count of a counter has reached a predetermined threshold, and when the count of the counter reaches the predetermined threshold, to determine that the chip pin connected to the counter whose count has reached the threshold is a pin connected to a clock signal.

[0012] One aspect of the present invention provides a chip ID generation apparatus, wherein the chip ID generation circuit is configured to change the set chip ID when the judgment result based on the level detection circuit is inconsistent with the judgment result based on the counter.

[0013] One aspect of the present invention provides a chip ID generation apparatus, wherein the level detection circuit includes an inverter for detecting the rising and falling edges of a pulse signal.

[0014] One aspect of the present invention provides a method for generating a chip ID, comprising: receiving different chip input signals by connecting N chip pin connection terminals to chip pins, and generating a chip ID according to the different connection methods of the N chip pin terminals and chip input signals, wherein N is a natural number greater than or equal to 2.

[0015] Beneficial effects

[0016] According to various aspects of the present invention, an apparatus and method are realized for distinguishing different ID addresses of a chip while maintaining the package size and number of package pins. Attached Figure Description

[0017] Figure 1 This is a schematic diagram showing the pin connection method of the radio frequency switch chip;

[0018] Figure 2 This is a schematic diagram showing the pin layout of an RF switch chip;

[0019] Figure 3 This is a schematic diagram illustrating how different chips are distinguished by different pin connection methods according to an embodiment of the present invention;

[0020] Figure 4 This is a signal waveform diagram illustrating the system communication bus protocol according to an embodiment of the present invention;

[0021] Figure 5 A schematic diagram of a circuit for generating a chip ID according to an embodiment of the present invention is shown; and

[0022] Figure 6 This is a schematic diagram illustrating a circuit for generating a chip ID according to an embodiment of the present invention. Detailed Implementation

[0023] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this patent document. The terms “coupled,” “connected,” and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are physically in contact with each other. The terms “transmit,” “receive,” and “communicate,” and their derivatives cover both direct and indirect communication. The terms “comprise,” “include,” and their derivatives refer to, but are not limited to, those including, those including, those including, those including. The term “or” is inclusive, meaning and / or. The phrase “associated with,” and its derivatives refer to, including, being contained within, interconnected, containing, being included in, being connected or connected to, coupled or coupled to, communicating with, cooperating, intertwining, juxtaposed, proximate, bound or bound to, having, having attributes, having a relationship or being related to, etc. The term “driver” refers to any device, system, or part thereof that controls at least one operation. Such a driver may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular driver may be centralized or distributed, local or remote. The phrase "at least one" when used with a list of items means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0024] Definitions of other specific words and phrases are provided throughout this patent document. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0025] In this patent document, the combination of modules and the division of sub-modules are for illustrative purposes only. Without departing from the scope of this disclosure, the combination of modules and the division of sub-modules can be done in different ways.

[0026] Figure 3 This is a schematic diagram illustrating how different chips are distinguished by different pin connection methods according to an embodiment of the present invention.

[0027] According to embodiments of the present invention, different chips are distinguished by utilizing the different connection methods between two pins of the chip and the system. Figure 3 The illustrated embodiment shows an example using two pins; however, those skilled in the art will understand that implementations with other numbers of pins can be used without departing from the scope of the invention. Furthermore, in Figure 3In the examples provided, the invention is illustrated using the data line (DATA) pin and the clock (SCLK) pin as examples. However, those skilled in the art should understand that other pins can be used to implement the invention without departing from its scope. References Figure 3 Based on the different connection methods of the data line (DATA) pin and clock (SCLK) pin to the system, the internal circuitry of the chip determines the different connection methods and sets different ID values ​​accordingly, thereby distinguishing different chips.

[0028] refer to Figure 3 Pins 1 and 2 of the chip can be used as both data lines and clock pins, respectively. When pin 1 of one chip is connected to the system data line DATA and pin 2 is connected to the system clock CLK, the internal circuitry of the chip can detect this connection and automatically set the chip's ID value to the first value (e.g., ...). Figure 3 (The ID value is set to "0"). When another chip's pin 1 is connected to the system clock CLK and pin 2 is connected to the system data line DATA, the internal circuitry of that chip can detect this connection and automatically set its ID value to the second value (e.g., Figure 3 The ID value is set to "1" in the code, where the first value is different from the second value. Based on the above operations, the chip generates different ID values ​​for communication with the bus, enabling the system to distinguish between two different chips and thus allowing them to communicate and control separately.

[0029] Figure 4 This is a signal waveform diagram illustrating the protocol of the System Communication Bus (MIPI) according to an embodiment of the present invention.

[0030] refer to Figure 4 When the system communicates with the chip, it first sends a "pulse" (as shown in the diagram) on the data signal line. This pulse represents the data "010". Then, clock and data signals begin to be emitted on the bus. The chip responds accordingly to these clock and data signals. If the address and the chip's ID match, the chip parses the received data instructions and responds, such as controlling its internal logic based on the received information, or replying to the system's read requests. If the address and the chip's ID do not match, the chip does not respond.

[0031] According to an embodiment of the present invention, by determining which pin1 and pin2 of the chip are connected to the clock (CLK) and which are connected to the data line (DATA), the chip ID can be set using two possible different connections, thereby distinguishing two different chips when the chip pins are exactly the same.

[0032] Figure 5 A schematic diagram of a circuit for generating a chip ID according to an embodiment of the present invention is shown.

[0033] refer to Figure 5 Pin 1 and pin 2 are connected to level detection circuits 501 and 502, respectively. Level detection circuits 501 and 502 are used to detect the voltage levels of pins 1 and 2. Furthermore, the outputs of level detection circuits 501 and 502 are connected to a judgment circuit 503. When the judgment circuit 503 detects a pulse signal first on a pin, it can be determined that the pin is connected to a system data line. Figure 3 and Figure 5 In the example shown, when the system and the chip communicate, the first chip on the left detects a pulse signal ("010") on pin 1 before pin 2. At this time, the first chip's determination circuit determines its ID to a first value (e.g., "0") based on this information. Conversely, the second chip on the right detects the pulse ("010") on pin 2 before pin 1. At this time, the second chip's determination circuit determines its ID to a second value different from the first value (e.g., "1") based on this information. Those skilled in the art should understand that the examples of this invention are merely illustrative and are not intended to limit the invention. Appropriate modifications can be made to the invention without departing from its scope.

[0034] Figure 6 This is a schematic diagram illustrating a circuit for generating a chip ID according to an embodiment of the present invention.

[0035] To eliminate the possibility of misjudgments caused by noise such as burrs, the implementation methods of this invention can be optimized. (See reference...) Figure 6Pin 1 and pin 2 are connected to level detection circuits 601 and 602, respectively. Level detection circuits 601 and 602 detect the voltage levels of pins 1 and 2, and output the detection results to judgment circuit 605. According to an embodiment of the present invention, level detection circuits 601 and 602 consist of circuits including inverters for detecting the rising and falling edges of pulses. Furthermore, level detection circuits 601 and 602 are also connected to counters 603 and 604, respectively, to count the number of pulse signals detected by level detection circuits 601 and 602. The counting results are then output to judgment circuit 605.

[0036] refer to Figure 4 When the system communicates with the chip, a pulse signal is first sent on the data line SDATA. However, if a glitch signal appears on the system clock bus (SCLK) for some reason, it will interfere with the chip's judgment and lead to misjudgment. Since the duty cycle of the system clock SCLK is greater than the duty cycle of the data line SDATA, generally, the duty cycle of the clock SCLK is more than twice that of the data line SDATA. Utilizing these characteristics, to eliminate misjudgments caused by noise such as glitches, according to an embodiment of the present invention, two counters are used to count the number of pulses on pin 1 and pin 2 respectively. The pin connected to the counter that first reaches a predetermined threshold is determined to be the pin connected to the clock SCLK. The larger the threshold, the lower the probability of error.

[0037] According to an embodiment of the present invention, when there is no interference from noise such as glitches, a chip ID is generated by a judgment circuit 605 based on the measurement results of level detection circuits 601 and 602. When noise interference may cause level detection circuits 601 and 602 to make incorrect judgments, the judgment results of level detection circuits 601 and 602 are verified by the counting results provided by counters 603 and 604. When the judgment results provided by counters 603 and 604 are inconsistent with the judgment results of level detection circuits 601 and 602, the chip ID setting is changed according to the judgment results of counters 603 and 604. According to an embodiment of the present invention, the possibility of judgment errors can be reduced while quickly setting the chip ID.

[0038] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0039] Any description in this invention should not be construed as implying that any particular element, step, or function is essential and must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.

Claims

1. A chip ID generation device, comprising: N chip pin connection terminals are configured to connect to chip pins; The chip ID generation circuit is configured to generate a chip ID based on the different connection methods between the N chip pin connection terminals and the chip input signals. Where N is a natural number greater than or equal to 2. The chip ID generation circuit includes two level detection circuits, which are respectively connected to the data line connection terminal and the clock signal connection terminal and are configured to detect pulse signals input from the chip pins. The different connection methods between the N chip pin connection terminals and the chip input signals include: the first chip pin connection terminal is connected to the system data line as a data line connection terminal, and the second chip pin connection terminal is connected to the system clock as a clock signal connection terminal; or the first chip pin connection terminal is connected to the system clock as a clock signal connection terminal, and the second chip pin connection terminal is connected to the system data line as a data line connection terminal.

2. The chip ID generation device according to claim 1, wherein, The chip ID generation circuit is configured to identify the chip pin connected to the level detection circuit that first detects the pulse signal as a data line pin, and set the chip ID based on the identification result.

3. The chip ID generation device according to claim 1, wherein, The chip ID generation circuit includes two counters, which are respectively connected to the corresponding level detection circuits and are configured to count the number of pulse signals detected by the corresponding level detection circuits.

4. The chip ID generation apparatus according to claim 3, wherein, The chip ID generation circuit is configured to determine whether the counter count has reached a predetermined threshold, and when the counter count reaches the predetermined threshold, to determine that the chip pin connected to the counter that has reached the threshold is a pin connected to the clock signal.

5. The chip ID generation apparatus according to claim 4, wherein, The chip ID generation circuit is configured to change the set chip ID when the judgment result based on the level detection circuit is inconsistent with the judgment result based on the counter.

6. The chip ID generation apparatus according to claim 1, wherein, The level detection circuit includes an inverter for detecting the rising and falling edges of a pulse signal.

7. A method for generating a chip ID, comprising: Different chip input signals are received by connecting to the chip pins through N chip pin connection terminals. The chip ID is generated based on the different connection methods between the N chip pin connection terminals and the chip input signals. Where N is a natural number greater than or equal to 2. The chip ID generation process includes: using two level detection circuits connected to the data line connection terminal and the clock signal connection terminal respectively to detect pulse signals input from the chip pins to generate the chip ID. The different connection methods between the N chip pin connection terminals and the chip input signals include: the first chip pin connection terminal is connected to the system data line as a data line connection terminal, and the second chip pin connection terminal is connected to the system clock as a clock signal connection terminal; or the first chip pin connection terminal is connected to the system clock as a clock signal connection terminal, and the second chip pin connection terminal is connected to the system data line as a data line connection terminal.

Images