Display devices and pixel units with internal compensation

Abstract

A display device and pixel unit with internal compensation are provided. The display device includes pixels connected to a first scan line, a second scan line, a third scan line, a data line, a first emission control line, and a second emission control line. Each pixel includes: a light-emitting element; a first transistor connected between a first node connected to a first power supply and a second node connected to the anode of the light-emitting element, and including a gate electrode connected to a third node; a second transistor connected between the data line and a fourth node, and including a gate electrode connected to the first scan line; a first capacitor connected between the second node and a fifth node; a second capacitor connected between the fourth node and the fifth node; a fourth transistor connected between the third node and the fifth node, and including a gate electrode connected to the second scan line; and a sixth transistor connected between the third node and the fourth node, and including a gate electrode connected to the first emission control line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0125224, filed with the Korean Intellectual Property Office on September 25, 2020, the entire contents of which are incorporated by reference. Technical Field

[0003] This disclosure relates generally to display devices, and more specifically to display devices with internal compensation. Background Technology

[0004] With the development of information technology, the role of display devices, which provide a connection medium between users and information, is receiving increasing attention. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays is growing rapidly.

[0005] The display device may include pixels connected to scan lines and data lines, a scan driver for driving the scan lines, and a data driver for driving the data lines. Each pixel may include pixel circuitry, which includes a transistor, a capacitor, and a light-emitting element. When a scan signal is supplied from the scan line, the pixel circuitry may receive a data voltage from the data line and supply current to the light-emitting element according to the data voltage. The light-emitting element may emit light with an intensity corresponding to the current of the driving transistor.

[0006] In the presence of process variations or degradation, the desired pixel grayscale value may not be accurately achieved due to deviations in the electrical characteristics (such as threshold voltage) of the driving transistors between pixels. Therefore, internal compensation methods can be used to compensate for deviations in the electrical characteristics of the driving transistors within a pixel, and / or external compensation methods can be used to compensate for deviations in the electrical characteristics of the driving transistors outside the pixel. Summary of the Invention

[0007] Internal compensation methods may include setting the gate voltage of the driving transistor in a source follower approach. The source follower internal compensation method can adjust the gate potential of the driving transistor while simultaneously increasing the source potential towards the gate potential to compensate for deviations in the electrical characteristics of the driving transistor.

[0008] In a source follower type pixel, when another capacitor is connected to a storage capacitor arranged between the gate and source electrodes of the driving transistor, the voltage difference across the storage capacitor can change according to the capacitance ratio between the two capacitors. When the voltage difference across the storage capacitor decreases, a larger data voltage can be supplied to the pixel to achieve the desired grayscale value.

[0009] Embodiments of this disclosure provide a pixel capable of preventing data voltage loss or degradation due to capacitors. Another embodiment of this disclosure provides a pixel capable of high-resolution and high-speed driving by sufficiently ensuring time periods for compensating for deviations in the electrical characteristics of the driving transistors, such as threshold voltage. However, embodiments of this disclosure are not limited to the above-described embodiments and various adaptations or extensions can be made without departing from the scope and spirit of this disclosure.

[0010] A display device according to embodiments of the present disclosure may include a plurality of pixels connected to a first scan line, a second scan line, a third scan line, a data line, a first emission control line, and a second emission control line. Each of the plurality of pixels may include: a light-emitting element; a first transistor connected between a first node connected to a first power supply and a second node connected to the anode of the light-emitting element, and including a gate electrode connected to a third node; a second transistor connected between a data line and a fourth node, and including a gate electrode connected to the first scan line; a first capacitor connected between the second node and a fifth node; a second capacitor connected between the fourth node and the fifth node; a fourth transistor connected between the third node and the fifth node, and including a gate electrode connected to the second scan line; and a sixth transistor connected between the third node and the fourth node, and including a gate electrode connected to the first emission control line. The display device may further include: a third transistor connected between the third node and a third power supply, and including a gate electrode connected to the second scan line. The display device may further include: a fifth transistor connected between the second node and the fourth power supply, and including a gate electrode connected to the third scan line. The display device may further include: a seventh transistor connected between the first node and the first power supply, and including a gate electrode connected to the second emission control line.

[0011] The display device may further include a non-emission period and an emission period. The non-emission period includes: an initialization period, in which the second node is initialized by a fourth power supply and the fifth node is initialized by a third power supply; a compensation period, in which the threshold voltage of the first transistor is compensated; and a data writing period, in which a data voltage applied through a data line is supplied to the third node, and in the emission period, the light-emitting element emits light in response to the data voltage. The data writing period may overlap with the compensation period, and during the compensation period, the voltage of the fifth node may be maintained by the third power supply.

[0012] The first through seventh transistors can be N-type thin-film transistors, with a gate on-voltage of logic high and a gate off-voltage of logic low. The third and fourth transistors can remain on during the initialization, compensation, and data write phases, and the fifth transistor can be on during the initialization phase. During the compensation phase, the seventh transistor can remain on.

[0013] During the compensation period, the voltage of the second node can converge to the voltage difference between the third power supply and the threshold voltage of the first transistor, and during the compensation period, the voltage difference across the first capacitor can correspond to the threshold voltage of the first transistor. The data write period can overlap with the compensation period, and the second transistor can be turned on during the data write period. During the data write period, the voltage difference across the second capacitor can be the difference between the data voltage and the third power supply.

[0014] During the emission period, the first and second capacitors can be connected in series between the second and third nodes. During the emission period, the sixth and seventh transistors can remain in the on state, and the fourth transistor can remain in the off state. The cathode of the light-emitting element can be connected to a second power supply.

[0015] A pixel unit according to embodiments of the present disclosure may include multiple pixels, each pixel including: a light-emitting element including a cathode connected to a second power supply; a first transistor including a first electrode, a second electrode connected to the anode of the light-emitting element, and a gate electrode; a third transistor including a first electrode connected to a third power supply, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to a second scan line; a fourth transistor including a first electrode connected to the gate electrode of the first transistor, a second electrode, and a gate electrode connected to the second scan line; a first capacitor connected between the second electrode of the first transistor and the second electrode of the fourth transistor; and a seventh transistor including a first electrode connected to the first power supply, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a second emission control line. The gate electrode of the first transistor may be connected to the second electrode of the third transistor and the first electrode of the fourth transistor.

[0016] Each pixel may further include a second transistor, which includes a first electrode, a second electrode, and a gate electrode connected to a data line. Each pixel may also include a second capacitor connected between the second electrode of the second transistor and the second electrode of the fourth transistor. Each pixel may further include: a fifth transistor, including a first electrode connected to the second electrode of the first transistor, a second electrode connected to a fourth power supply, and a gate electrode connected to a third scan line; and a sixth transistor, including a first electrode connected to the second electrode of the second transistor, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to a first emitter control line. The first to seventh transistors may be P-type thin-film transistors, with a gate on-voltage that is logic low and a gate off-voltage that is logic high. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept.

[0018] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0019] Figure 2 This is a circuit diagram used to explain the pixels according to embodiments of the present disclosure;

[0020] Figure 3 It shows the supply to Figure 2 A timing diagram of an example of the driving signals for a pixel;

[0021] Figure 4 It is a mixed circuit and timing diagram used to explain the operation of pixels during the initialization period;

[0022] Figure 5 It is a mixed circuit and timing diagram used to explain the operation of pixels during the compensation period;

[0023] Figure 6 It is a mixed circuit and timing diagram used to explain the operation of pixels during the data writing period; and

[0024] Figure 7 It is a mixed circuit and timing diagram used to explain the operation of pixels during the emission period. Detailed Implementation

[0025] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals may be used for the same or similar elements, and repeated descriptions of the same or similar elements may be omitted.

[0026] Figure 1 A display device according to an embodiment of the present disclosure is shown.

[0027] Reference Figure 1 The display device 1000 may include pixel units 100, scan drivers 200, transmit drivers 300, data drivers 400, and timing controllers 500. Each of the drivers and / or controllers may be implemented as one or more circuits. Alternatively, one or more of the drivers and / or controllers may be combined in an integrated circuit.

[0028] In an embodiment, the display device 1000 may further include a power supply unit for supplying voltages of a first power supply VDD, a second power supply VSS, a third power supply Vref, and a fourth power supply Vint to the pixel unit 100. However, this is just an example, and at least one of the first power supply VDD, the second power supply VSS, the third power supply Vref, and the fourth power supply Vint may be supplied from the timing controller 500 or the data driver 400.

[0029] Pixel unit 100 may include a plurality of first scan lines SL11 to SL1n, a plurality of second scan lines SL21 to SL2n, a plurality of third scan lines SL31 to SL3n, a plurality of first emission control lines EL11 to EL1n, a plurality of second emission control lines EL21 to EL2n, a plurality of data lines DL1 to DLm, and a plurality of (e.g., an n×m matrix) pixels PX connected to the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, the third scan lines SL31 to SL3n, the first emission control lines EL11 to EL1n, the second emission control lines EL21 to EL2n, and the data lines DL1 to DLm, where n and m may be integers greater than 1. Each of the pixels PX may include a driving transistor and a plurality of switching transistors.

[0030] The scan driver 200 can sequentially supply scan signals to the pixel PX via first scan lines SL11 to SL1n, second scan lines SL21 to SL2n, and third scan lines SL31 to SL3n based on a first control signal such as a scan control signal SCS. The scan driver 200 can receive the first control signal, at least one clock signal, etc., from the timing controller 500.

[0031] In an implementation, the scan signal supplied to a scan line during a frame period may include at least one scan pulse. For example, the scan signal may include a first scan signal SS1 sequentially supplied to first scan lines SL11 to SL1n (see...). Figure 2 The second scan signal SS2 (see) is sequentially supplied to the second scan lines SL21 to SL2n. Figure 2) and the third scan signal SS3 sequentially supplied to the third scan lines SL31 to SL3n (see Figure 2 ).

[0032] The first scan signal SS1 may include at least one first scan pulse, the second scan signal SS2 may include at least one second scan pulse, and the third scan signal SS3 may include at least one third scan pulse. Here, the first, second, and third scan pulses can be gate on-state voltages used to turn on the transistors included in the pixel PX. For example, when the transistors included in the pixel PX are P-channel metal-oxide-semiconductor (PMOS) transistors (e.g., P-type), the gate on-state voltage can be set to a logic low level, and the gate off-state voltage can be set to a logic high level. When the transistors included in the pixel PX are N-channel metal-oxide-semiconductor (NMOS) transistors (e.g., N-type), the gate on-state voltage can be set to a logic high level, and the gate off-state voltage can be set to a logic low level. In alternative embodiments, some of the transistors may be N-type and others may be P-type, but the implementation is not limited to this.

[0033] In an implementation, the scan driver 200 may include: being interconnected to sequentially output a first scan signal SS1, including a first scan pulse, to a first stage of first scan lines SL11 to SL1n; being interconnected to sequentially output a second scan signal SS2, including a second scan pulse, to a second stage of second scan lines SL21 to SL2n; and being interconnected to sequentially output a third scan signal SS3, including a third scan pulse, to a third stage of third scan lines SL31 to SL3n.

[0034] The transmit driver 300 can sequentially supply transmit control signals to pixels PX via first transmit control lines EL11 to EL1n and second transmit control lines EL21 to EL2n based on a second control signal, such as a transmit control signal ECS. The transmit driver 300 can receive the second control signal, clock signal, etc., from the timing controller 500. Each transmit control signal can divide a frame period into a transmit period and a non-transmit period for pixels PX located on the same horizontal line or row.

[0035] In an implementation, the transmit control signal may include a first transmit control signal EM1 sequentially supplied to the first transmit control lines EL11 to EL1n (see [link]). Figure 2 ) and the second transmit control signal EM2 sequentially supplied to the second transmit control lines EL21 to EL2n (see Figure 2 ).

[0036] The data driver 400 can receive a third control signal, such as a data control signal DCS, and image data, such as RGB (red-green-blue), from the timing controller 500. Based on the third control signal and the image data, the data driver 400 can supply data signals, such as data voltages, to the pixel PX via data lines DL1 to DLm. In one embodiment, the data driver 400 can supply data signals corresponding to the grayscale values ​​of the image to the data lines DL1 to DLm. For example, the data signal for the corresponding pixel PX can be supplied synchronously to the corresponding pixel PX with each first scan signal SS1 including a first scan pulse.

[0037] The timing controller 500 can control the operation of the scan driver 200, the transmit driver 300, and the data driver 400 based on timing signals supplied from an external source. The timing controller 500 can supply control signals, including a first control signal and a scan clock signal, to the scan driver 200, and can supply control signals, including a second control signal and a transmit control clock signal, to the transmit driver 300. A third control signal for controlling the data driver 400 may include a source start signal, a source output enable signal, and a source sampling clock.

[0038] Figure 2 Pixels according to an embodiment of this disclosure are shown. For ease of explanation, pixels PX arranged in the i-th row and j-th column will be described as examples, where i and j can be natural numbers greater than 1.

[0039] Reference Figure 1 and Figure 2 A pixel PX may include a pixel circuit PXC and a light-emitting element LD connected to the pixel circuit PXC. The pixel circuit PXC may control the amount of current flowing from a first power supply VDD through the light-emitting element LD to a second power supply VSS in response to a data voltage Vdata. The first power supply VDD may be set to a voltage higher than the second power supply VSS. The anode of the light-emitting element LD may be connected to the pixel circuit PXC, and the cathode may be connected to the second power supply VSS. The light-emitting element LD may generate light with a predetermined brightness in response to the amount of current supplied from the pixel circuit PXC.

[0040] In an alternative embodiment, the anode of the light-emitting element LD can be connected to a first power supply VDD, and the cathode can be connected to the pixel circuit PXC.

[0041] The pixel circuit PXC according to the embodiment may include a first transistor TR1 to a seventh transistor TR7, a first capacitor C1 and a second capacitor C2.

[0042] The first transistor TR1 may include a first electrode connected to a first node N1, a second electrode connected to a second node N2, and a gate electrode connected to a third node N3. The first electrode may be connected to a first power supply VDD via a seventh transistor TR7, and the second electrode may be connected to the anode of the light-emitting element LD. The gate electrode may be connected to the j-th data line DLj via a second transistor TR2 and a sixth transistor TR6.

[0043] According to an embodiment, the first electrode can be the drain electrode of the first transistor TR1, and the second electrode can be the source electrode of the first transistor TR1. The first transistor TR1 can supply a drive current to the light-emitting element LD corresponding to the voltage of the third node N3 (such as the gate electrode). That is, the first transistor TR1 can be used as the driving transistor of the pixel PX.

[0044] The second transistor TR2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the fourth node N4, and a gate electrode connected to the first i-th scan line SL1i. The gate electrode can receive the first scan signal SS1 through the first i-th scan line SL1i. When the second transistor TR2 is turned on by the first scan signal SS1, the data voltage Vdata can be transmitted to the fourth node N4.

[0045] The third transistor TR3 may include a first electrode connected to a third power supply Vref, a second electrode connected to a third node N3, and a gate electrode connected to a second i-th scan line SL2i. The gate electrode can receive a second scan signal SS2 through the second i-th scan line SL2i. When the third transistor TR3 is turned on by the second scan signal SS2, the third power supply Vref can be transmitted to the third node N3. In this case, the third power supply Vref can be set to a specific voltage with a substantially DC component.

[0046] The fourth transistor TR4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5, and a gate electrode connected to the second i-th scan line SL2i. The gate electrode can receive the second scan signal SS2 through the second i-th scan line SL2i. When the fourth transistor TR4 is turned on by the second scan signal SS2, the voltage of the third node N3, such as the third power supply Vref, can be transmitted to the fifth node N5.

[0047] The fifth transistor TR5 may include a first electrode connected to the second node N2, a second electrode connected to the fourth power supply Vint, and a gate electrode connected to the third i-th scan line SL3i. The gate electrode can receive the third scan signal SS3 through the third i-th scan line SL3i. When the fifth transistor TR5 is turned on by the third scan signal SS3, the fourth power supply Vint can be transmitted to the second node N2. In this case, the fourth power supply Vint can be ground voltage. However, the fourth power supply Vint is not limited to this and can be set to a specific voltage with a substantially DC component, like the third power supply Vref.

[0048] The sixth transistor TR6 may include a first electrode connected to the fourth node N4, a second electrode connected to the third node N3, and a gate electrode connected to the first i-th transmit control line EL1i. The gate electrode can receive a first transmit control signal EM1 via the first i-th transmit control line EL1i. When the sixth transistor TR6 is turned on by the first transmit control signal EM1, the voltage of the fourth node N4, such as the data voltage Vdata, can be transmitted to the third node N3.

[0049] The seventh transistor TR7 may include a first electrode connected to the first power supply VDD, a second electrode connected to the first node N1, and a gate electrode connected to the second i-th transmit control line EL2i. The gate electrode can receive the second transmit control signal EM2 through the second i-th transmit control line EL2i. When the seventh transistor TR7 is turned on by the second transmit control signal EM2, the first power supply VDD can be transmitted to the first node N1.

[0050] A first capacitor C1 can be connected between the second node N2 and the fifth node N5. In this case, the fifth node N5 can be connected to the gate electrode of the first transistor TR1 via the fourth transistor TR4. That is, the first capacitor C1 can be connected between the gate electrode and the source electrode (such as the second electrode) of the first transistor TR1. The first capacitor C1 can store the voltage difference between the voltage of the second node N2 and the voltage of the third node N3, which changes according to the operating timing of the pixel PX.

[0051] The second capacitor C2 can be connected between the fourth node N4 and the fifth node N5. In this case, the fourth node N4 can be connected to the j-th data line DLj via the second transistor TR2. That is, the second capacitor C2 can be connected between the j-th data line DLj and the fifth node N5. The second capacitor C2 can store the data voltage Vdata applied through the j-th data line DLj. Subsequently, when the sixth transistor TR6 is turned on, the data voltage Vdata can be provided to the third node N3, such as the gate electrode of the first transistor TR1.

[0052] The light-emitting element (LD) can be connected between the second node N2 and the second power supply VSS. The cathode of the LD can receive the second power supply VSS. The first power supply VDD and the second power supply VSS can have different potentials. As an example, the first power supply VDD can be set to a high potential power supply, and the second power supply VSS can be set to a low potential power supply. In this case, during the emission period of pixel PX, the potential difference between the first power supply VDD and the second power supply VSS can be set to be greater than or equal to the threshold voltage of the LD.

[0053] Figure 3 It shows the supply to Figure 2 An example of the driving signal for a pixel.

[0054] Reference Figure 1 , Figure 2 and Figure 3 A frame period of the display device 1000 may include a transmission period EP and a non-transmission period NEP. In this case, although the non-transmission period NEP included in a frame period is shown to be longer than the transmission period EP, it should be understood that the length of the transmission period EP may actually be longer than the length of the non-transmission period NEP.

[0055] The non-emission period (NEP) can be the period from the first time point t1 to the ninth time point t9, and can be defined as the period during which pixel PX substantially does not emit light. The transmission period (EP) can be the period from the ninth time point t9 to the tenth time point t10 before the start of the next frame, and can be defined as the period during which pixel PX substantially emits light in response to the received data signal. The second scan signal SS2 can change from a logic low level to a logic high level at the second time point t2.

[0056] The non-emission period (NEP) of the display device 1000 may include an initialization period P1 for initializing the source electrode (such as the second electrode) and gate electrode of the first transistor TR1 during the NEP, a compensation period P2 for compensating the electrical characteristics of the first transistor TR1, such as the threshold voltage Vth, and a data writing period P3 for writing a data signal to the gate electrode of the first transistor TR1. In this case, the initialization period P1 may correspond to the period from the third time point t3 to the fourth time point t4, the compensation period P2 may correspond to the period from the fifth time point t5 to the eighth time point t8, and the data writing period P3 may correspond to the period from the sixth time point t6 to the seventh time point t7.

[0057] According to embodiments of this disclosure, during the initialization period P1, the gate electrode of the first transistor TR1 may be initialized by a third power supply Vref, and the source electrode (such as a second electrode) may be initialized by a fourth power supply Vint.

[0058] During the compensation period P2, the voltage Vs of the source electrode (such as the second electrode) of the first transistor TR1 converges to the difference between the third power supply Vref and the threshold voltage Vth of the first transistor TR1, i.e., Vs = Vref - Vth. At this time, since the voltage Vg of the gate electrode of the first transistor TR1 corresponds to the third power supply Vref, the threshold voltage Vth of the first transistor TR1 can be stored in the first capacitor C1.

[0059] During the data writing period P3, the data voltage Vdata corresponding to the data signal can be stored in the second capacitor C2.

[0060] During the emission period EP, a predetermined current is supplied from the first transistor TR1 to the light-emitting element LD in response to the voltage Vg of the gate electrode (such as the third node N3) of the first transistor TR1. In this case, the light-emitting element LD can generate light with a predetermined brightness in response to the amount of current supplied from the first transistor TR1.

[0061] The following can be used as a reference. Figures 4 to 7 The detailed operation of pixel PX in each of the time periods P1, P2, P3 and EP is further described.

[0062] Figure 4 The operation of pixels during the initialization period is shown.

[0063] Reference Figure 4 During the initialization period P1, the first transmit control signal EM1 and the second transmit control signal EM2 can each have a logic low level, the first scan signal SS1 can have a logic low level, the second scan signal SS2 can have a logic high level, and the third scan signal SS3 can change from a logic low level to a logic high level. Correspondingly, the first capacitor C1 can be initialized by the third power supply Vref and the fourth power supply Vint.

[0064] Specifically, since the third transistor TR3 and the fourth transistor TR4 are in the on state during the initialization period P1, the third power supply Vref can be supplied to the third node N3 and the fifth node N5. Furthermore, since the fifth transistor TR5 is in the on state during the initialization period P1, the fourth power supply Vint can be supplied to the second node N2. As a result, the first capacitor C1 can be initialized with the voltage corresponding to the difference between the third power supply Vref and the fourth power supply Vint. In this case, since the sixth transistor TR6 and the seventh transistor TR7 are in the off state during the initialization period P1, the light-emitting element LD can remain in a non-emitting state.

[0065] Figure 5 The operation of pixels during the compensation period is shown.

[0066] Reference Figure 5 During the compensation period P2, the first transmit control signal EM1 may be at a logic low level, the second transmit control signal EM2 may change from a logic low level to a logic high level, the first scan signal SS1 may be at a logic low level, the second scan signal SS2 may be at a logic high level, and the third scan signal SS3 may be at a logic low level. Correspondingly, the voltage corresponding to the threshold voltage Vth of the first transistor TR1 can be stored in the first capacitor C1 through the first power supply VDD and the third power supply Vref.

[0067] Specifically, while the first transistor TR1 is turned on, the fifth transistor TR5 can be turned off, and the third transistor TR3 and the fourth transistor TR4 can remain on. Accordingly, a third power supply Vref can be supplied to the third node N3, such as the gate electrode of the first transistor TR1, and the second node N2, such as the source electrode of the first transistor TR1, can be electrically floated by the turned-off fifth transistor TR5. Accordingly, the first transistor TR1 can be turned on by the third power supply Vref of the third node N3 (such as the gate electrode of the first transistor TR1) to operate as a source follower, and can be turned off when the source voltage is a voltage Vref-Vth obtained by subtracting the threshold voltage Vth of the first transistor TR1 from the third power supply Vref. Therefore, a voltage (such as a compensation voltage) corresponding to the threshold voltage Vth of the first transistor TR1 can be charged in the first capacitor C1. That is, the first capacitor C1 can be charged with a voltage equal to or close to the difference between the third power supply Vref and the threshold voltage Vth of the first transistor TR1.

[0068] Figure 6 The operation of pixels during the data writing period is shown.

[0069] Reference Figure 6 During the data writing period P3, the first transmit control signal EM1 may be at a logic low level, the second transmit control signal EM2 may be at a logic high level, the first scan signal SS1 may change from a logic low level to a logic high level, the second scan signal SS2 may be at a logic high level, and the third scan signal SS3 may be at a logic low level. Accordingly, the data voltage Vdata may be stored in the second capacitor C2.

[0070] Specifically, since the third transistor TR3 and the fourth transistor TR4 are in the on state during the data writing period P3, the third power supply Vref can still be supplied to the fifth node N5. Furthermore, since the sixth transistor TR6 is in the off state during the data writing period P3, the third node N3 and the fourth node N4 can be electrically open-circuited. Because the second transistor TR2 is in the on state, the data voltage Vdata received through the j-th data line DLj can be supplied to the fourth node N4. That is, the second capacitor C2 can be charged to a voltage equal to the difference between the third power supply Vref and the voltage of the fourth node N4, or a voltage close to the data voltage Vdata.

[0071] Thus, although the data writing period P3 overlaps with the compensation period P2, the compensation operation and the data writing operation can be separated by continuously supplying a third power supply Vref to the intermediate node between the series-connected first capacitor C1 and second capacitor C2 during the compensation period P2. That is, since the fifth node N5 serves as a ground node, the threshold voltage Vth of the first transistor TR1 can be compensated through the first capacitor C1, and simultaneously, the data voltage Vdata can be written through the second capacitor C2. Accordingly, since the pixel PX according to the embodiment of this disclosure can ensure a sufficient compensation period P2, the effect of driving the display device 1000 with high resolution and high speed can be expected.

[0072] Figure 7 The operation of the pixels during the emission period is shown.

[0073] Reference Figure 7 During the transmission period EP, the first transmission control signal EM1 and the second transmission control signal EM2 may have a logic high level, and the first scan signal SS1, the second scan signal SS2, and the third scan signal SS3 may have a logic low level. Accordingly, the light-emitting element LD can emit light through the first power supply VDD and the voltage of the first capacitor C1 and the second capacitor C2.

[0074] Since the sixth transistor TR6 is in the on state during the emission period EP, the data voltage Vdata stored in the second capacitor C2 can be supplied to the third node N3, such as the gate electrode of the first transistor TR1. Furthermore, since the seventh transistor TR7 is in the on state, the first power supply VDD can be supplied to the first node N1, such as the drain electrode of the first transistor TR1. Then, the first transistor TR1 can control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light-emitting element LD in response to the voltage of the third node N3 (such as the gate electrode of the first transistor TR1). Accordingly, during the emission period EP, the light-emitting element LD can generate light with a predetermined brightness in response to the amount of current supplied from the first transistor TR1. During the emission period EP, the current Ids supplied from the first transistor TR1 to the light-emitting element LD can be set as shown in the following equation. In this case, the voltage Vg of the gate electrode of the first transistor TR1 can be Vdata[V], and the voltage Vs of the source electrode can be Vref-Vth[V].

[0075] [Equation 1]

[0076] Ids = k(Vgs - Vth) 2 =k(Vdata-(Vref-Vth)-Vth) 2 = k(Vdata-Vref) 2

[0077] Here, k represents a constant, and Vgs represents the gate-source voltage of the first transistor TR1, which is the voltage difference between the gate electrode voltage Vg and the source electrode voltage Vs of the first transistor TR1.

[0078] Referring to the above equation, the current Ids supplied from the first transistor TR1 to the light-emitting element LD can be determined in correspondence with the voltage difference between the data voltage Vdata and the third power supply Vref. Since the third power supply Vref is a fixed voltage, the current Ids supplied to the light-emitting element LD can be determined in correspondence with the data voltage Vdata.

[0079] As shown in the equation, the current Ids supplied to the light-emitting element LD can be determined independently of the first power supply VDD and the threshold voltage Vth of the first transistor TR1. Accordingly, in this disclosure, the current Ids can be supplied to the light-emitting element LD independently of the voltage drop of the first power supply VDD and the deviation of the threshold voltage Vth of the first transistor TR1. Accordingly, the reliability of the display quality of the display device 1000 can be ensured.

[0080] Furthermore, during the transmission period EP, since the first capacitor C1 and the second capacitor C2 are connected in series between the second node N2 (such as the source electrode of the first transistor TR1) and the third node N3 (such as the gate electrode of the first transistor TR1), the phenomenon that the gate-source voltage Vgs of the first transistor TR1 changes according to the capacitance ratio between the capacitors can be prevented. That is, the loss of data voltage Vdata can be prevented.

[0081] As a result, since it is not necessary to supply a larger data voltage Vdata to the pixel PX to compensate for the lost data voltage Vdata (i.e., since the data swing range does not increase), the power consumption required to drive the display device 1000 can be reduced.

[0082] In a pixel according to an embodiment of the present disclosure, data voltage loss due to the capacitor can be prevented by applying a reference voltage with a DC component to the intermediate node of the series-connected capacitor.

[0083] According to embodiments of this disclosure, pixels can be implemented using N-type thin-film transistors, and a reference voltage with a DC component can be applied to the intermediate node of a series-connected capacitor. Therefore, high-resolution and high-speed driving can be achieved by sufficiently ensuring the time period for compensating for deviations in the electrical characteristics of the driving transistors, such as the threshold voltage.

[0084] However, the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. For example, in an alternative embodiment, the first to seventh transistors may be P-type thin-film transistors, the gate on-voltage may have a logic low level, and the gate off-voltage may have a logic high level.

[0085] Embodiments of the present disclosure have been described above with reference to figures. However, those skilled in the art to which this disclosure pertains will appreciate that various modifications and changes can be made to the disclosed embodiments without departing from the scope and spirit of the inventive concept as set forth in the appended claims.

Claims

1. A display device, comprising: Multiple pixels are connected to the first scan line, the second scan line, the third scan line, the data line, the first emission control line, and the second emission control line. Each of the plurality of pixels includes: Light-emitting elements; A first transistor is connected between a first node connected to a first power supply and a second node connected to the anode of the light-emitting element, and includes a gate electrode connected to a third node. The second transistor is connected between the data line and the fourth node, and includes a gate electrode connected to the first scan line; A third transistor is connected between the third node and the third power supply, and includes a gate electrode connected to the second scan line; The first capacitor is connected between the second node and the fifth node; A second capacitor is connected between the fourth node and the fifth node; A fourth transistor, connected between the third node and the fifth node, and including a gate electrode connected to the second scan line; and A sixth transistor is connected between the third node and the fourth node, and includes a gate electrode connected to the first emitter control line.

2. The display device as claimed in claim 1, further comprising: The fifth transistor is connected between the second node and the fourth power supply, and includes a gate electrode connected to the third scan line.

3. The display device as claimed in claim 2, further comprising: A seventh transistor is connected between the first node and the first power supply, and includes a gate electrode connected to the second emitter control line.

4. The display device as claimed in claim 3, further comprising: The non-emission period includes: an initialization period, during which the second node is initialized by the fourth power supply and the fifth node is initialized by the third power supply; a compensation period, during which the threshold voltage of the first transistor is compensated; and a data writing period, during which a data voltage applied through the data line is supplied to the third node; and During the emission period, the light-emitting element emits light in response to the data voltage.

5. The display device as described in claim 4, in, The data writing period overlaps with the compensation period, and During the compensation period, the voltage of the fifth node is maintained by the third power source.

6. The display device as claimed in claim 4, wherein, The first to the seventh transistors are N-type thin-film transistors, with a gate on-voltage having a logic high level and a gate off-voltage having a logic low level.

7. The display device as claimed in claim 4, in, The third transistor and the fourth transistor remain in the ON state during the initialization period, the compensation period, and the data write period, and The fifth transistor is turned on during the initialization period.

8. The display device as claimed in claim 4, wherein, During the compensation period, the seventh transistor remains in the on state.

9. The display device as claimed in claim 8, in, During the compensation period, the voltage of the second node converges to the voltage difference between the third power supply and the threshold voltage of the first transistor, and During the compensation period, the voltage difference between the two ends of the first capacitor corresponds to the threshold voltage of the first transistor.

10. The display device as claimed in claim 9, in, The data writing period overlaps with the compensation period, and The second transistor is turned on during the data writing period.

11. The display device as claimed in claim 10, wherein, During the data writing period, the voltage difference between the two ends of the second capacitor is the difference between the data voltage and the third power supply.

12. The display device as claimed in claim 4, wherein, During the transmission period, the first capacitor and the second capacitor are connected in series between the second node and the third node.

13. The display device as claimed in claim 12, wherein, During the transmission period, the sixth and seventh transistors remain in the ON state, and the fourth transistor remains in the OFF state.

14. The display device as claimed in claim 1, wherein, The cathode of the light-emitting element is connected to a second power source.

15. A pixel unit, the pixel unit comprising a plurality of pixels, each pixel comprising: The light-emitting element includes a cathode connected to a second power source; The first transistor includes a first electrode, a second electrode connected to the anode of the light-emitting element, and a gate electrode; The third transistor includes a first electrode connected to a third power supply, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to a second scan line; The fourth transistor includes a first electrode, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the second scan line; A first capacitor is connected between the second electrode of the first transistor and the second electrode of the fourth transistor; The second transistor includes a first electrode connected to a data line, a second electrode, and a gate electrode connected to a first scan line; A second capacitor is connected between the second electrode of the second transistor and the second electrode of the fourth transistor; The sixth transistor includes a first electrode connected to the second electrode of the second transistor, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the first emitter control line; as well as The seventh transistor includes a first electrode connected to a first power supply, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a second emitter control line. The gate electrode of the first transistor is connected to the second electrode of the third transistor and the first electrode of the fourth transistor.

16. The pixel unit of claim 15, wherein each pixel further comprises: The fifth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the fourth power supply, and a gate electrode connected to the third scan line.

17. The pixel unit as claimed in claim 16, wherein, The first to the seventh transistors are P-type thin-film transistors, with a gate on-voltage having a logic low level and a gate off-voltage having a logic high level.

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