A dual-port SRAM memory cell and layout structure thereof

Abstract

The application provides a dual-port SRAM memory cell and a layout structure thereof, first and second NMOS and first and second PMOS; the first and second NMOS gates are connected with the first and second PMOS drains to form a word line; the first NMOS source is connected with a first bit line; the first PMOS source is connected with a second bit line; the second NMOS source is connected with a third bit line; the second PMOS source is connected with a fourth bit line; the first NMOS drain and the first PMOS gate are commonly connected to an input node of a latch; the second NMOS drain and the second PMOS gate are connected to an output node of the latch. The application significantly improves the symmetry of the dual-port SRAM memory cell, effectively improves the read-write speed and the read interference window by rearranging eight transistors without changing the length-width size of the conventional SRAM unit.

Description

Technical Field

[0001] This invention relates to the field of circuit design, and in particular to a dual-port SRAM memory cell and its layout structure. Background Technology

[0002] As computer speeds increase, the demands on CPU frequencies also rise. Dual-port SRAM, as the CPU's primary high-speed buffer, has a crucial read / write speed that directly impacts the CPU's actual operating speed.

[0003] Currently, the commonly used dual-port SRAM layout design in industry is as follows: Figure 1 As shown, it consists of two PMOS (PU1 and PU2), two NMOS (PD1 and PD2), and four NMOS (PG1-A, PG1-B, PG2-A, PG2-B). It has two word lines WL1 and WL2 and two sets of bit lines BL1, BL2 and BLB1, BLB2, which can realize the function of simultaneous reading. There is an R-gate series resistor between PG1-B (or PG2-A) and the output of the inverter. Due to the existence of this series resistor, the dual-port SRAM is asymmetrical in physical structure and has an inherent defect. The speed of reading "0" and reading "1" is different.

[0004] For example, when node Q = "0" and Qb = "1", the read current Iread at the BL1 terminal reaches Vss through PG1-A and PD1, while the read current Iread at the BLB2 terminal reaches Vss through PG1-B, R-Gate, PD2 gate, PU2 gate, and PD1. Due to the voltage division of the series resistor R-Gate, the read current Iread at the BLB2 terminal will be higher than the read current Iread at the BL1 terminal, thus causing the read speeds at the two terminals to be different.

[0005] Furthermore, because each memory node of a dual-port SRAM is connected to two NMOS transistors in parallel during read operations, the smaller the read interference window, the easier it is for functional failure to occur. For dual-port SRAM, due to the two NMOS transistors in parallel, the read interference window of an 8T SRAM (8-transfer transistor SRAM) is much smaller than that of a 6T SRAM (6-transfer transistor SRAM). Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a dual-port SRAM memory cell and its layout structure to solve the problem that the dual-port SRAM memory cell in the prior art has an asymmetrical structure due to the presence of series resistors, which leads to different read speeds at both ends and easy functional failure.

[0007] To achieve the above object and other related objects, the present application provides a dual-port SRAM memory cell, comprising at least: a first NMOS, a second NMOS, a first PMOS and a second PMOS; the gates of the first and second NMOSs are connected to the drains of the first and second PMOSs, and the drains of the first and second NMOSs are connected to a word line; the source of the first NMOS is connected to a first bit line; the source of the first PMOS is connected to a second bit line; the source of the second NMOS is connected to a third bit line; and the source of the second PMOS is connected to a fourth bit line.

[0008] The memory cell further comprises a latch having an input node Q and an output node Qb; the drain of the first NMOS and the gate of the first PMOS are connected to the input node Q of the latch; and the drain of the second NMOS and the gate of the second PMOS are connected to the output node Qb of the latch.

[0009] Preferably, the latch comprises a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor; the drain of the first pull-up transistor and the drain of the first pull-down transistor are connected to the gate of the second pull-up transistor and the gate of the second pull-down transistor, and a node therebetween is the input node Q of the latch; the gate of the first pull-up transistor and the gate of the first pull-down transistor are connected to the drain of the second pull-up transistor and the drain of the second pull-down transistor, and a node therebetween is the output node Qb of the latch; the sources of the first and second pull-up transistors are connected to a power supply voltage Vdd; and the source of the first pull-down transistor and the source of the second pull-down transistor are connected to ground.

[0010] Preferably, the first and second pull-up transistors are PMOS, and the first and second pull-down transistors are NMOS.

[0011] Preferably, in a read operation of the dual-port SRAM memory cell, the word line, the first bit line and the third bit line are connected to the power supply voltage Vdd, and the second bit line and the fourth bit line are connected to ground.

[0012] Preferably, in a write operation of the dual-port SRAM memory cell, the word line, the first bit line, the fourth bit line and the second bit line are connected to the power supply voltage Vdd, and the third bit line is connected to ground.

[0013] Preferably, in a write operation of the dual-port SRAM memory cell, the word line, the third bit line, the fourth bit line and the second bit line are connected to the power supply voltage Vdd, and the first bit line is connected to ground.

[0014] Preferably, in a sleep mode of the dual-port SRAM memory cell, the word line, the fourth bit line and the second bit line are connected to ground, and the first bit line and the third bit line are connected to the power supply voltage Vdd.

[0015] The application further provides a layout structure of a dual-port SRAM memory cell, comprising at least:

[0016] An active region layer comprising first to sixth active region patterns, which are distributed in sequence from left to right; the first active region pattern is shared by the first NMOS and the first pull-down tube; the second active region pattern is used for the first pull-up tube; the third active region pattern is used for the first PMOS; the fourth active region pattern is used for the second PMOS; the fifth active region pattern is used for the second pull-up tube; and the sixth active region pattern is shared by the second pull-down tube and the second NMOS;

[0017] A polysilicon layer covering the active region layer; the polysilicon layer comprises: a first polysilicon pattern across the first active region pattern as the gate of the first NMOS; a second polysilicon pattern across the first, second and fourth active region patterns, wherein the part of the second polysilicon pattern across the first active region pattern is used as the gate of the first pull-down tube; the part of the second polysilicon pattern across the second active region pattern is used as the gate of the first pull-up tube; and the part of the second polysilicon pattern across the fourth active region pattern is used as the gate of the second PMOS;

[0018] The polysilicon layer further comprises: a third polysilicon pattern across the third, fifth and sixth active region patterns; and a fourth polysilicon pattern across the sixth active region pattern; wherein the part of the third polysilicon pattern across the third active region pattern is used as the gate of the first PMOS; the part of the third polysilicon pattern across the fifth active region pattern is used as the gate of the second pull-up tube; the part of the third polysilicon pattern across the sixth active region pattern is used as the gate of the second pull-down tube; and the fourth polysilicon pattern across the sixth active region pattern is used as the gate of the second NMOS;

[0019] A contact hole layer is covered on the polysilicon layer; the contact hole layer comprises: first and second contact hole patterns distributed on the first active region pattern and on the upper and lower sides of the first polysilicon pattern; third and fourth contact hole patterns distributed on the first active region pattern and on the lower side of the second polysilicon pattern; fifth and sixth contact hole patterns distributed on the second active region pattern and on the upper and lower sides of the second polysilicon pattern; seventh and eighth contact hole patterns distributed on the third active region pattern and on the upper and lower sides of the third polysilicon pattern; ninth and tenth contact hole patterns distributed on the fourth active region pattern and on the upper and lower sides of the second polysilicon pattern; eleventh and twelfth contact hole patterns distributed on the fifth active region pattern and on the upper and lower sides of the third polysilicon pattern; thirteenth and fourteenth contact hole patterns distributed on the sixth active region pattern and on the upper side of the third polysilicon pattern; fifteenth and sixteenth contact hole patterns distributed on the sixth active region pattern and on the upper and lower sides of the fourth polysilicon pattern;

[0020] The contact hole layer further comprises: a seventeenth contact hole pattern located at one end of the first polysilicon pattern; an eighteenth contact hole pattern located at one end of the fourth polysilicon pattern;

[0021] A first metal layer is covered on the contact hole layer; the first metal layer comprises: a first metal pattern covering the seventeenth contact hole pattern; a second metal pattern covering the first contact hole pattern; a third metal pattern covering the second contact hole pattern and connecting the fifth contact hole pattern; a fourth metal pattern covering the third and fourth contact hole patterns; a fifth metal pattern covering the sixth contact hole pattern; a sixth metal pattern covering the seventh contact hole pattern; a seventh metal pattern covering the eighth and ninth contact hole patterns; an eighth metal pattern covering the tenth contact hole pattern; a ninth metal pattern covering the eleventh contact hole pattern; a tenth metal pattern covering the twelfth and fifteenth contact hole patterns; an eleventh metal pattern covering the thirteenth and fourteenth contact hole patterns; a twelfth metal pattern covering the sixteenth contact hole pattern; a thirteenth metal pattern covering the eighteenth contact hole pattern;

[0022] The first, seventh and thirteenth metal patterns connect the word line; the second metal pattern connects the first bit line; the fourth metal pattern and the eleventh metal pattern are grounded; the sixth metal pattern connects the second bit line; the eighth metal pattern connects the fourth bit line; the fifth metal pattern and the ninth metal pattern connect the power voltage Vdd; and the twelfth metal pattern connects the third bit line.

[0023] Preferably, the second polysilicon pattern and the third active region pattern partially overlap.

[0024] Preferably, the third polysilicon pattern partially overlaps both the fourth active area pattern.

[0025] Preferably, the third polysilicon pattern extends onto the second active area pattern near the end of the second active area pattern and partially overlaps the fifth contact hole pattern.

[0026] Preferably, the second polysilicon pattern extends onto the fifth active area pattern near the end of the fifth active area pattern and partially overlaps the twelfth contact hole pattern.

[0027] As described above, the dual-port SRAM memory cell and its layout structure of the present application have the following beneficial effects: the present application significantly improves the symmetry of the dual-port SRAM memory cell, effectively improves the read / write speed and read interference window, and is compatible with the conventional process, without changing the length and width size of the conventional SRAM cell. Since the dual-port SRAM is widely used in CPU level cache, the speed requirement is higher, so the present application has its practical significance. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 shows a circuit structure schematic diagram of a dual-port SRAM memory cell in the prior art;

[0029] Figure 2 shows a circuit structure schematic diagram of a dual-port SRAM memory cell of the present application;

[0030] Figure 3 shows a layout structure schematic diagram of a dual-port SRAM memory cell of the present application. DETAILED DESCRIPTION

[0031] The embodiments of the present application will be described herein below with reference to specific exemplary embodiments. Other advantages and effects of the present application, which can be easily understood by those skilled in the art, can be learned from the description of the present application. The present application can also be implemented or applied in other different specific embodiments, and various modifications or changes can be made to the details in the description based on different views and applications, without departing from the spirit of the present application.

[0032] Reference will now be made to the following Figures 2 to 3 It should be noted that the drawings provided in the present embodiment only schematically illustrate the basic concept of the present application, and the drawings only show the components related to the present application, rather than the number, shape and size of the components in actual implementation. The actual implementation of each component may be randomly changed in terms of shape, number and proportion, and the component layout pattern may also be more complex.

[0033] The present application provides a dual-port SRAM memory cell, asFigure 2 As shown, Figure 2 The double-port SRAM memory unit circuit structure of the present application is shown in the figure. The double-port SRAM memory unit of the present application at least includes:

[0034] A first NMOS and a second NMOS, and a first PMOS and a second PMOS; the gates of the first and second NMOSs are connected to the drains of the first and second PMOSs as the word line; the source of the first NMOS is connected to the first bit line BL1; the source of the first PMOS is connected to the second bit line; the source of the second NMOS is connected to the third bit line; and the source of the second PMOS is connected to the fourth bit line.

[0035] A latch with an input node Q and an output node Qb; the drain of the first NMOS and the gate of the first PMOS are connected to the input node Q of the latch; and the drain of the second NMOS and the gate of the second PMOS are connected to the output node Qb of the latch.

[0036] Referring to Figure 2 The double-port SRAM memory unit in the embodiment includes a first NMOS (PG1-A), a second NMOS (PG2-A), a first PMOS (PG1-B), and a second PMOS (PG2-B); the gates of the first and second NMOSs are connected to the drains of the first and second PMOSs as the word line WL; the source of the first NMOS (PG1-A) is connected to the first bit line BL1; the source of the first PMOS (PG1-B) is connected to the second bit line BLB2; the source of the second NMOS (PG2-A) is connected to the third bit line BLB1; and the source of the second PMOS (PG2-B) is connected to the fourth bit line BL2.

[0037] A latch with an input node Q and an output node Qb; the drain of the first NMOS (PG1-A) and the gate of the first PMOS (PG1-B) are connected to the input node Q of the latch; and the drain of the second NMOS (PG2-A) and the gate of the second PMOS (PG2-B) are connected to the output node Qb of the latch.

[0038] As Figure 2As shown, the latch in the embodiment further includes a first pull-up tube (PU1), a second pull-up tube (PU2) and a first pull-down tube (PD1), a second pull-down tube (PD2); wherein the drain of the first pull-up tube (PU1), the drain of the first pull-down tube (PD1) are connected with the gate of the second pull-up tube (PU2), the gate of the second pull-down tube (PD2), and the node is as the input node Q of the latch; the gate of the first pull-up tube (PU1), the gate of the first pull-down tube (PD1) are connected with the drain of the second pull-up tube (PU2), the drain of the second pull-down tube (PD2), and the node is as the output node Qb of the latch; the source of the first pull-up tube (PU1), the source of the second pull-up tube (PU2) are commonly connected with a power supply voltage Vdd; the source of the first pull-down tube (PD1), the source of the second pull-down tube (PD2) are grounded Vss.

[0039] The first pull-up tube (PU1), the second pull-up tube (PU2) in the embodiment are PMOS, and the first pull-down tube (PD1), the second pull-down tube (PD2) are NMOS.

[0040] The dual-port SRAM storage unit in the embodiment under the read operation, the word line WL, the first bit line BL1, the third bit line BLB1 are commonly connected with the power supply voltage Vdd; the second bit line BLB2 and the fourth bit line BL2 are grounded Vss.

[0041] The dual-port SRAM storage unit in the embodiment under the write operation, the word line WL, the first bit line BL1, the fourth bit line BL2 and the second bit line BLB2 are connected with the power supply voltage Vdd; the third bit line BLB1 is grounded Vss.

[0042] The dual-port SRAM storage unit in the embodiment under the write operation, the word line WL, the third bit line BLB1, the fourth bit line BL2 and the second bit line BLB2 are connected with the power supply voltage Vdd; the first bit line BL1 is grounded Vss.

[0043] The dual-port storage unit in the embodiment under the sleep mode (low power consumption mode), the word line WL, the fourth bit line BL2, the second bit line BLB2 are grounded Vss; the first bit line BL1, the third bit line BLB1 are connected with the power supply voltage Vdd.

[0044] The application also provides a layout structure of the dual-port SRAM memory cell, comprising: an active area layer comprising first to sixth active area patterns, which are distributed in sequence from left to right; the first NMOS and the first pull-down tube share the first active area pattern; the second active area pattern is used for the first pull-up tube; the third active area pattern is used for the first PMOS; the fourth active area pattern is used for the second PMOS; the fifth active area pattern is used for the second pull-up tube; and the second pull-down tube and the second NMOS share the sixth active area pattern;

[0045] The layout structure of the dual-port SRAM memory cell further comprises: a polysilicon layer covering the active area layer; the polysilicon layer comprises: a first polysilicon pattern across the first active area pattern as the gate of the first NMOS; a second polysilicon pattern across the first, second and fourth active area patterns, wherein the part of the second polysilicon pattern across the first active area pattern is used as the gate of the first pull-down tube; the part of the second polysilicon pattern across the second active area pattern is used as the gate of the first pull-up tube; and the part of the second polysilicon pattern across the fourth active area pattern is used as the gate of the second PMOS; the polysilicon layer further comprises: a third polysilicon pattern across the third, fifth and sixth active area patterns; and a fourth polysilicon pattern across the sixth active area pattern; wherein the part of the third polysilicon pattern across the third active area pattern is used as the gate of the first PMOS; the part of the third polysilicon pattern across the fifth active area pattern is used as the gate of the second pull-up tube; the part of the third polysilicon pattern across the sixth active area pattern is used as the gate of the second pull-down tube; and the fourth polysilicon pattern across the sixth active area pattern is used as the gate of the second NMOS;

[0046] The layout structure of the dual-port SRAM memory cell further comprises a contact hole layer covering the polysilicon layer; the contact hole layer comprises: first and second contact hole patterns distributed on the first active area pattern and on both sides of the first polysilicon pattern; third and fourth contact hole patterns distributed on the first active area pattern and on the lower side of the second polysilicon pattern; fifth and sixth contact hole patterns distributed on the second active area pattern and on both sides of the second polysilicon pattern; seventh and eighth contact hole patterns distributed on the third active area pattern and on both sides of the third polysilicon pattern; ninth and tenth contact hole patterns distributed on the fourth active area pattern and on both sides of the second polysilicon pattern; eleventh and twelfth contact hole patterns distributed on the fifth active area pattern and on both sides of the third polysilicon pattern; thirteenth and fourteenth contact hole patterns distributed on the sixth active area pattern and on both sides of the fourth polysilicon pattern above the sixth active area pattern;

[0047] The contact hole layer further comprises: a seventeenth contact hole pattern located at one end of the first polysilicon pattern; an eighteenth contact hole pattern located at one end of the fourth polysilicon pattern;

[0048] The layout structure of the dual-port SRAM memory cell further comprises a first metal layer covering the contact hole layer; the first metal layer comprises: a first metal pattern covering the seventeenth contact hole pattern; a second metal pattern covering the first contact hole pattern; a third metal pattern covering the second and fifth contact hole patterns; a fourth metal pattern covering the third and fourth contact hole patterns; a fifth metal pattern covering the sixth contact hole pattern; a sixth metal pattern covering the seventh contact hole pattern; a seventh metal pattern covering the eighth and ninth contact hole patterns; an eighth metal pattern covering the tenth contact hole pattern; a ninth metal pattern covering the eleventh contact hole pattern; a tenth metal pattern covering the twelfth and fifteenth contact hole patterns; an eleventh metal pattern covering the thirteenth and fourteenth contact hole patterns; a twelfth metal pattern covering the sixteenth contact hole pattern; and a thirteenth metal pattern covering the eighteenth contact hole pattern;

[0049] The first, seventh, and thirteenth metal patterns are connected to the word line; the second metal pattern is connected to the first bit line; the fourth metal pattern and the eleventh metal pattern are grounded; the sixth metal pattern is connected to the second bit line; the eighth metal pattern is connected to the fourth bit line; the ninth metal pattern is connected to the power voltage Vdd; and the twelfth metal pattern is connected to the third bit line.

[0050] As shown in Figure 3 ​Figure 3 A schematic diagram of a layout structure of a dual-port SRAM memory cell according to the present application is shown. According to the present application, the layout structure of the dual-port SRAM memory cell of the embodiment includes: an active region layer including first to sixth active region patterns, which are distributed in sequence from left to right with intervals; the first active region pattern 01, the second active region pattern 02, the third active region pattern 03, the fourth active region pattern 04, the fifth active region pattern 05, and the sixth active region pattern 06 are arranged in sequence from left to right with intervals.

[0051] The first NMOS (PG1-A) and the first pull-down tube (PD1) share the first active region pattern 01; the second active region pattern 02 is used to form the first pull-up tube (PU1); the third active region pattern 03 is used to form the first PMOS (PG1-B); the fourth active region pattern 04 is used to form the second PMOS (PG2-B); the fifth active region pattern 05 is used to form the second pull-up tube (PU2); the second pull-down tube (PD2) and the second NMOS (PG2-A) share the sixth active region pattern 06.

[0052] In the embodiment, the layout structure of the dual-port SRAM memory cell further comprises: a polysilicon layer overlaid on the active region layer; the polysilicon layer comprises: a first polysilicon pattern A across the first active region pattern 01 as the gate of the first NMOS (PG1-A); a second polysilicon pattern B across the first active region pattern 01, the second active region pattern 02, and the fourth active region pattern 04, wherein the part of the second polysilicon pattern B across the first active region pattern 01 serves as the gate of the first pull-down transistor (PD1); the part of the second polysilicon pattern B across the second active region pattern 02 serves as the gate of the first pull-up transistor (PU1); the part of the second polysilicon pattern B across the fourth active region pattern 04 serves as the gate of the second PMOS (PG2-B); the polysilicon layer further comprises: a third polysilicon pattern C across the third active region pattern 03, the fifth active region pattern 05, and the sixth active region pattern 06; a fourth polysilicon pattern D across the sixth active region pattern 06; wherein the part of the third polysilicon pattern C across the third active region pattern 03 serves as the gate of the first PMOS (PG1-B); the part of the third polysilicon pattern C across the fifth active region pattern 05 serves as the gate of the second pull-up transistor (PU2); the part of the third polysilicon pattern C across the sixth active region pattern 06 serves as the gate of the second pull-down transistor (PD2); and the fourth polysilicon pattern D across the sixth active region pattern 06 serves as the gate of the second NMOS (PG2-A).

[0053] In the embodiment, the layout structure of the dual-port SRAM memory cell further comprises a contact hole layer covering the polysilicon layer, wherein the contact hole layer comprises: a first contact hole pattern C1 and a second contact hole pattern C2 distributed on the first active region pattern 01 and on both sides of the first polysilicon pattern A; a third contact hole pattern C3 and a fourth contact hole pattern C4 distributed on the first active region pattern 01 and on the lower side of the second polysilicon pattern B; a fifth contact hole pattern C5 and a sixth contact hole pattern C6 distributed on the second active region pattern 02 and on both sides of the second polysilicon pattern B; a seventh contact hole pattern C7 and an eighth contact hole pattern C8 distributed on the third active region pattern 03 and on both sides of the third polysilicon pattern C; a ninth contact hole pattern C9 and a tenth contact hole pattern C10 distributed on the fourth active region pattern 04 and on both sides of the second polysilicon pattern B; an eleventh contact hole C11 and a twelfth contact hole pattern C12 distributed on the fifth active region pattern 05 and on both sides of the third polysilicon pattern C; a thirteenth contact hole pattern C13 and a fourteenth contact hole pattern C14 distributed on the sixth active region pattern 06 and above the third polysilicon pattern C; a fifteenth contact hole pattern C15 and a sixteenth contact hole pattern C16 distributed on the sixth active region pattern 06 and on both sides of the fourth polysilicon pattern D.

[0054] In the embodiment, the contact hole layer further comprises: a seventeenth contact hole pattern C17 located at one end of the first polysilicon pattern A; and an eighteenth contact hole pattern C18 located at one end of the fourth polysilicon pattern D.

[0055] In this embodiment, the layout structure of the dual-port SRAM memory cell further includes: a first metal layer covering the contact hole layer; the first metal layer includes: a first metal pattern M1 covering the seventeenth contact hole pattern C17; a second metal pattern M2 covering the first contact hole pattern C1; a third metal pattern M3 covering the second contact hole pattern C2 and connecting to the fifth contact hole pattern C5; a fourth metal pattern M4 covering the third contact hole pattern C3 and the fourth contact hole pattern C4; a fifth metal pattern M5 covering the sixth contact hole pattern C6; and a fifth metal pattern M5 covering the seventh contact hole. The sixth metal pattern M6 of pattern C7; the seventh metal pattern M7 covering the eighth contact hole pattern C8 and the ninth contact hole pattern C9; the eighth metal pattern M8 covering the tenth contact hole pattern C10; the ninth metal pattern M9 covering the eleventh contact hole pattern C11; the tenth metal pattern M10 covering the twelfth and fifteenth contact hole patterns; the eleventh metal pattern M11 covering the thirteenth and fourteenth contact hole patterns; the twelfth metal pattern M12 covering the sixteenth contact hole pattern C16; and the thirteenth metal pattern M13 covering the eighteenth contact hole pattern C18.

[0056] In the layout structure of this embodiment, the first metal graphic M1, the seventh metal graphic M7, and the thirteenth metal graphic M13 are connected to the word line WL; the second metal graphic M2 is connected to the first bit line BL1; the fourth metal graphic M4 and the eleventh metal graphic M11 are grounded to Vss; the sixth metal graphic M6 is connected to the second bit line BLB2; the eighth metal graphic M8 is connected to the fourth bit line BL2; the fifth metal graphic M5 and the ninth metal graphic M9 are connected to the power supply voltage Vdd; and the twelfth metal graphic M12 is connected to the third bit line BLB1.

[0057] Furthermore, in this embodiment, the second polysilicon pattern B and the third active region pattern 03 partially overlap. For example... Figure 3 As shown, while the second polysilicon pattern B spans the first, second, and fourth active region patterns, since the active region pattern 03 is located between the second and fourth active region patterns, a portion of the second polysilicon pattern B overlaps with one end of the third active region pattern. Furthermore, in this embodiment, the third polysilicon pattern and the fourth active region pattern partially overlap. While the third polysilicon pattern C spans the third active region pattern 03, the fifth active region pattern 05, and the sixth active region pattern 06, since the fourth active region pattern 04 is located between the third and fifth active region patterns, one end of the fourth active region pattern 04 partially overlaps with the third polysilicon pattern C.

[0058] Further, the third polysilicon pattern C in the embodiment extends to the second active area pattern 02 near the end of the second active area pattern 02 and partially overlaps the fifth contact hole pattern C5.

[0059] The second polysilicon pattern B in the embodiment extends to the fifth active area pattern 05 near the end of the fifth active area pattern 05 and partially overlaps the twelfth contact hole pattern C12.

[0060] With Figure 1 Compared with the traditional structure in the prior art, the first bit line BL1 and the third bit line BLB1 in the application are completely symmetrical, no information of the transmission node is transmitted through the gate as a connecting line, and the voltage drop is avoided; the second bit line BLB2 and the fourth bit line BL2 are also completely symmetrical, but the first PMOS (PG1-B) and the second PMOS (PG2-B) are composed of two PMOSs, and only one word line WL is used as the drain of the first PMOS (PG1-B) and the second PMOS (PG2-B), the gate of the two PMOSs is controlled by the node Q, so that the read interference window is increased; the first PMOS (PG1-B) and the second PMOS (PG2-B) share the gate with the first and second pull-up tubes, and the voltage drop caused by providing the node storage information through the gate connecting line is abandoned, so that the whole memory cell is completely symmetrical; meanwhile, the problem of mismatch of the bit line is removed, the active area size of the first and second PMOSs depends on the demand of the read current, since the read current of the channel where the first and second NMOSs are located is limited by the linear current of the two pull-down tubes, and the read current of the channel where the first and second PMOSs are located is determined by the saturation current, therefore, the active area size of the first and second PMOSs will not be greater than that of the first and second NMOSs.

[0061] In summary, the application significantly improves the symmetry of the dual-port SRAM memory cell, effectively improves the read and write speed and the read interference window, and is compatible with the traditional process without changing the length and width size of the traditional SRAM memory cell. Since the dual-port SRAM memory cell is widely used in CPU level cache, the speed requirement is higher, so the application has practical significance in reducing the voltage drop caused by using the gate as a connecting line. Therefore, the application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0062] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A dual-port SRAM memory cell, characterized in that, At least including: First and second NMOS and first and second PMOS; the gates of the first and second NMOS and the drains of the first and second PMOS are connected to the word line together; The source of the first NMOS is connected to the first bit line; the source of the first PMOS is connected to the second bit line; the source of the second NMOS is connected to the third bit line; and the source of the second PMOS is connected to the fourth bit line. A latch is provided with an input node Q and an output node Qb; the drain of the first NMOS and the gate of the first PMOS are connected to the input node Q of the latch; the drain of the second NMOS and the gate of the second PMOS are connected to the output node Qb of the latch.

2. The dual-port SRAM memory cell according to claim 1, characterized in that: The latch includes a first and a second pull-up transistor and a first and a second pull-down transistor; wherein the drain of the first pull-up transistor and the drain of the first pull-down transistor are interconnected with the gate of the second pull-up transistor and the gate of the second pull-down transistor, and the node serves as the input node Q of the latch; the gate of the first pull-up transistor and the gate of the first pull-down transistor are interconnected with the drain of the second pull-up transistor and the drain of the second pull-down transistor, and the node serves as the output node Qb of the latch; the sources of the first and second pull-up transistors are connected to the power supply voltage Vdd; the sources of the first and second pull-down transistors are grounded.

3. The dual-port SRAM memory cell according to claim 2, characterized in that: The first and second pull-up transistors are PMOS; the first and second pull-down transistors are NMOS.

4. The dual-port SRAM memory cell according to claim 3, characterized in that: In the read operation, the word line, the first bit line, and the third bit line of the dual-port SRAM memory cell are all connected to the power supply voltage Vdd; the second bit line and the fourth bit line are grounded.

5. The dual-port SRAM memory cell according to claim 3, characterized in that: During a write operation, the word line, the first bit line, the fourth bit line, and the second bit line of the dual-port SRAM memory cell are connected to the power supply voltage Vdd; the third bit line is grounded.

6. The dual-port SRAM memory cell according to claim 3, characterized in that: During a write operation, the word line, the third bit line, the fourth bit line, and the second bit line of the dual-port SRAM memory cell are connected to the power supply voltage Vdd; the first bit line is grounded.

7. The dual-port SRAM memory cell according to claim 3, characterized in that: In sleep mode, the word line, the fourth bit line, and the second bit line of the dual-port SRAM memory cell are grounded; the first bit line and the third bit line are connected to the power supply voltage Vdd.

8. A layout structure based on the dual-port SRAM memory cell as described in claim 2, characterized in that, At least including: An active region layer containing first to sixth active region patterns, the first to sixth active region patterns being distributed alternately from left to right; the first NMOS and the first pull-down transistor share the first active region pattern; the second active region pattern is used for the first pull-up transistor; the third active region pattern is used for the first PMOS; the fourth active region pattern is used for the second PMOS; the fifth active region pattern is used for the second pull-up transistor; the second pull-down transistor and the second NMOS share the sixth active region pattern; A polysilicon layer covering the active region layer; the polysilicon layer includes: a first polysilicon pattern spanning the first active region pattern as the gate of the first NMOS; a second polysilicon pattern spanning the first, second, and fourth active region patterns, wherein the portion of the second polysilicon pattern spanning the first active region pattern serves as the gate of the first pull-down transistor; the portion of the second polysilicon pattern spanning the second active region pattern serves as the gate of the first pull-up transistor; and the portion of the second polysilicon pattern spanning the fourth active region pattern serves as the gate of the second PMOS. The polysilicon layer further includes: a third polysilicon pattern spanning the third, fifth, and sixth active region patterns; a fourth polysilicon pattern spanning the sixth active region pattern; wherein the portion of the third polysilicon pattern spanning the third active region pattern serves as the gate of the first PMOS; the portion of the third polysilicon pattern spanning the fifth active region pattern serves as the gate of the second pull-up transistor; the portion of the third polysilicon pattern spanning the sixth active region pattern serves as the gate of the second pull-down transistor; and the fourth polysilicon pattern spanning the sixth active region pattern serves as the gate of the second NMOS. A contact hole layer covering the polysilicon layer; the contact hole layer includes: first and second contact hole patterns distributed on the first active region pattern and on the upper and lower sides of the first polysilicon pattern; third and fourth contact hole patterns distributed on the first active region pattern and on the lower side of the second polysilicon pattern; fifth and sixth contact hole patterns distributed on the second active region pattern and on the upper and lower sides of the second polysilicon pattern; seventh and eighth contact hole patterns distributed on the third active region pattern and on the upper and lower sides of the third polysilicon pattern; ninth and tenth contact hole patterns distributed on the fourth active region pattern and on the upper and lower sides of the second polysilicon pattern; eleventh and twelfth contact hole patterns distributed on the fifth active region pattern and on the upper and lower sides of the third polysilicon pattern; thirteenth and fourteenth contact hole patterns distributed on the sixth active region pattern and above the third polysilicon pattern; and fifteenth and sixteenth contact hole patterns distributed on the sixth active region pattern and on the upper and lower sides of the fourth polysilicon pattern. The contact hole layer further includes: a seventeenth contact hole pattern located at one end of the first polysilicon pattern; and an eighteenth contact hole pattern located at one end of the fourth polysilicon pattern. A first metal layer covering the contact hole layer; the first metal layer comprising: a first metal pattern covering the seventeenth contact hole pattern; a second metal pattern covering the first contact hole pattern; a third metal pattern covering the second contact hole pattern and connecting to the fifth contact hole pattern; a fourth metal pattern covering the third and fourth contact hole patterns; a fifth metal pattern covering the sixth contact hole pattern; a sixth metal pattern covering the seventh contact hole pattern; a seventh metal pattern covering the eighth and ninth contact hole patterns; an eighth metal pattern covering the tenth contact hole pattern; a ninth metal pattern covering the eleventh contact hole pattern; a tenth metal pattern covering the twelfth and fifteenth contact hole patterns; an eleventh metal pattern covering the thirteenth and fourteenth contact hole patterns; a twelfth metal pattern covering the sixteenth contact hole pattern; and a thirteenth metal pattern covering the eighteenth contact hole pattern. The first, seventh, and thirteenth metal patterns are connected to the word lines; the second metal pattern is connected to the first bit line; the fourth and eleventh metal patterns are grounded; the sixth metal pattern is connected to the second bit line; the eighth metal pattern is connected to the fourth bit line; the fifth and ninth metal patterns are connected to the power supply voltage Vdd; and the twelfth metal pattern is connected to the third bit line.

9. The layout structure of the dual-port SRAM memory cell according to claim 8, characterized in that: The second polysilicon pattern and the third active region pattern partially overlap.

10. The layout structure of the dual-port SRAM memory cell according to claim 8, characterized in that: The third polysilicon pattern and the fourth active region pattern partially overlap.

11. The layout structure of the dual-port SRAM memory cell according to claim 8, characterized in that: The third polysilicon pattern extends from the end near the second active region pattern onto the second active region pattern and partially overlaps with the fifth contact hole pattern.

12. The layout structure of the dual-port SRAM memory cell according to claim 8, characterized in that: The second polysilicon pattern extends from the end near the fifth active region pattern onto the fifth active region pattern and partially overlaps with the twelfth contact hole pattern.

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