Semiconductor element with inclined isolation layer and preparation method thereof

Abstract

The present disclosure provides a semiconductor device having multiple inclined isolation layers and a method for manufacturing the same. The semiconductor device includes a substrate, two conductive studs, a first set of inclined isolation layers, and a second set of inclined isolation layers; the two conductive studs are located on the substrate and extend along a vertical axis; the first set of inclined isolation layers are parallel to each other and located between the two conductive studs; the second set of inclined isolation layers are parallel to each other and located between the two conductive studs. The first set of inclined isolation layers extends along a first direction that is inclined relative to the vertical axis; the second set of inclined isolation layers extends along a second direction that is inclined relative to the vertical axis; and the first direction intersects the second direction.

Description

Technical Field

[0001] This disclosure claims priority to and the benefit of U.S. regular application No. 17 / 031,119, filed on September 24, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor element and a method for manufacturing the same, and more particularly to a semiconductor element having multiple inclined isolation layers and a method for manufacturing the same. Background Art

[0003] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor device sizes are steadily shrinking to meet the increasing demand for computing power. However, this process of shrinking size introduces various challenges, which continue to increase in number and complexity. Consequently, achieving improvements in quality, yield, performance, and reliability, while also reducing complexity, remains a constant challenge.

[0004] The above description of “prior art” is merely to provide background technology, and does not admit that the above description of “prior art” reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the Invention

[0005] One embodiment of the present disclosure provides a semiconductor element, comprising a substrate; two conductive studs located on the substrate and extending along a vertical axis; a first set of inclined isolation layers parallel to each other and located between the two conductive studs; and a second set of inclined isolation layers parallel to each other and located between the two conductive studs; wherein the first set of inclined isolation layers extends along a first direction, which is inclined relative to the vertical axis; the second set of inclined isolation layers extends along a second direction, which is inclined relative to the vertical axis; and the first direction intersects the second direction.

[0006] In some embodiments, the semiconductor element further includes a first isolation layer located on the substrate, wherein the two conductive plugs are arranged along the first isolation layer, the first group of inclined isolation layers and the second group of inclined isolation layers are located in the first isolation layer, and the first group of inclined isolation layers and the second group of inclined isolation layers contain a material that is different from the material of the first isolation layer.

[0007] In some embodiments, the first set of sloped isolation layers and the second set of sloped isolation layers include a material having a dielectric constant lower than a dielectric constant of the material of the first isolation layer.

[0008] In some embodiments, the first set of sloped isolation layers and the second set of sloped isolation layers are porous.

[0009] In some embodiments, the porosity of each of the first set of sloped isolation layers and the second set of sloped isolation layers is between about 10% and about 80%.

[0010] In some embodiments, the first set of inclined isolation layers and the second set of inclined isolation layers comprise a material having a thermal expansion coefficient and a Young's modulus less than about 20 ppm / ° C. and less than about 15 GPa.

[0011] In some embodiments, the semiconductor device further includes a pad layer located on the two conductive studs, the first set of inclined isolation layers, and the second set of inclined isolation layers.

[0012] In some embodiments, an angle between the first direction and the vertical axis is between about 10 degrees and about 80 degrees.

[0013] In some embodiments, an angle between the second direction and the vertical axis is between approximately -10 degrees and approximately -80 degrees.

[0014] In some embodiments, an angle between the first direction and the vertical axis is different from an angle between the second direction and the vertical axis.

[0015] In some embodiments, an angle between the first direction and the vertical axis is opposite to an angle between the second direction and the vertical axis.

[0016] In some embodiments, each lower surface of the first set of inclined isolation layers and each lower surface of the second set of inclined isolation layers are substantially coplanar with a lower surface of the first isolation layer.

[0017] In some embodiments, each lowest point of the first set of inclined isolation layers and each lowest point of the second set of inclined isolation layers are located at a plane on a lower surface of the first isolation layer.

[0018] Another embodiment of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming a first isolation layer on the substrate; forming two conductive studs along the first isolation layer; forming a first group of inclined grooves along the first isolation layer between the two conductive studs; forming a second group of inclined grooves along the first isolation layer between the two conductive studs; forming a first group of inclined isolation layers in the first group of inclined grooves along a first direction; and forming a second group of inclined isolation layers in the second group of inclined grooves along a second direction; wherein the first group of inclined isolation layers and the second group of inclined isolation layers are formed simultaneously, and the first direction intersects the second direction.

[0019] In some embodiments, the first set of sloped isolation layers and the second set of sloped isolation layers include a material that is different from a material of the first isolation layer.

[0020] In some embodiments, the first set of sloped isolation layers and the second set of sloped isolation layers include a material having a dielectric constant lower than a dielectric constant of the material of the first isolation layer.

[0021] In some embodiments, the step of forming the first set of inclined grooves includes: forming a first hard mask layer on the first isolation layer; forming a plurality of first hard mask openings along the first hard mask layer; and using the first hard mask layer and the plurality of first hard mask openings as a plurality of pattern guides to perform a first inclined etching process on the first isolation layer to form the first set of inclined grooves.

[0022] In some embodiments, the first hard mask layer includes the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or a carbon film.

[0023] In some embodiments, the step of forming the second set of inclined isolation layers includes: using the first hard mask layer and the multiple first hard mask openings as multiple pattern guides to perform a second inclined etching process on the first isolation layer to form the second set of inclined grooves, and an incident angle of the first inclined etching process is opposite to an incident angle of the second inclined etching process.

[0024] In some embodiments, the step of forming the first set of inclined isolation layers and the step of forming the second set of inclined isolation layers include: forming a layer of energy-removable compound in the first set of inclined grooves and the second set of inclined grooves, wherein the layer of energy-removable compound includes a base material and a decomposable porogen material; and performing an energy treatment to convert the layer of energy-removable compound into the first set of inclined isolation layers and the second set of inclined isolation layers.

[0025] Due to the design of the semiconductor device disclosed herein, the first set of inclined isolation layers and the second set of inclined isolation layers can be used to adjust the dielectric constant between the plurality of conductive studs. Consequently, the parasitic capacitance between the plurality of conductive studs can be reduced, thereby improving the performance of the semiconductor device. Furthermore, the first set of inclined isolation layers and the second set of isolation layers can increase the elasticity of the first isolation layer, which can improve the resistance of the semiconductor device's bonding strength during a bonding process or a wiring process.

[0026] The above has provided a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. Those skilled in the art of the present disclosure should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] A more complete understanding of the disclosure of the present invention may be obtained by referring to the embodiments and claims in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.

[0028] Figure 1 Schematic cross-sectional views of semiconductor devices illustrating some embodiments of the present disclosure.

[0029] Figures 2 to 9 Schematic cross-sectional views of various semiconductor devices illustrating some embodiments of the present disclosure.

[0030] Figure 10 A schematic flow chart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0031] Figures 11 to 19 A schematic cross-sectional view illustrating the process of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0032] Figures 20 to 22 A schematic cross-sectional view illustrating the process of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0033] Description of reference numerals:

[0034] 1A: Semiconductor components

[0035] 1B: Semiconductor components

[0036] 1C: Semiconductor components

[0037] 1D: Semiconductor components

[0038] 1E: Semiconductor components

[0039] 1F: Semiconductor components

[0040] 1G: Semiconductor components

[0041] 1H: semiconductor components

[0042] 1I: Semiconductor components

[0043] 10: Preparation method

[0044] 101: Base

[0045] 103: Lower isolation layer

[0046] 105: Lower conductive layer

[0047] 107: First isolation layer

[0048] 107BS: bottom surface

[0049] 107TS: Top surface

[0050] 109: cushion

[0051] 201-1: Conductive bolt

[0052] 201-3: Conductive bolt

[0053] 201-5: Conductive bolt

[0054] 201-7: Conductive bolt

[0055] 301: The first set of inclined isolation layers

[0056] 301BP: Lowest point

[0057] 301BS: bottom surface

[0058] 301SW: Sidewall

[0059] 301TS: upper surface

[0060] 303: The second set of inclined isolation layers

[0061] 303BP: Lowest point

[0062] 303BS: bottom surface

[0063] 303SW: Sidewall

[0064] 303TS: upper surface

[0065] 401: First hard mask layer

[0066] 403: First mask layer

[0067] 405: First hard mask opening

[0068] 407: The first set of inclined grooves

[0069] 407BS: bottom surface

[0070] 407SW: Sidewall

[0071] 409: The second set of inclined grooves

[0072] 409BS: bottom surface

[0073] 409SW: Sidewall

[0074] 411: First isolation material

[0075] 413: Energy Removable Complex

[0076] 501: First inclined etching process

[0077] 503: Second inclined etching process

[0078] E1: First Direction

[0079] E2: Second Direction

[0080] H1: Height

[0081] S11: Steps

[0082] S13: Steps

[0083] S15: Steps

[0084] S17: Steps

[0085] S19: Steps

[0086] S21: Steps

[0087] W1: width

[0088] W2: width

[0089] W3: Width

[0090] Z: vertical axis

[0091] α: angle

[0092] β: angle

[0093] γ: angle of incidence

[0094] γ': acute angle

[0095] γ”: acute angle

[0096] δ: angle of incidence

[0097] δ': acute angle

[0098] δ”: acute angle DETAILED DESCRIPTION

[0099] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0100] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0101] It should be understood that when forming a component on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0102] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0103] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variances that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, terms such as substantially the same, substantially equal, or substantially planar may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable variance, which may occur, for example, due to a manufacturing process.

[0104] In the present disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor devices.

[0105] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0106] Figure 1 A cross-sectional view of a semiconductor device 1A illustrating some embodiments of the present disclosure is shown in FIG. Figure 1In some embodiments, the substrate 101 may be a bulk semiconductor substrate. For example, the bulk semiconductor substrate may include an elemental semiconductor or a compound semiconductor. The elemental semiconductor may be silicon or germanium. The compound semiconductor may be silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors.

[0107] In some embodiments, substrate 101 may comprise a semiconductor-on-insulator (SIO) structure composed, from bottom to top, of a handling substrate, an isolation layer, and a topmost semiconductor layer. The materials comprising the handling substrate and the topmost semiconductor layer are similar to those of the bulk semiconductor substrate described above. The isolation layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. The isolation layer may have a thickness ranging from approximately 10 nm to 200 nm.

[0108] The substrate 101 may also include dielectrics, isolation layers, or conductive features formed on the bulk semiconductor substrate or the semiconductor-on-insulator structure. For example, the dielectrics or isolation layers may include a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, tetraethylorthosilicate oxide, phosphosilicate glass, borophosphosilicate glass, fluorinated silica glass, carbon doped silicon oxide, amorphous fluorinated carbon, or a combination thereof. The conductive features may be conductive lines, conductive vias, conductive contacts, or the like. The dielectrics or isolation layers may serve as an insulator that supports and electrically isolates the conductive features.

[0109] In some embodiments, a plurality of device elements (not shown) may be disposed in the substrate 101. For example, the plurality of device elements may be bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOS FETs), diodes, system large-scale integration (SLI), flash memories, dynamic random-access memories (DRAMs), static random-access memories (SRAMs), electrically erasable programmable read-only memories (EPROMs), image sensors, micro-electromechanical systems (MEMSs), active components, or passive components. The plurality of device elements may be electrically isolated from adjacent device elements by a plurality of isolation structures, such as shallow trench isolation (STIs).

[0110] Please refer to Figure 1 The lower isolation layer 103 may be disposed on the substrate 101. In some embodiments, the lower isolation layer 103 may include the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, flowable oxide, tonn silazen, undoped silica glass, borosilica glass, phosphosilicate glass, borophosphosilicate glass, plasma-enhanced tetra-ethylorthosilicate, fluoride silicate glass, carbon-doped silicon oxide, organosilicate glass, a low-k dielectric material, or a combination thereof. The low-k dielectric material may have a dielectric constant less than 3.0 or even less than 2.5.

[0111] Please refer to Figure 1The lower conductive layer 105 may be disposed in the lower isolation layer 103. For example, the lower conductive layer 105 includes copper, aluminum, titanium, tungsten, or the like, or a combination thereof. The lower conductive layer 105 may be electrically coupled to the plurality of device elements.

[0112] Please refer to Figure 1 , the first isolation layer 107 may be disposed on the lower isolation layer 103. In some embodiments, the first isolation layer 107 may include the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, flowing oxide, silazane, undoped silica glass, borosilica glass, phosphosilicate glass, borophosphosilicate glass, plasma-assisted tetrasilicon dioxide, fluorosilicate glass, carbon-doped silicon oxide, organosilicate glass, low-k dielectric material, or a combination thereof.

[0113] In some embodiments, the first isolation layer 107 may include the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxide nitride, polyimide, polybenzoxazole, phosphosilicate glass, undoped silicate glass, or fluorosilicate glass. The first isolation layer 107 may be considered a passivation layer.

[0114] Please refer to Figure 1 , the conductive plugs 201-1 and 201-3 may be vertically disposed along the first isolation layer 107 and the lower isolation layer 103. That is, the conductive plugs 201-1 and 201-3 may extend along the vertical axis Z. The lower portions of the sidewalls of the conductive plugs 201-1 and 201-3 may be attached to the lower conductive layer 105. In other words, the conductive plugs 201-1 and 201-3 and the lower conductive layer 105 may be electrically connected. The upper surfaces of the conductive plugs 201-1 and 201-3 may be substantially coplanar with the upper surfaces 107TS of the first isolation layer 107. For example, the conductive plugs 201-1 and 201-3 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

[0115] Please refer to Figure 1The first set of inclined isolation layers 301 may be disposed in the first isolation layer 107 and between the conductive studs 201-1 and 201-3. Each upper surface 301TS of the first set of inclined isolation layers 301 may be substantially coplanar with the upper surface 107TS of the first isolation layer 107. Each lower surface 301BS of the first set of inclined isolation layers 301 may be substantially coplanar with the lower surface 107BS of the first isolation layer 107. The first set of inclined isolation layers 301 may be parallel to one another. The first set of inclined isolation layers 301 may extend along a first direction E1. The first direction E1 may be inclined relative to the vertical axis Z. An angle α between the first direction E1 and the vertical axis Z may be between approximately 10 degrees and approximately 80 degrees.

[0116] Please refer to Figure 1 The second group of inclined isolation layers 303 may be disposed within the first isolation layer 107 and between the conductive studs 201-1 and 201-3. Each upper surface 303TS of the second group of inclined isolation layers 303 may be substantially coplanar with the upper surface 107TS of the first isolation layer 107. Each lower surface 303BS of the second group of inclined isolation layers 303 may be coplanar with the lower surface 107BS of the first isolation layer 107. The second group of inclined isolation layers 303 may be parallel to one another. The second group of inclined isolation layers 303 may extend along a second direction E2. The second direction E2 may be inclined relative to the vertical axis Z. The first direction E1 and the second direction E2 may intersect. An angle β between the second direction E2 and the vertical axis Z ranges from approximately -10 degrees to approximately -80 degrees. Some of the first group of inclined isolation layers 301 and some of the second group of inclined isolation layers 303 may intersect. Others of the first group of inclined isolation layers 301 and others of the second group of inclined isolation layers 303 may not intersect.

[0117] In some embodiments, an angle between the first direction E1 and the second direction E2 may be between about 20 degrees and about 160 degrees.

[0118] The first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may comprise the same material. In some embodiments, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may comprise a material different from that of the first isolation layer 107. In some embodiments, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may comprise the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, fluidized oxide, silazane, undoped silica glass, borosilica glass, phosphosilicate glass, borophosphosilicate glass, plasma-assisted ethyltetrasilicon dioxide, fluorosilicate glass, carbon-doped silicon oxide, organosilicate glass, low-k dielectric material, or a combination thereof.

[0119] In some embodiments, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may comprise a material having a dielectric constant lower than that of the first isolation layer 107. The first set of inclined isolation layers 301 and the second set of inclined isolation layers 303, comprising a material with a lower dielectric constant, can reduce parasitic capacitance between the conductive studs 201-1 and 201-3. In other words, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303, comprising a material with a lower dielectric constant, can mitigate interference effects between electronic signals generated by the conductive studs 201-1 and 201-3, or between electronic signals applied to the conductive studs 201-1 and 201-3.

[0120] In some embodiments, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may comprise a material having a coefficient of thermal expansion (CTE) less than approximately 20 ppm / °C and a Young's modulus less than approximately 15 GPa. In some embodiments, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may comprise a material including polyimide or an epoxy-based material. The first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may serve as a cushion to reduce stress during a bumping process or a wiring process; thereby, delamination of the first isolation layer 107 may be reduced.

[0121] Please refer to Figure 1 The pad layer 109 may be disposed on the first isolation layer 107. The pad layer 109 may cover the upper surfaces of the conductive studs 201-1 and 201-3, the upper surfaces 301TS of the first set of inclined isolation layers 301, and the upper surfaces 301TS of the second set of inclined isolation layers 303. For example, the pad layer 109 may include the following materials: aluminum, copper, titanium, tungsten, aluminum-copper alloy, aluminum alloy, or copper alloy.

[0122] Figures 2 to 9 Schematic cross-sectional views of semiconductor elements 1B, 1C, 1D, 1E, 1F, 1G, 1H, and 1I illustrating some embodiments of the present disclosure. Figure 2 , the semiconductor element 1B may have a similar Figure 1 A structure is shown as an example. Figure 2 Zhongyu Figure 1 The same or similar components are marked with similar component numbers and repeated descriptions are omitted. Figure 2The lower portions of the sidewalls of the conductive studs 201-1 and 201-3 may be away from the lower conductive layer 105. The first group of inclined isolation layers 301 and the second group of inclined isolation layers 303 may be disposed between the conductive studs 201-1 and 201-3.

[0123] Please refer to Figure 3 , the semiconductor element 1C may have a similar Figure 1 A structure is shown as an example. Figure 3 Zhongyu Figure 1 The same or similar elements are marked with like element numbers, and repeated descriptions are omitted.

[0124] Please refer to Figure 3 The conductive studs 201-1 and 201-3 may be disposed along the first isolation layer 107 and on the lower conductive layer 105. The first group of inclined isolation layers 301 and the second group of inclined isolation layers 303 may be disposed between the conductive studs 201-1 and 201-3.

[0125] Please refer to Figure 4 , the semiconductor element 1D may have a similar Figure 1 A structure is shown as an example. Figure 4 Zhongyu Figure 1 The same or similar components are marked with similar component numbers and repeated descriptions are omitted. Figure 4 The conductive stud 201-1 may be disposed along the first isolation layer 107 and on the lower conductive layer 105. The conductive stud 201-3 may be disposed along the first isolation layer 107 and the lower conductive layer 105. The lower portion of the sidewall of the conductive stud 201-3 may be bonded to the lower conductive layer 105. The first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may be disposed between the conductive studs 201-1 and 201-3.

[0126] Please refer to Figure 5 , the semiconductor element 1E may have a similar Figure 4 A structure is shown as an example. Figure 5 Zhongyu Figure 4 The same or similar components are marked with similar component numbers and repeated descriptions are omitted. Figure 5 The lower portion of the sidewall of the conductive stud 201-3 may be away from the lower conductive layer 105. In some embodiments, the conductive stud 201-3 may electrically isolate the lower conductive layer 105. The first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may be disposed between the conductive studs 201-1 and 201-3. The conductive stud 201-3 may improve the mechanical strength of the semiconductor device 1E.

[0127] Please refer to Figure 6, the semiconductor element 1F may have a similar Figure 1 A structure is shown as an example. Figure 6 Zhongyu Figure 1 The same or similar components are marked with similar component numbers and repeated descriptions are omitted. Figure 6 , the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may be porous. The porosity of the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may be between about 10% and about 80%. The first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may include a skeleton and a plurality of empty spaces, wherein the plurality of empty spaces are between the skeletons. The plurality of empty spaces may be interconnected and may be filled with air. For example, the skeleton may include silicon oxide, low-dielectric materials, or methylsilsesquioxane. The plurality of empty spaces of the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may be filled with air. Therefore, for example, a dielectric constant of the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may be significantly lower than that of a layer including silicon oxide. Therefore, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 can significantly reduce the parasitic capacitance between the conductive studs 201-1 and 201-3. In other words, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 can mitigate interference effects between electronic signals generated by the conductive studs 201-1 and 201-3, or between electronic signals applied to the conductive studs 201-1 and 201-3.

[0128] Please refer to Figure 7 , the semiconductor element 1G may have a similar Figure 1 A structure is shown as an example. Figure 7 Zhongyu Figure 1 The same or similar components are marked with similar component numbers and repeated descriptions are omitted. Figure 7 More conductive studs can be disposed in the semiconductor device 1G. For example, conductive studs 201-1 and 201-3 can be disposed along the first isolation layer 107 and the lower isolation layer 103. Conductive studs 201-5 and 201-7 can be disposed along the first isolation layer 107 and on the lower conductive layer 105. The first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 can be disposed between adjacent pairs of conductive studs 201-1, 201-3, 201-5, and 201-7, respectively.

[0129] Please refer to Figure 8 , the semiconductor element 1H may have a similar Figure 7 A structure is shown as an example. Figure 8 Zhongyu Figure 7 The same or similar components are marked with similar component numbers and repeated descriptions are omitted. Figure 8 The first group of inclined isolation layers 301 and the second group of inclined isolation layers 303 may be disposed only in some of the adjacent pairs of conductive studs 201-1, 201-3, 201-5, and 201-7. For example, in the present disclosure, the first group of inclined isolation layers 301 and the second group of inclined isolation layers 303 may be disposed only between the conductive studs 201-1 and 201-5, and between the conductive studs 201-7 and 201-3.

[0130] Please refer to Figure 9 , the semiconductor element 1I may have a similar Figure 7 A structure is shown as an example. Figure 9 Zhongyu Figure 7 The same or similar elements are marked with like element numbers, and repeated descriptions are omitted.

[0131] Please refer to Figure 9 Each lowest point 301BP of the first set of inclined isolation layers 301 and each lowest point 303BP of the second set of inclined isolation layers 303 may be located on a vertical plane, which is located on a vertical plane of the lower surface 107BS of the first isolation layer 107 .

[0132] Figure 10 A schematic flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to some embodiments of the present disclosure. Figures 11 to 19 A cross-sectional diagram illustrating the process of a method for manufacturing a semiconductor device 1A according to some embodiments of the present disclosure. Figure 10 and Figure 11 In step S11 , a substrate 101 may be provided, a lower conductive layer 104 may be formed on the substrate 101 , and a first isolation layer 107 may be formed on the lower conductive layer 105 .

[0133] Please refer to Figure 11 A lower isolation layer 103 may be formed on the substrate 101. The fabrication technique for the lower isolation layer 103 may include a deposition process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or the like. The lower conductive layer 105 may be formed in the lower isolation layer 103 using a damascene process. The first isolation layer 107 may be formed on the lower conductive layer 105 and the lower isolation layer 103 using a process similar to that used to form the lower isolation layer 103.

[0134] Please refer to Figure 10 and Figure 12In step S13, conductive studs 201-1 and 201-3 may be formed along the first isolation layer 107 and electrically connected to the lower conductive layer 105, and a first hard mask layer 401 may be formed on the first isolation layer 107. Figure 12 A lithography process may be performed to define a desired pattern of the conductive plugs 201-1 and 201-3. A continuous etching process, such as an anisotropic etching process, may be performed to vertically form a plurality of openings along the first isolation layer 107 and the lower isolation layer 103. A conductive material, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (such as tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (such as titanium nitride), transition metal aluminide, or a combination thereof, may completely fill the plurality of openings. Next, a planarization process, such as chemical mechanical polishing, may be performed until the upper surface of the first isolation layer 107 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the conductive plugs 201-1 and 201-3.

[0135] In some embodiments, the first hard mask layer 401 may include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like, or a combination thereof. The first hard mask layer 401 may be fabricated using a variety of deposition techniques, such as chemical vapor deposition (CVD), plasma-enhanced CVD, low-pressure CVD, or the like.

[0136] It should be understood that in the description of this disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the ratio of oxygen is greater than the ratio of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the ratio of nitrogen is greater than the ratio of oxygen.

[0137] In some embodiments, the first hard mask layer 401 may include boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride. The fabrication technique for the first hard mask layer 401 may include a film formation process and a treatment process. In some embodiments, during the film formation process, a first precursor, which may be a boron-based precursor, may be introduced onto the first isolation layer 107 to form a boron-based layer. Next, during the treatment process, a second precursor, which may be a nitrogen-based precursor, may be introduced to react with the boron-based layer and convert the boron-based layer into the first hard mask layer 401.

[0138] In some embodiments, the first precursors may be diborane, borazine, or an alkyl-substituted derivative of borazine. In some embodiments, the first precursors may be introduced at a flow rate between approximately 5 sccm (standard cubic centimeter per minute) and approximately 50 slm (standard liter per minute); in some embodiments, between approximately 10 sccm and approximately 1 slm. In some embodiments, the first precursors may be introduced via a dilution gas, such as nitrogen, hydrogen, argon, or a combination thereof. The dilution gas may be introduced at a flow rate between approximately 5 sccm and approximately 50 slm; in some embodiments, between approximately 1 slm and approximately 10 slm.

[0139] In some embodiments, the film formation process can be performed without plasma assistance. In this case, a substrate temperature during the film formation process may be between approximately 100° C. and approximately 1000° C. For example, the substrate temperature during the film formation process may be between approximately 300° C. and approximately 500° C. A process pressure during the film formation process may be between approximately 10 mTorr and approximately 760 Torr. For example, the process pressure during the film formation process may be between approximately 2 Torr and approximately 10 Torr.

[0140] In some embodiments, the film formation process may be performed in the presence of plasma. In this case, a substrate temperature of the film formation process may be between approximately 100° C. and approximately 1000° C. For example, the substrate temperature of the film formation process may be between approximately 300° C. and approximately 500° C. A process temperature of the film formation process may be between approximately 10 mTorr and approximately 760 Torr. For example, the process temperature of the film formation process may be between approximately 2 Torr and approximately 10 Torr. The plasma may be provided by an RF power between 2 W and 5000 W. For example, the plasma may be provided by an RF power between 30 W and 1000 W.

[0141] In some embodiments, the plurality of second precursors may be ammonia or hydrazine. In some embodiments, the plurality of second precursors may be introduced at a flow rate between about 5 sccm and about 50 slm; in some embodiments, between about 10 sccm and about 1 slm.

[0142] In some embodiments, a plurality of oxygen-based precursors may be introduced together with the plurality of second precursors during the treatment process. For example, the plurality of oxygen-based precursors may be oxygen, nitric oxide, nitrous oxide, carbon dioxide, or water.

[0143] In some embodiments, a plurality of silicon-based precursors may be introduced during the treatment process along with the plurality of second precursors. For example, the plurality of silicon-based precursors may include silane, trisilylamine, trimethylsilane, and silazanes (e.g., hexamethylcyclotrisilazane).

[0144] In some embodiments, a plurality of phosphorus-based precursors may be introduced into the process together with the plurality of second precursors. For example, the plurality of phosphorus-based precursors may be phosphine.

[0145] In some embodiments, the plurality of oxygen-based precursors, the plurality of silicon-based precursors, or the plurality of phosphorus-based precursors may be introduced together with the plurality of second precursors during the treatment process.

[0146] In some embodiments, the treatment process may be performed with the assistance of a plasma process, a UV cure process, a thermal annealing process, or a combination thereof.

[0147] When the treatment is performed with the aid of a plasma process, the plasma of the plasma process may be provided by radio frequency (RF) power. In some embodiments, the RF power may be between about 2 W and about 5000 W at a single low frequency between about 100 kHz and about 1 MHz. In some embodiments, the RF power may be between about 30 W and about 1000 W at a single high frequency greater than about 13.6 MHz. In this case, a substrate temperature of the treatment process may be between about 20° C. and about 1000° C. A process pressure of the treatment process may be between about 10 mTorr and about 760 Torr.

[0148] When the treatment is performed with the aid of a UV curing process, a substrate temperature for the treatment process may be between approximately 20° C. and approximately 1000° C. A process temperature for the treatment process may be between approximately 10 mTorr and approximately 760 Torr. UV curing may be provided by any UV source, such as a mercury microwave arc lamp, a pulsed xenon flash lamp, or a high-efficiency UV light emitting diode array. The UV source may have a wavelength between approximately 170 nm and approximately 400 nm. The UV source may provide a photon energy between approximately 0.5 eV and approximately 10 eV; in some embodiments, between approximately 1 eV and approximately 6 eV. The UV curing process may assist in removing hydrogen from the first hard mask layer 201. While hydrogen may diffuse into other regions of the semiconductor device 1A and potentially degrade the reliability of the semiconductor device 1A, the removal of hydrogen with the aid of the UV curing process may improve the reliability of the semiconductor device 1A. In addition, the UV curing process can increase the density of the first hard mask layer 401 .

[0149] When the treatment is performed with the aid of a thermal annealing process, a substrate temperature of the treatment process may be between about 20° C. and about 1000° C. A process pressure of the treatment process may be between about 10 mTorr and about 760 Torr.

[0150] In some embodiments, the first hard mask layer 401 can be made of a carbon film. As used herein, the term "carbon film" refers to a material primarily defined by a plurality of carbon atoms or whose physical and chemical properties depend on its carbon content. The term "carbon film" excludes materials that are simple mixtures or compounds containing carbon, such as dielectric materials such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polysilicon. These terms do include, for example, graphite, charcoal, and halocarbons.

[0151] In some embodiments, the carbon film is deposited by a process comprising introducing a process gas mixture into a process chamber, the process gas mixture comprising one or more hydrocarbon compounds having a chemical formula C x H y, wherein x is in the range of 2 to 4, and y is in the range of 2 to 10. For example, the hydrocarbon compound may be propylene (C3H6), propyne (C3H4), propane (C3H8), butane (C4H 10 ), butylene (C4H8), butadiene (C4H6), acetylene (C2H2), or a combination thereof. In some embodiments, partially or fully fluorinated derivatives of hydrocarbon compounds may be used. Doping derivatives include boron-containing derivatives of hydrocarbon compounds and fluorinated derivatives thereof.

[0152] In some embodiments, the carbon film is deposited from the process gas mixture by maintaining a substrate temperature between about 100° C. and about 700° C., and in some embodiments, between about 350° C. and 550° C. In some embodiments, the carbon film is deposited from the process gas mixture by maintaining a chamber pressure between about 1 Torr and about 20 Torr. The carbon film can be deposited from the process gas mixture by introducing a hydrocarbon gas and any inert or reactive gas at a flow rate between about 50 sccm and about 2000 sccm, respectively.

[0153] In some embodiments, the processing gas mixture may also include an inert gas, such as argon. However, other inert gases may be used, such as nitrogen or other inert gases, such as helium. The multiple inert gases may be used to control the density and deposition rate of the carbon film. In addition, a variety of different gases may be added to the processing gas mixture to change the properties of the carbon film. The multiple gases may be reactive gases, such as hydrogen, ammonia, a mixture of hydrogen and nitrogen, or a combination thereof. The addition of hydrogen or ammonia may be used to control the hydrogen ratio of the carbon film, thereby controlling layer properties, such as etching selectivity, chemical mechanical polishing resistance characteristics, and reflectivity. In some embodiments, a mixture of the multiple reactive gases and the multiple inert gases may be added to the processing gas mixture to deposit the carbon film.

[0154] Carbon films can contain carbon and hydrogen atoms with an adjustable carbon:hydrogen ratio ranging from approximately 10% hydrogen to approximately 60% hydrogen. Controlling the hydrogen ratio of the carbon film can adjust the corresponding etch selectivity and chemical mechanical polishing resistance characteristics. As the hydrogen content decreases, the etch resistance and selectivity of the carbon film increase. The reduced removal rate of the carbon film makes it suitable for use as a masking layer when performing an etching process to transfer the desired pattern to the underlying layer.

[0155] Please refer to Figure 13 A first mask layer 403 may be formed on the first hard mask layer 401. The first mask layer 43 may be a photoresist layer. The first mask layer 403 may be patterned by a lithography process. Figure 14 An etching process, such as an anisotropic dry etching process, may be performed to remove portions of the first hard mask layer 401 and simultaneously form the plurality of first hard mask openings 405. In some embodiments, the etching rate of the first hard mask layer 401 during the etching process may be faster than the etching rate of the first isolation layer 107 during the etching process. For example, during the etching process, the ratio of the etching rate of the first hard mask layer 401 to the first isolation layer 107 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1. In some embodiments, a ratio of the width W1 of the plurality of first hard mask openings 405 to the height H1 of the first hard mask openings 405 may be between approximately 5:1 and approximately 1:15, between approximately 3:1 and approximately 1:13, between approximately 1:1 and approximately 1:11, and between approximately 5:1 and approximately 1:8.

[0156] Please refer to Figure 10 、 Figure 15 as well as Figure 16 In step S17, a first set of inclined trenches 407 and a second set of inclined trenches 409 may be formed along the first isolation layer 107 between the conductive studs 201-1 and 201-3. Figure 15, a first oblique etching process 501 may be performed to form a first set of oblique trenches 407 along the first isolation layer 107. The first oblique etching process 501 may use the first hard mask layer 401 and the plurality of first hard mask openings 405 as a plurality of pattern guides. In some embodiments, an incident angle γ of the first oblique etching process 501 may be defined by a width W1 of the plurality of first hard mask openings 405 and a height H1 of the plurality of first hard mask openings 405. In some embodiments, the incident angle γ of the first oblique etching process 501 may be between approximately 10 degrees and approximately 80 degrees. In some embodiments, the incident angle γ of the first oblique etching process 501 may be between approximately 20 degrees and approximately 60 degrees. In some embodiments, the incident angle γ of the first oblique etching process 501 may be between approximately 20 degrees and approximately 40 degrees.

[0157] In some embodiments, the first oblique etching process 501 may be an anisotropic etching process, such as a reactive ion etching process. The reactive ion etching process may include multiple etchant gases and multiple passivation gases, which may suppress the isotropic effect and limit the removal of material in the horizontal direction. The multiple etchant gases may include chlorine gas and boron trichloride. The multiple passivation gases may include fluoroform or other suitable halocarbons. In some embodiments, the multiple first hard mask layers 401 made of carbon film can serve as a halocarbon source for the multiple passivation gases in the reactive ion etching process.

[0158] In some embodiments, the etching rate of the first isolation layer 107 in the first bevel etching process 501 may be faster than the etching rate of the first hard mask layer 401 in the first bevel etching process 501. For example, during the first bevel etching process 501, the ratio of the etching rate of the first isolation layer 107 to the first hard mask layer 401 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1. In some embodiments, during the first inclined etching process 501, an etching rate ratio of the first isolation layer 107 to the conductive plugs 201-1 and 201-3 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0159] The first group of inclined trenches 407 may extend along a first direction E1, which is inclined relative to the vertical axis Z. An acute angle γ' between each sidewall 407SW of the first group of inclined trenches 407 and each bottom surface 407BS of the first group of inclined trenches 407 may be between approximately 10 degrees and approximately 80 degrees. A width W2 of the first group of inclined trenches 407 may be smaller than a width W1 of the plurality of first hard mask openings 405.

[0160] Please refer to Figure 16 A second oblique etching process 503 may be performed to form a second set of oblique trenches 409 along the first isolation layer 107. The second oblique etching process 503 may use the first hard mask layer 401 and the plurality of first hard mask openings 405 as pattern guides. In some embodiments, an incident angle δ of the second oblique etching process 503 may be opposite to an incident angle γ of the first oblique etching process 501 relative to the vertical axis Z and may be defined by a width W1 of the plurality of first hard mask openings 405 and a height H1 of the plurality of first hard mask openings 405. In some embodiments, the incident angle δ of the second oblique etching process 503 may be different from the incident angle γ of the first oblique etching process 501. In some embodiments, the incident angle δ of the second oblique etching process 503 may be between approximately -10 degrees and approximately -80 degrees.

[0161] In some embodiments, the second bevel etching process 503 may be an anisotropic etching process, such as a reactive ion etching process. The etching rate of the first isolation layer 107 during the second bevel etching process 503 may be faster than the etching rate of the first hard mask layer 401 during the second bevel etching process 503. For example, during the second bevel etching process 503, the etching rate ratio of the first isolation layer 107 to the first hard mask layer 401 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1. In some embodiments, during the second inclined etching process 503, an etching rate ratio of the first isolation layer 107 to the conductive plugs 201-1 and 201-3 may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1.

[0162] The second group of inclined grooves 409 may extend along a second direction E2, which is inclined relative to the vertical axis Z. The second direction E2 may intersect the first direction E1. In some embodiments, an acute angle δ' between each sidewall 409SW of the second group of inclined grooves 409 and each bottom surface 409BS of the second group of inclined grooves 409 may be between approximately -10 degrees and approximately -80 degrees. In some embodiments, portions of the first group of inclined grooves 407 and the second group of inclined grooves 409 may overlap. In other words, some of the first group of inclined grooves 407 and the second group of inclined grooves 409 may intersect. The width W3 of the second group of inclined grooves 409 may be less than the width W1 of the plurality of first hard mask openings 405. In some embodiments, the width W3 of the second group of inclined grooves 409 may be the same as the width W2 of the first group of inclined grooves 407, but is not limited thereto.

[0163] Please refer to Figure 10 、 Figure 17 and Figure 18 In step S19, a first set of inclined isolation layers 301 may be formed in the first set of inclined trenches 407, and a second set of inclined isolation layers 301 may be formed in the second set of inclined trenches 409. Figure 17A layer of first isolation material 411 may be formed to completely fill the first set of inclined trenches 407, the second set of inclined trenches 409, and the plurality of first hard mask openings 405, and to cover the first hard mask layer 401. In some embodiments, the first isolation material 411 may be a material different from the first isolation layer 107. In some embodiments, the first isolation material 411 may be a material having a dielectric constant that is less than the dielectric constant of the first isolation layer 107. In some embodiments, the first isolation material 411 may be silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, flowing oxide, silazane, undoped silica glass, borosilica glass, phosphosilicate glass, borophosphosilicate glass, plasma-assisted ethyltetrasilicon, fluorosilicate glass, carbon-doped silicon oxide, organosilicate glass, or combinations thereof. In some embodiments, the first isolation material 411 may be a material having a coefficient of thermal expansion less than approximately 20 ppm / °C and a Young's modulus less than approximately 15 GPa.

[0164] Please refer to Figure 18 A planarization process, such as chemical mechanical polishing, may be performed until the upper surface 107TS of the first isolation layer 107 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303.

[0165] The cross-sectional profile of the first set of inclined isolation layers 301 can be defined by the first set of inclined trenches 407. In some embodiments, the first set of inclined isolation layers 301 can extend along a first direction E1. An acute angle γ" between each sidewall 301SW of the first set of inclined isolation layers 301 and each bottom surface 301BS of the first set of inclined isolation layers 301 can be between approximately 10 degrees and approximately 80 degrees.

[0166] The cross-sectional profile of the second set of inclined isolation layers 303 may be defined by the second set of inclined trenches 409. In some embodiments, the second set of inclined isolation layers 303 may extend along the second direction E2. An acute angle δ″ between each sidewall 303SW of the second set of inclined isolation layers 303 and each bottom surface 303BS of the second set of inclined isolation layers 303 may be between approximately -10 degrees and approximately -80 degrees. In some embodiments, portions of the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may overlap. In other words, portions of the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 may intersect.

[0167] Please refer to Figure 10 and Figure 19 In step S21, a pad layer 109 may be formed on the conductive studs 201-1 and 201-3. Figure 19A pad layer 109 can be formed to cover the upper surfaces of the conductive studs 201-1 and 201-3, the upper surfaces of the first set of inclined isolation layers 301, and the upper surfaces of the second set of inclined isolation layers 303. The pad layer 109 can be fabricated using a deposition process followed by a subsequent photo-etching process. The deposition process can be physical vapor deposition, chemical vapor deposition, sputtering, or electroplating.

[0168] Figures 20 to 22 A cross-sectional view illustrating the process of a method for manufacturing a semiconductor device 1F according to another embodiment of the present disclosure. Figure 20 , an intermediate semiconductor can be similar to Figures 11 to 16 The energy-removable composite 413 is fabricated by a process illustrated in the example. A layer of energy-removable composite 413 may completely fill the first set of inclined trenches 407, the second set of inclined trenches 409, and the plurality of first hard mask openings 405, and cover the first hard mask layer 401. The energy-removable composite 413 may include a material, such as a thermally decomposable material, a photodecomposable material, an electron beam decomposable material, or a combination thereof. For example, the energy-removable composite 413 may include a base material and a decomposable porogen material that is sacrificially removed upon exposure to an energy source. The base material may include a methylsilsesquioxane-based material, a low-k dielectric material, or silicon oxide. The decomposable porogen material may include a porogen organic compound that provides porosity to the base material of the energy-removable composite 413. In some embodiments, the energy-removable composite 413 may comprise approximately 10% decomposable porogen material and approximately 90% base material. In some embodiments, the energy removable composite 413 may comprise approximately 80% decomposable porogen material and approximately 20% base material.

[0169] Please refer to Figure 21 , which can be executed similar to Figure 18 The pad layer 109 can be planarized by a process similar to the following. Figure 19 The etched portion is formed on the first isolation layer 107 by the illustrated process.

[0170] Please refer to Figure 22 , an energy treatment process can be performed by applying an energy source thereto. Figure 21The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, a temperature of the energy treatment may be between approximately 800° C. and approximately 900° C. When light is used as the energy source, ultraviolet light may be applied. The energy treatment may remove the decomposable porogen material from the layer of energy-removable composite 413 to create a plurality of empty spaces (pores), while the base material remains in place. After the energy treatment, the layer of energy-removable composite 413 may be converted into the porous first set of tilted isolation layers 301 and the second set of tilted isolation layers 303.

[0171] One embodiment of the present disclosure provides a semiconductor element, comprising a substrate; two conductive studs located on the substrate and extending along a vertical axis; a first set of inclined isolation layers parallel to each other and located between the two conductive studs; and a second set of inclined isolation layers parallel to each other and located between the two conductive studs; wherein the first set of inclined isolation layers extends along a first direction, which is inclined relative to the vertical axis; the second set of inclined isolation layers extends along a second direction, which is inclined relative to the vertical axis; and the first direction intersects the second direction.

[0172] Another embodiment of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming a first isolation layer on the substrate; forming two conductive studs along the first isolation layer; forming a first group of inclined grooves along the first isolation layer between the two conductive studs; forming a second group of inclined grooves along the first isolation layer between the two conductive studs; forming a first group of inclined isolation layers in the first group of inclined grooves along a first direction; and forming a second group of inclined isolation layers in the second group of inclined grooves along a second direction; wherein the first group of inclined isolation layers and the second group of inclined isolation layers are formed simultaneously, and the first direction intersects the second direction.

[0173] Due to the design of the semiconductor device disclosed herein, the first set of inclined isolation layers 301 and the second set of inclined isolation layers 303 can be used to adjust the dielectric constant between the conductive studs 201-1 and 201-3. Consequently, the parasitic capacitance between the conductive studs 201-1 and 201-3 can be reduced, thereby improving the performance of the semiconductor device 1A. Furthermore, the first set of inclined isolation layers 301 and the second set of isolation layers 303 can increase the elasticity of the first isolation layer 107, which can improve the bond strength and resistance of the semiconductor device 1A during a bonding process or a wiring process.

[0174] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0175] Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this disclosure.

Claims

1. A semiconductor device comprising: a base; Two conductive studs are located on the base and extend along a vertical axis; a first set of inclined isolation layers, parallel to each other and located between the two conductive studs; and a second set of inclined isolation layers, parallel to each other and located between the two conductive studs; The first group of inclined isolation layers extends along a first direction, which is inclined relative to the vertical axis; the second group of inclined isolation layers extends along a second direction, which is inclined relative to the vertical axis; and the first direction intersects the second direction.

2. The semiconductor device as claimed in claim 1 , further comprising a first isolation layer disposed on the substrate, wherein the two conductive studs are disposed along the first isolation layer, the first set of inclined isolation layers and the second set of inclined isolation layers are disposed in the first isolation layer, and the first set of inclined isolation layers and the second set of inclined isolation layers comprise a material different from a material of the first isolation layer. 3 . The semiconductor device of claim 2 , wherein the first set of inclined isolation layers and the second set of inclined isolation layers comprise a material having a dielectric constant lower than a dielectric constant of a material of the first isolation layer. 4 . The semiconductor device as claimed in claim 2 , wherein the first set of inclined isolation layers and the second set of inclined isolation layers are porous. 5 . The semiconductor device of claim 4 , wherein a porosity of each of the first set of inclined isolation layers and the second set of inclined isolation layers is between about 10% and about 80%. 6 . The semiconductor device of claim 2 , wherein the first set of inclined isolation layers and the second set of inclined isolation layers comprise a material having a thermal expansion coefficient and a Young's modulus, the thermal expansion coefficient being less than approximately 20 ppm / ° C., and the Young's modulus being less than approximately 15 GPa. 7 . The semiconductor device as claimed in claim 3 , further comprising a pad layer located on the two conductive studs, the first set of inclined isolation layers, and the second set of inclined isolation layers. 8 . The semiconductor device of claim 7 , wherein an angle between the first direction and the vertical axis is between about 10 degrees and about 80 degrees. 9 . The semiconductor device of claim 7 , wherein an angle between the second direction and the vertical axis is between approximately −10 degrees and approximately −80 degrees. 10 . The semiconductor device as claimed in claim 7 , wherein an angle between the first direction and the vertical axis is different from an angle between the second direction and the vertical axis. 11 . The semiconductor device as claimed in claim 7 , wherein an angle between the first direction and the vertical axis is opposite to an angle between the second direction and the vertical axis. 12 . The semiconductor device as claimed in claim 7 , wherein each lower surface of the first set of inclined isolation layers and each lower surface of the second set of inclined isolation layers are substantially coplanar with a lower surface of the first isolation layer. 13 . The semiconductor device as claimed in claim 7 , wherein each lowest point of the first set of inclined isolation layers and each lowest point of the second set of inclined isolation layers are located at a plane on a lower surface of the first isolation layer.

14. A method for preparing a semiconductor element, comprising: providing a substrate; forming a first isolation layer on the substrate; forming two conductive studs along the first isolation layer; forming a first set of inclined grooves along the first isolation layer between the two conductive studs; forming a second set of inclined trenches along the first isolation layer between the two conductive studs; forming a first set of inclined isolation layers in the first set of inclined trenches along a first direction; as well as forming a second set of inclined isolation layers in the second set of inclined trenches along a second direction; The first group of inclined isolation layers and the second group of inclined isolation layers are formed simultaneously, and the first direction intersects the second direction. 15 . The method for fabricating a semiconductor device as claimed in claim 14 , wherein the first set of inclined isolation layers and the second set of inclined isolation layers comprise a material that is different from a material of the first isolation layer. 16 . The method for fabricating a semiconductor device as claimed in claim 14 , wherein the first set of inclined isolation layers and the second set of inclined isolation layers comprise a material having a dielectric constant lower than a dielectric constant of a material of the first isolation layer.

17. The method for fabricating a semiconductor device as claimed in claim 15, wherein the step of forming the first set of inclined trenches comprises: forming a first hard mask layer on the first isolation layer; forming a plurality of first hard mask openings along the first hard mask layer; as well as A first oblique etching process is performed on the first isolation layer using the first hard mask layer and the first hard mask openings as pattern guides to form the first set of oblique trenches. 18 . The method for fabricating a semiconductor device according to claim 17 , wherein the first hard mask layer comprises the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or a carbon film.

19. The method for fabricating a semiconductor device according to claim 18, wherein the step of forming the second set of inclined isolation layers comprises: The first hard mask layer and the plurality of first hard mask openings are used as a plurality of pattern guides to perform a second inclined etching process on the first isolation layer to form the second set of inclined grooves, and an incident angle of the first inclined etching process is opposite to an incident angle of the second inclined etching process.

20. The method for fabricating a semiconductor device according to claim 19, wherein the step of forming the first set of inclined isolation layers and the step of forming the second set of inclined isolation layers comprise: forming a layer of energy-removable compound in the first set of inclined grooves and the second set of inclined grooves, wherein the layer of energy-removable compound comprises a base material and a decomposable porogen material; as well as An energy treatment is performed to transform the layer of energy-removable composite into the first set of tilted isolation layers and the second set of tilted isolation layers.

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