Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a manufacturing method of a semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked with each other, a cell plug passing through the stacked structure, a selection plug coupled to the cell plug, and a selection pattern surrounding the selection plug, wherein the selection pattern includes a first conductive portion and a second conductive portion covering a side wall and a top surface of the first conductive portion, and wherein the plurality of conductive patterns, the first conductive portion, and the second conductive portion include different materials.

Description

Technical Field

[0001] The various embodiments of this disclosure generally relate to semiconductor devices and methods of manufacturing such semiconductor devices, and more specifically, to three-dimensional semiconductor devices and methods of manufacturing such three-dimensional semiconductor devices. Background Technology

[0002] Semiconductor memory devices may include memory cells capable of storing data. Three-dimensional semiconductor memory devices may include memory cells arranged in three dimensions, thereby reducing the area occupied by the memory cells per unit area of ​​the substrate.

[0003] To increase the integration density of three-dimensional semiconductor memory devices, the number of memory cells stacked on top of each other can be increased. However, with more memory cells stacked, the operational reliability of three-dimensional semiconductor memory devices may deteriorate. Summary of the Invention

[0004] According to an embodiment, a semiconductor device may include: a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on top of each other; a unit plug passing through the stacked structure; a selection plug coupled to the unit plug; and a selection pattern surrounding the selection plug, wherein the selection pattern includes a first conductive portion and a second conductive portion covering the sidewalls and top surface of the first conductive portion, and wherein the plurality of conductive patterns, the first conductive portion and the second conductive portion comprise different materials.

[0005] According to an embodiment, a semiconductor device may include: a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on top of each other; a cell plug passing through the stacked structure; a selection plug coupled to the cell plug; and a selection pattern surrounding the selection plug, wherein the selection pattern includes a first conductive portion and a second conductive portion covering the sidewalls and top surface of the first conductive portion, wherein the selection plug includes a selection channel layer coupled to the cell plug and a selection overlay pattern located above the selection channel layer, and wherein the second conductive portion and the selection overlay pattern comprise the same material.

[0006] According to an embodiment, a semiconductor device may include: a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on top of each other; a unit plug passing through the stacked structure; a selection plug coupled to the unit plug; and a selection pattern surrounding the selection plug, wherein the selection pattern includes a first conductive portion and a second conductive portion covering the sidewalls and top surface of the first conductive portion, and wherein the second conductive portion includes a metal silicide.

[0007] According to an embodiment, a method of manufacturing a semiconductor device may include the following steps: forming a stacked structure; forming a cell channel layer through the stacked structure; forming a select channel layer electrically connected to the cell channel layer; forming a preliminary select pattern around the select channel layer; forming a diffused metal layer covering the select channel layer and the preliminary select pattern; and diffusing metal from the diffused metal layer into the select channel layer and the preliminary select pattern.

[0008] According to an embodiment, a method of manufacturing a semiconductor device may include the following steps: forming a stacked structure; forming a cell channel layer through the stacked structure; forming a selection channel layer electrically connected to the cell channel layer; forming a preliminary selection pattern around the selection channel layer; forming a diffused metal layer covering the preliminary selection pattern; and forming the selection pattern by diffusing the metal of the diffused metal layer into the preliminary selection pattern, wherein the selection pattern includes a first conductive portion and a second conductive portion covering a top surface and sidewalls of the first conductive portion, and wherein the second conductive portion includes the metal of the diffused metal layer. Attached Figure Description

[0009] Figure 1A This is a plan view of a semiconductor device according to an embodiment;

[0010] Figure 1B It is along Figure 1A A cross-sectional view taken by line A1-A1′;

[0011] Figure 1C It is along Figure 1A A cross-sectional view of line BB′;

[0012] Figure 1D yes Figure 1B A magnified view of region C1;

[0013] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19 , Figure 20A , Figure 20B , Figure 21 and Figure 22 This illustrates the example based on 1A, Figure 1B , Figure 1C and Figure 1D A diagram illustrating a method for manufacturing a semiconductor device according to an embodiment;

[0014] Figure 23 This is a block diagram illustrating the configuration of a memory system according to an embodiment; and

[0015] Figure 24 This is a block diagram illustrating the configuration of a computing system according to an implementation method. Detailed Implementation

[0016] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0017] In the following text, the terms "first" and "second" are used to distinguish one component from another. Therefore, components should not be limited by these terms.

[0018] Various implementations relate to semiconductor devices that can minimize the RC delay of the selected transistor.

[0019] Figure 1A This is a plan view of a semiconductor device according to an embodiment. Figure 1B It is along Figure 1A The cross-sectional view taken by line A1-A1′. Figure 1C It is along Figure 1A The cross-sectional view taken from line BB′. Figure 1D yes Figure 1B A magnified view of region C1.

[0020] Reference Figure 1A , Figure 1B , Figure 1C and Figure 1D A semiconductor device may include a source structure SOS. The source structure SOS may be plate-shaped, extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may intersect at right angles. The source structure SOS can be used as a source line of a semiconductor device. The source structure SOS may include a conductive material such as polysilicon.

[0021] According to an embodiment, the source structure SOS can be disposed on a substrate (not shown) that physically supports the source structure SOS. The substrate, which can serve as a semiconductor substrate, can have a plate-like shape extending along a plane defined by a first direction D1 and a second direction D2.

[0022] According to the embodiment, a peripheral circuit structure (not shown) including transistors and lines can be provided between the source structure SOS and the substrate.

[0023] The source structure SOS may include a first source layer SL1, a second source layer SL2, and a third source layer SL3. The second source layer SL2 may be disposed above the first source layer SL1, and the third source layer SL3 may be disposed above the second source layer SL2. The first source layer SL1, the second source layer SL2, and the third source layer SL3 may include conductive materials such as polysilicon.

[0024] The stacked structure STA can be disposed above the source structure SOS. The stacked structure STA can include conductive patterns CP and first insulating patterns IP1 alternately stacked on a third direction D3. The third direction D3 can intersect the first direction D1 and the second direction D2. For example, the third direction D3 can intersect the first direction D1 and the second direction D2 at right angles.

[0025] The first insulating pattern IP1 may include an insulating material such as an oxide. Each of the conductive patterns CP may include a conductive layer, such as, for example, at least one selected from doped silicon, metal silicide, tungsten, nickel, and cobalt. According to an embodiment, each of the conductive patterns CP may further include a barrier layer covering the surface of the conductive layer, wherein the barrier layer may be formed between the conductive layer and the first insulating pattern IP1. For example, the barrier layer may include titanium, titanium nitride, tantalum, or tantalum nitride. The conductive patterns CP can be used as word lines in a semiconductor device.

[0026] Cell plugs (CEPs) can be configured to pass through the stacked structure STA. Each cell plug (CEP) may include a cell fill layer (CFI), a cell channel layer (CCL) surrounding the cell fill layer (CFI), a first tunnel insulation layer (TL1) surrounding the upper and middle portions of the cell channel layer (CCL), a second tunnel insulation layer (TL2) surrounding the lower portion of the cell channel layer (CCL), a first data storage layer (DL1) surrounding the first tunnel insulation layer (TL1), a second data storage layer (DL2) surrounding the second tunnel insulation layer (TL2), a first barrier layer (BKL1) surrounding the first data storage layer (DL1), and a second barrier layer (BKL2) surrounding the second data storage layer (DL2). The cell plug (CEP) may extend in the third direction (D3).

[0027] The cell filler layer CFI can extend to D3 from the third direction. The cell filler layer CFI can include insulating materials such as oxides.

[0028] The cell channel layer CCL can extend onto the third direction D3. The cell channel layer CCL can contact the second source layer SL2 of the source structure SOS. The cell channel layer CCL can be coupled to the second source layer SL2 of the source structure SOS and can be electrically coupled to the second source layer SL2 of the source structure SOS. The cell channel layer CCL can include a conductive material such as polysilicon.

[0029] The first tunnel insulating layer TL1 and the second tunnel insulating layer TL2 may be spaced apart from each other on a third-direction D3. A second source layer SL2 may be disposed between the first tunnel insulating layer TL1 and the second tunnel insulating layer TL2. The first tunnel insulating layer TL1 and the second tunnel insulating layer TL2 may include materials that allow charge tunneling, such as oxides.

[0030] The first data storage layer DL1 and the second data storage layer DL2 may be spaced apart from each other on a third-direction D3. A second source layer SL2 may be disposed between the first data storage layer DL1 and the second data storage layer DL2. According to one embodiment, the first data storage layer DL1 and the second data storage layer DL2 may include materials for trapping charges, such as nitrides. According to another embodiment, the first data storage layer DL1 and the second data storage layer DL2 may include various materials depending on the method of storing data. For example, the first data storage layer DL1 and the second data storage layer DL2 may include silicon, phase change materials, or nanodots.

[0031] The first barrier layer BKL1 and the second barrier layer BKL2 may be spaced apart from each other on a third-direction D3. A second source layer SL2 may be disposed between the first barrier layer BKL1 and the second barrier layer BKL2. The first barrier layer BKL1 and the second barrier layer BKL2 may comprise materials capable of blocking charge movement, such as oxides.

[0032] The cell plug (CEP) may further include a cell cover pattern (CCP). The cell cover pattern (CCP) may cover the top surfaces of the cell fill layer (CFI), the cell channel layer (CCL), the first tunnel insulating layer (TL1), and the first data storage layer (DL1). The bottom surface of the cell cover pattern (CCP) may contact the top surface of the cell channel layer (CCL). The cell cover pattern (CCP) may be electrically connected to the cell channel layer (CCL). A first barrier layer (BKL1) may surround the cell cover pattern (CCP). The inner sidewall of the first barrier layer (BKL1) may contact the outer sidewall of the cell cover pattern (CCP). The cell cover pattern (CCP) may include a conductive material such as polysilicon.

[0033] A first insulating layer 110 may be disposed above the stacked structure STA. The first insulating layer 110 may cover the top surface of the cell plug CEP. The first insulating layer 110 may include an insulating material such as an oxide.

[0034] A slit structure SLS can be provided. The slit structure SLS can pass through the first insulating layer 110 and the laminated structure STA. Each of the slit structures SLS can extend in a second direction D2 and a third direction D3. Conductive patterns CP disposed on both sides of each slit structure SLS can be separated from each other in the first direction D1 through the slit structure SLS. Insulating patterns IP1 disposed on both sides of each slit structure SLS can be separated from each other in the first direction D1 through the slit structure SLS. The slit structure SLS can be disposed between cell plugs CEP. Cell plugs CEP can be disposed on both sides of each slit structure SLS. The slit structure SLS can include an insulating material such as oxide. Although in Figure 1B Not shown, but in an embodiment, the slit structure SLS may further include a source contact electrically connected to the source structure SOS.

[0035] The second insulating layer 120 may be disposed above the first insulating layer 110. The second insulating layer 120 may cover the top surface of the slit structure SLS. The second insulating layer 120 may include an insulating material such as an oxide.

[0036] Selective plugs (SEPs) can be configured to pass through the second insulating layer 120. Each selective plug SEP may include a selective fill layer (SFI), a selective channel layer (SCL), a gate insulating layer (GI), a spacer (SPA), and a selective overlay pattern (SCP). Selective plug SEPs may extend in a third direction (D3). Selective plug SEPs may contact cell plugs (CEPs). Selective plug SEPs may be coupled to and electrically connected to cell plugs (CEPs).

[0037] Selection patterns SP can be set around selection plugs SEP. Each selection pattern SP can surround multiple selection plugs SEP. Selection patterns SP can be set above the top surface of the first insulating layer 110. Selection patterns SP can be set in the second insulating layer 120 and can be used as selection lines for semiconductor devices.

[0038] Each of the selected patterns SP may include a first conductive portion CO1 and a second conductive portion CO2 surrounding the first conductive portion CO1, wherein the first conductive portion CO1 and the second conductive portion CO2 may include different materials. For example, the first conductive portion CO1 may include polycrystalline silicon, and the second conductive portion CO2 may include a metal silicide. For example, the metal silicide included in the second conductive portion CO2 may be nickel silicide. For example, the composition of the nickel silicide included in the second conductive portion CO2 may be NiSi. The first conductive portion CO1 of the selected pattern SP, the second conductive portion CO2 of the selected pattern SP, and the conductive pattern CP of the stacked structure STA may include different materials.

[0039] Multiple selection patterns SP can be disposed between adjacent slit structures SLS, wherein the multiple selection patterns SP can be disposed between slit structures SLS that are adjacent to each other along the first direction D1. The selection patterns SP disposed between adjacent slit structures SLS in the first direction D1 can be spaced apart from each other in the first direction D1. The space between adjacent selection patterns SP disposed between adjacent slit structures SLS can be defined as a first isolation gap DG1. The first isolation gap DG1 can be filled with a second insulating layer 120. The selection patterns SP disposed between adjacent slit structures SLS can be spaced apart from each other through the first isolation gap DG1.

[0040] The selection patterns SP disposed on both sides of the slit structure SLS can be spaced apart from each other. For example, the selection patterns SP disposed on both sides of the slit structure SLS can be spaced apart from each other in the first direction D1. The space between the selection patterns SP disposed on both sides of the slit structure SLS can be defined as a second isolation gap DG2. The second isolation gap DG2 can be filled with a second insulating layer 120. The selection patterns disposed on both sides of the slit structure SLS can be spaced apart from each other through the second isolation gap DG2.

[0041] The third insulating layer 130 may be disposed above the second insulating layer 120 and may include an insulating material. For example, the third insulating layer 130 may include a nitride.

[0042] The bit line contact BCT may be disposed in the third insulating layer 130. The bit line contact BCT may contact and be coupled to the select plug SEP. The bit line contact BCT may be electrically coupled to the select plug SEP. The bit line contact BCT may include a conductive material.

[0043] The fourth insulating layer 140 may be disposed above the third insulating layer 130. The fourth insulating layer 140 may include an insulating material such as an oxide.

[0044] Bit line BL can be disposed in the fourth insulating layer 140. Bit line BL can contact bit line contact BCT. Bit line BL can be connected to bit line contact BCT. Bit line BL can be electrically connected to bit line contact BCT and can include conductive material.

[0045] Reference Figure 1D The selectable filler layer SFI of the selectable plug SEP can extend in the third direction D3 to pass through the selectable pattern SP and the first insulating layer 110. The selectable filler layer SFI may include an insulating material such as oxide.

[0046] The selection channel layer SCL of the selector plug SEP can extend in the third direction D3 to pass through the selection pattern SP and the first insulating layer 110. The selection channel layer SCL can surround the selection fill layer SFI. The bottom surface SCL_B of the selection channel layer SCL can be curved. The bottom surface SCL_B of the selection channel layer SCL can contact the top surface of the cell cover pattern CCP and the first barrier layer BKL1. The top surface of the cell cover pattern CCP and the top surface of the first barrier layer BKL1 can correspond to the bottom surface SCL_B of the selection channel layer SCL and can be curved. The lowest portion SCL_L of the selection channel layer SCL can be located in the cell cover pattern CCP. The selection channel layer SCL can cover the top surface of the selection fill layer SFI and can include a conductive material. The selection channel layer SCL can include the same material as the first conductive portion CO1 of the selection pattern SP and the cell channel layer CCL of the cell plug CEP. The selection channel layer SCL can include a different material than the second conductive portion CO2 of the selection pattern SP and the selection cover pattern SCP. For example, the channel layer SCL can be polysilicon.

[0047] The selection overlay pattern SCP of the select plug SEP can be disposed above the select channel layer SCL. The selection overlay pattern SCP can contact the select channel layer SCL and the bit line contact BCT. The selection overlay pattern SCP can be coupled to the select channel layer SCL and the bit line contact BCT. The selection overlay pattern SCP can be electrically connected to the select channel layer SCL and the bit line contact BCT. The bottom surface SCP_B of the selection overlay pattern SCP can cover the top surface SCL_T of the select channel layer SCL. The bottom surface of the bit line contact BCT can contact the top surface SCP_T of the selection overlay pattern SCP. The selection overlay pattern SCP can be made of the same material as the second conductive portion CO2 of the selection pattern SP. The selection overlay pattern SCP can include a metal silicide such as nickel silicide. For example, the nickel silicide included in the selection overlay pattern SCP can be NiSi.

[0048] The gate insulating layer GI of the select plug SEP can extend in the third direction D3 to pass through the select pattern SP. The gate insulating layer GI can surround the select channel layer SCL and the select overlay pattern SCP. The gate insulating layer GI can surround the lower part of the select overlay pattern SCP.

[0049] The height of the bottom surface GI_B of the gate insulating layer GI can be higher than the height of the bottom surface SCL_B of the selected channel layer SCL. The bottom surface GI_B of the gate insulating layer GI can be disposed in the first insulating layer 110. The height of the bottom surface GI_B of the gate insulating layer GI can be lower than the height of the top surface of the first insulating layer 110, and can be higher than the height of the bottom surface of the first insulating layer 110. The height of the top surface GI_T of the gate insulating layer GI can be higher than the height of the top surface SCL_T of the selected channel layer SCL. The height of the top surface GI_T of the gate insulating layer GI can be higher than the height of the bottom surface SCP_B of the selected overlay pattern SCP. The height of the top surface GI_T of the gate insulating layer GI can be lower than the height of the top surface SCP_T of the selected overlay pattern SCP. The gate insulating layer GI can include an insulating material such as an oxide.

[0050] The spacer SPA of the selected plug SEP can extend on the third direction D3. The spacer SPA can surround the gate insulating layer GI. The spacer SPA can surround the upper part of the gate insulating layer GI. The thickness of the spacer SPA can be greater than the thickness of the gate insulating layer GI. The height of the top surface SPA_T of the spacer SPA can be the same as the height of the top surface GI_T of the gate insulating layer GI. The height of the top surface SPA_T of the spacer SPA can be higher than the height of the bottom surface SCP_B of the selected overlay pattern SCP, and can be higher than the height of the top surface SCL_T of the selected channel layer SCL. The height of the top surface SPA_T of the spacer SPA can be lower than the height of the top surface SCP_T of the selected overlay pattern SCP. The spacer SPA can be disposed above the selected pattern SP. The bottom surface SPA_B of the spacer SPA can contact the top surface CO2_T of the second conductive portion CO2 of the selected pattern SP. The spacer SPA can include an insulating material such as oxide.

[0051] The second conductive portion CO2 of pattern SP can cover the top surface CO1_T and sidewall CO1_S of the first conductive portion CO1. The first conductive portion CO1 can be spaced apart from the second insulating layer 120 by the second conductive portion CO2. The top surface CO1_T and sidewall CO1_S of the first conductive portion CO1 can be spaced apart from the second insulating layer 120. The bottom surface of the first conductive portion CO1 can contact the top surface of the first insulating layer 110.

[0052] The first conductive portion CO1 may include a protrusion PT passing through the second conductive portion CO2. The protrusion PT may protrude from the top surface CO1_T of the first conductive portion CO1 in a third direction D3. The sidewalls of the protrusion PT may contact the gate insulating layer GI or the sidewalls of the second conductive portion CO2. The top surface of the protrusion PT may contact the bottom surface SPA_B of the spacer SPA.

[0053] The selectable plug (SEP) may include a first selectable plug (SEP1) and a second selectable plug (SEP2). The first selectable plug (SEP1) may have a center that is offset from the center of the unit plug (CEP) in a direction opposite to the first direction (D1). The second selectable plug (SEP2) may have a center that is offset from the center of the unit plug (CEP) in the first direction (D1).

[0054] The selection pattern SP may include a first selection pattern SP1 and a second selection pattern SP2. The first selection pattern SP1 may surround a plurality of first selection plugs SEP1. The second selection pattern SP2 may surround a plurality of second selection plugs SEP2. The first selection pattern SP1 and the second selection pattern SP2 may be disposed between adjacent slit structures SLS. The first selection pattern SP1 and the second selection pattern SP2 disposed between adjacent slit structures SLS may be spaced apart from each other by a first isolation gap DG1.

[0055] The semiconductor device according to the embodiment includes a selection pattern SP and a selection plug SEP that can be formed by a process separate from the process of forming the conductive pattern CP and the cell plug CEP. Therefore, the space between the selection patterns SP can be reduced, and the dummy cell plugs disposed in the space between the selection patterns SP can be omitted. Therefore, the area of ​​the cell region can be reduced.

[0056] The semiconductor device according to the embodiment includes a select overlay pattern SCP that connects the select channel layer SCL and the bit line contact BCT. Therefore, a separate contact for connecting the select channel layer SCL and the bit line contact BCT can be omitted.

[0057] In the semiconductor device according to the embodiment, the second conductive portion CO2 covering the top surface CO1_T and sidewall CO1_S of the first conductive portion CO1 of the selection pattern SP may include nickel silicide. Therefore, the RC delay of the selection transistor can be minimized and the resistance of the selection line can be reduced.

[0058] According to the implementation method, the degree of freedom in selecting the length of the channel layer SCL can be increased. Therefore, the channel layer SCL can have a length sufficient to reduce the cutoff current of the selection transistor.

[0059] Figure 2 , Figure 3 , Figure 4, Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19 , Figure 20A , Figure 20B , Figure 21 and Figure 22 This is an example based on Figure 1A , Figure 1B , Figure 1C and Figure 1D A diagram illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0060] Reference Figure 2 The source structure SOS, the stacked structure STA, and the cell plug CEP can be formed as shown in the figure. Forming the source structure SOS may include sequentially forming a first source layer SL1, a first etch stop layer EL1, a source sacrificial layer SFL, a second etch stop layer EL2, and a third source layer SL3 on a third-direction D3. The first etch stop layer EL1 and the second etch stop layer EL2 may comprise different materials than the first source layer SL1 and the third source layer SL3. For example, the first etch stop layer EL1 and the second etch stop layer EL2 may comprise oxides. The source sacrificial layer SFL may comprise the same material as the first source layer SL1 and the third source layer SL3, such as polysilicon.

[0061] A stacked structure STA can be formed over a source structure SOS. Forming the stacked structure STA may include alternately stacking a first insulating layer and a second insulating layer on a third-direction D3 over the source structure SOS. The first insulating layer and the second insulating layer may include different materials from each other. For example, the first insulating layer may include an oxide, and the second insulating layer may include a nitride.

[0062] Cell plugs (CEPs) can be formed through the stacked structure STA. Forming each cell plug CEP may include forming a hole through the stacked structure STA, and sequentially forming a preliminary barrier layer pBKL, a preliminary data storage layer pDL, a preliminary tunnel insulation layer pTL, a cell channel layer CCL, a cell fill layer CFI, and a cell overlay pattern CCP within the hole. The preliminary barrier layer pBKL may include a material capable of blocking charge movement. According to an embodiment, the preliminary data storage layer pDL may include a material in which charge is trapped. The preliminary tunnel insulation layer pTL may include a material that allows charge tunneling.

[0063] As the forming unit plug CEP is formed, the first insulating layer of the stacked structure STA can be patterned and defined as a first insulating pattern IP1, and the second insulating layer of the stacked structure STA can be patterned and defined as a second insulating pattern IP2. The second insulating pattern IP2 may include a material different from the first insulating pattern IP1, such as a nitride.

[0064] Reference Figure 3 The first insulating layer 110 can be formed on top of the stacked structure STA. Subsequently, the second source layer SL2 of the source structure SOS, the conductive pattern CP of the stacked structure STA, and the slit structure SLS can be formed.

[0065] The steps of forming a second source layer SL2, a conductive pattern CP, and a slit structure SLS may include: forming a slit through a stacked structure STA; removing a source sacrificial layer SFL, a first etch stop layer EL1, and a second etch stop layer EL2 from the source structure SOS through the slit; exposing the sidewalls of the cell channel layer CCL by patterning a preliminary barrier layer pBKL, a preliminary data storage layer pDL, and a preliminary tunnel insulating layer pTL; forming a second source layer SL2 connected to the sidewalls of the cell channel layer CCL; removing a second insulating pattern IP2 from the stacked structure STA through the slit; forming a conductive pattern CP in the space of the stacked structure STA where the second insulating pattern IP2 has been removed; and forming the slit structure SLS in the slit.

[0066] Reference Figure 4 A preliminary selection layer pSE can be formed above the first insulating layer 110. The preliminary selection layer pSE can cover the top surface of the slit structure SLS and can include a conductive material. For example, the preliminary selection layer pSE can include polysilicon.

[0067] Reference Figure 5A first mask layer MA1 can be formed above the initial selection layer pSE, and a second mask layer MA2 can be formed above the first mask layer MA1. The initial selection layer pSE, the first mask layer MA1, and the second mask layer MA2 can include different materials from each other. For example, the first mask layer MA1 can include a nitride, while the second mask layer MA2 can include a photoresist layer.

[0068] Subsequently, a first aperture HO1 can be formed through the initial selection layer pSE, the first mask layer MA1, and the second mask layer MA2. A portion of the first insulating layer 110 can be exposed through the first aperture HO1. The second mask layer MA2 can be removed after the first aperture HO1 is formed.

[0069] Reference Figure 6 A first material layer ML1 can be formed covering the first insulating layer 110, the preliminary selection layer pSE, and the first mask layer MA1. The first material layer ML1 can be conformally formed on the first insulating layer 110, the preliminary selection layer pSE, and the first mask layer MA1. The first material layer ML1 may include an insulating material such as an oxide.

[0070] A second material layer ML2 may be formed covering the first material layer ML1. The second material layer ML2 may be conformally formed on the first material layer ML1. The second material layer ML2 may include a conductive material such as polysilicon.

[0071] Each of the first holes HO1 can be partially filled with the first material layer ML1 and the second material layer ML2.

[0072] Figure 7B yes Figure 7A A magnified view of region C2.

[0073] Reference Figure 7A and Figure 7B The first hole HO1 can be expanded. Expanding each first hole HO1 may include sequentially etching the second material layer ML2, the first material layer ML1, and the first insulating layer 110. Expanding each first hole HO1 may include sequentially removing a portion of the second material layer ML2, a portion of the first material layer ML1, and a portion of the first insulating layer 110 through the first hole HO1. The removed portion of the second material layer ML2, a portion of the first material layer ML1, and a portion of the first insulating layer 110 may be portions disposed between the first hole HO1 and the cell plug CEP. A portion of the second material layer ML2, a portion of the first material layer ML1, and a portion of the first insulating layer 110 may be removed to expose the cell cover pattern CCP and the first barrier layer BKL1 of the cell plug CEP. Expanding each first hole HO1 may also include removing a portion of the cell cover pattern CCP and a portion of the first barrier layer BKL1.

[0074] The sacrificial pattern FP retained in the first aperture HO1 can be formed by etching the second material layer ML2. The gate insulating layer GI retained in the first aperture HO1 can be formed by etching the first material layer ML1.

[0075] The bottom surface HO1_B of the expanded first hole HO1 can be bent. The top surface of the cell covering pattern CCP and the top surface of the first barrier layer BKL1 can correspond to the bottom surface HO1_B of the expanded first hole HO1, and can be bent.

[0076] Figure 8B yes Figure 8A A magnified view of region C3.

[0077] Reference Figure 8A and Figure 8B The sacrificial pattern FP can be removed from the first hole HO1. When the sacrificial pattern FP is removed, the inner sidewall of the gate insulation layer GI can be exposed.

[0078] Figure 9B yes Figure 9A A magnified view of region C4.

[0079] Reference Figure 9A and Figure 9B A third material layer ML3 can be formed to cover the first mask layer MA1, the gate insulating layer GI, the first insulating layer 110, the first barrier layer BKL1, and the cell overlay pattern CCP. The third material layer ML3 can be conformally formed over the first mask layer MA1, the gate insulating layer GI, the first insulating layer 110, the first barrier layer BKL1, and the cell overlay pattern CCP. The third material layer ML3 may include a conductive material such as polysilicon.

[0080] A fourth material layer ML4 can be formed covering the third material layer ML3. The fourth material layer ML4 can completely fill the first hole HO1. The fourth material layer ML4 can include an insulating material. For example, the fourth material layer ML4 can include an oxide.

[0081] Reference Figure 10 The fourth material layer ML4 can be etched. The fourth material layer ML4 can be etched such that the upper portion of the fourth material layer ML4 is removed, while the portion of the fourth material layer ML4 disposed in the first hole HO1 is retained. The portion of the fourth material layer ML4 retained in the first hole HO1 can be defined as the selective fill layer SFI.

[0082] Reference Figure 11A cover material layer can be formed covering the third material layer ML3 and the selective filler layer SFI. The cover material layer may include the same material as the third material layer ML3, such as polysilicon. Because the cover material layer includes the same material as the third material layer ML3, it can be integrally bonded to the third material layer ML3. The integrally bonded cover material layer and the third material layer ML3 can be defined as a fifth material layer ML5. The fifth material layer ML5 may include a conductive material such as polysilicon.

[0083] Reference Figure 12 The upper portion of the fifth material layer ML5 can be removed. For example, the upper portion of the fifth material layer ML5 can be removed by a chemical mechanical polishing (CMP) process. The retained portion in the fifth material layer ML5 can be defined as the selective channel layer SCL. The selective channel layer SCL can be retained in the first hole HO1. The upper portion of the fifth material layer ML5 can be removed to expose the top surface of the first mask layer MA1.

[0084] Reference Figure 13 The first mask layer MA1 can be removed. The first mask layer MA1 can be removed to expose the top surface of the initial selection layer pSE. The first mask layer MA1 can be removed to expose the outer wall of the gate insulating layer GI.

[0085] Reference Figure 14 A sixth material layer ML6 can be formed covering the top surface of the initial selection layer pSE, the outer wall of the gate insulating layer GI, and the top surface of the selection channel layer SCL. The sixth material layer ML6 can be conformally formed on the top surface of the initial selection layer pSE, the outer wall of the gate insulating layer GI, and the top surface of the selection channel layer SCL. The sixth material layer ML6 may include an insulating material such as an oxide.

[0086] Reference Figure 15 The sixth material layer ML6 can be etched. The sixth material layer ML6 can be etched to form the spacer SPA. The sixth material layer ML6 can be etched to re-expose the top surface of the initial selection layer pSE. The sixth material layer ML6 can be etched to re-expose the top surface of the selection channel layer SCL. The gate insulating layer GI can be etched concurrently with the etching of the sixth material layer ML6. The gate insulating layer GI can be etched to expose the sidewalls of the selection channel layer SCL.

[0087] Reference Figure 16A buffer sacrificial layer BFL can be formed, covering the top surface of the initial selection layer pSE, the top surface and sidewalls of each spacer SPA, the top surface of each gate insulating layer GI, and the top surface and sidewalls of each selection channel layer SCL. The buffer sacrificial layer BFL may include a cover portion CV and a connecting portion CN. The cover portion CV may cover the top surface and sidewalls of each spacer SPA, each gate insulating layer GI, and each selection channel layer SCL. The connecting portion CN may connect to the cover portion CV. The connecting portion CN may be formed on the top surface of the initial selection layer pSE. The cover portion CV may have a width that decreases toward the portion adjacent to the initial selection layer pSE and the stacked structure STA. For example, the cover portion CV may have a width that decreases toward the portion adjacent to the initial selection layer pSE and the stacked structure STA in a first direction D1.

[0088] A first trench TR1 or a second trench TR2 may be defined between cover portions CV. The first trench TR1 may be defined between adjacent cover portions CV disposed between adjacent slit structures SLS. The second trench TR2 may be defined between each pair of cover portions CV disposed on both sides of the slit structures SLS. Each of the first trench TR1 and the second trench TR2 may be defined by the sidewalls of adjacent cover portions CV and the top surface of the connecting portion CN. Due to the shape of the cover portions CV, each of the first trench TR1 and the second trench TR2 may have a width that increases toward the portion adjacent to the connecting portion CN, the preliminary selection layer pSE, and the laminated structure STA. For example, the first trench TR1 and the second trench TR2 may have a width that increases toward the portion adjacent to the connecting portion CN, the preliminary selection layer pSE, and the laminated structure STA in a first direction D1.

[0089] The buffer sacrificial layer BFL can be formed by depositing a first deposition material with relatively poor step coverage. Because the first deposition material has relatively poor step coverage, each of the first trench TR1 and the second trench TR2, as well as the coverage portion CV, can be formed with a partially varied width. The buffer sacrificial layer BFL can have etch selectivity relative to the initial selection layer pSE. For example, the buffer sacrificial layer BFL may include an amorphous carbon layer.

[0090] A third mask layer MA3 may be formed above the buffer sacrificial layer BFL. The third mask layer MA3 may include a first opening OP1 exposing the first trench TR1 and the second trench TR2. The step of forming the third mask layer MA3 may include: forming a photoresist layer covering the buffer sacrificial layer BFL; and forming the first opening OP1 in the photoresist layer. The first opening OP1 may expose the top surface of the connecting portion CN, the sidewalls of the covering portion CV, and a portion of the top surface of the covering portion CV. A portion of the covering portion CV may overlap with the first opening OP1.

[0091] Figure 17B It is along Figure 17A The cross-sectional view taken by line A2-A2′.

[0092] Reference Figure 17A and Figure 17B The third mask layer MA3 can be used as an etching mask to etch the buffer sacrificial layer BFL. The buffer sacrificial layer BFL can be etched to remove the portion of the covered portion CV that overlaps with the first opening OP1. The buffer sacrificial layer BFL can be etched to remove the connecting portion CN.

[0093] A portion of the cover portion CV of each buffer sacrificial layer BFL and the connecting portion CN can be removed to extend the first trench TR1 and the second trench TR2. The top surface of the initial selection layer pSE can be exposed through the extended first trench TR1 and second trench TR2. Since a portion of the cover portion CV of each buffer sacrificial layer BFL can be removed, the cover portion CV can be modified. The modified cover portion CV can have an increased width toward the portion adjacent to the initial selection layer pSE and the stacked structure STA.

[0094] During the etching process of the buffer sacrificial layer BFL, the portion of the cover portion CV that overlaps with the first opening OP1 can be used as an etching barrier layer. Therefore, even if the first opening OP1 in the third mask layer MA3 has a relatively large width in the first direction D1, each of the extended first trench TR1 and the second trench TR2 can be formed to have a relatively small width in the first direction D1. After etching the buffer sacrificial layer BFL, the third mask layer MA3 can be removed.

[0095] Figure 18B It is along Figure 18A The cross-sectional view taken by line A3-A3′.

[0096] Reference Figure 18A and Figure 18BThe initial selection layer pSE can be etched through the first trench TR1 and the second trench TR2. The initial selection layer pSE can be etched to divide it into initial selection patterns pSP. A first isolation gap DG1 and a second isolation gap DG2 can be defined between the initial selection patterns pSP. The initial selection patterns pSP can be spaced apart from each other in a first direction D1 by the first isolation gap DG1 and the second isolation gap DG2. Each of the initial selection patterns pSP can surround multiple selection channel layers SCL.

[0097] After etching the initial selection layer pSE, the cover portion CV of the buffer sacrificial layer BFL can be removed. The cover portion CV of the buffer sacrificial layer BFL can be removed to expose the top surface of the initial selection pattern pSP, the top surface and sidewalls of the spacer SPA, the top surface of the gate insulating layer GI, and the top surface and sidewalls of the selection channel layer SCL.

[0098] Reference Figure 19 A diffused metal layer DML can be formed covering the top surface and sidewalls of the initial selected pattern pSP, the top surface and sidewalls of the spacer SPA, the top surface of the gate insulating layer GI, and the top surface and sidewalls of the selective channel layer SCL. The diffused metal layer DML can be conformally formed on the top surface and sidewalls of the initial selected pattern pSP, the top surface and sidewalls of the spacer SPA, the top surface of the gate insulating layer GI, and the top surface and sidewalls of the selective channel layer SCL.

[0099] The diffusion metal layer (DML) may include a metallic material such as nickel-platinum. For example, the nickel-platinum composition included in the diffusion metal layer (DML) may be NiPt. The diffusion metal layer (DML) may contain a metal that can diffuse into the selective channel layer (SCL) and the preliminary selective pattern (pSP) at a temperature below that at which fumes can be generated in the conductive pattern (CP). For example, the diffusion metal layer (DML) may contain nickel that can diffuse into the selective channel layer (SCL) and the preliminary selective pattern (pSP).

[0100] Figure 20B yes Figure 20A A magnified view of region C5.

[0101] Reference Figure 20A and Figure 20B It can form Select Overlay Pattern (SCP) and Select Pattern (SP).

[0102] The composition of a portion of the initial selected pattern pSP can be altered to form a selected pattern pSP comprising a first conductive portion CO1 and a second conductive portion CO2. The composition of the portion of the initial selected pattern pSP adjacent to the diffused metal layer DML can be altered to form a second conductive portion CO2 of the selected pattern pSP. The remaining portion of the initial selected pattern pSP with unchanged composition can be defined as the first conductive portion CO1.

[0103] The composition of a portion of the Selective Channel Layer (SCL) can be altered to create a Selective Overlay Pattern SCP. The composition of the portion of the Selective Channel Layer (SCL) adjacent to the Diffused Metal Layer (DML) can also be altered to create a Selective Overlay Pattern SCP.

[0104] The second conductive portion CO2 and the selective overlay pattern SCP can be formed by heat treatment. The heat treatment can be performed at a temperature less than or equal to 450°C. Metals included in the diffusion metal layer DML can diffuse into the selective channel layer SCL and the initial selective pattern pSP, and the second conductive portion CO2 of the selective overlay pattern SCP and the selective pattern SP can be formed by heat treatment. For example, nickel included in the diffusion metal layer DML can diffuse into the selective channel layer SCL and the initial selective pattern pSP by heat treatment. For example, the nickel diffused into the selective channel layer SCL and the initial selective pattern pSP can be bonded to silicon in the selective channel layer SCL and the initial selective pattern pSP.

[0105] The second conductive portion CO2 of the selected overlay pattern SCP and the selected pattern SP may include nickel silicide. For example, the nickel silicide included in the second conductive portion CO2 of the selected overlay pattern SCP and the selected pattern SP may be composed of NiSi. The selected overlay pattern SCP may form an ohmic contact with the selected channel layer SCL. The second conductive portion CO2 of the selected pattern SP may form an ohmic contact with the first conductive portion CO1.

[0106] The composition of a portion of the bottom surface of the contact spacer SPA and the sidewall of the gate insulating layer GI in the preliminary selection pattern pSP can remain unchanged, and this portion in the preliminary selection pattern pSP can be defined as the protrusion PT of the first conductive portion CO1.

[0107] The selected pattern SP can be categorized into first selected pattern SP1 and second selected pattern SP2.

[0108] Reference Figure 21 The diffused metal layer DML can be removed. The diffused metal layer DML can be removed to expose the top surface and sidewalls of the selected pattern SP, the top surface and sidewalls of the spacer SPA, the top surface of the gate insulation layer GI, and the top surface and sidewalls of the selected overlay pattern SCP.

[0109] Reference Figure 22A second insulating layer 120 can be formed to cover the top surface and sidewalls of the selected pattern SP, the top surface and sidewalls of the spacer SPA, the top surface of the gate insulating layer GI, and the sidewalls of the selected cover pattern SCP. The second insulating layer 120 can cover the slit structure SLS. The second insulating layer 120 can fill the first isolation gap DG1 and the second isolation gap DG2, and can include an insulating material. For example, the second insulating layer 120 can include an oxide.

[0110] A third insulating layer 130 may be formed over the second insulating layer 120. The third insulating layer 130 may cover a selectively overlaid pattern SCP. The third insulating layer 130 may include an insulating material. For example, the third insulating layer 130 may include a nitride.

[0111] A fourth insulating layer 140 may be formed over the third insulating layer 130. The fourth insulating layer 140 may include an insulating material. For example, the fourth insulating layer 140 may include an oxide.

[0112] Subsequently, a reference can be formed in the third insulating layer 130. Figure 1B and Figure 1C The bit line contact BCT structure can be formed in the fourth insulating layer 140. Figure 1B and Figure 1C The bit line BL.

[0113] According to an embodiment of the method for manufacturing a semiconductor device according to this disclosure, the second conductive portion CO2 of the selection pattern SP and the selection overlay pattern SCP can be formed by heat treatment at a relatively low temperature. Therefore, the characteristic changes of the memory cell and selection transistor caused by heat treatment at high temperatures can be mitigated.

[0114] Figure 23 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment.

[0115] Reference Figure 23 The memory system 1100 according to the embodiment may include a memory device 1120 and a memory controller 1110.

[0116] The memory device 1120 may include a semiconductor device according to an embodiment. The memory device 1120 may be a multi-chip package including a plurality of flash memory chips.

[0117] Memory controller 1110 can be configured to control memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction code (ECC) circuitry 1114, and memory interface 1115. SRAM 1111 can serve as operating memory for CPU 1112, which performs general control operations for data exchange with memory controller 1110. Host interface 1113 may include a data exchange protocol for host access to memory system 1100. Additionally, ECC circuitry 1114 can detect and correct errors in data read from memory device 1120, and memory interface 1115 can perform interfacing with memory device 1120. Furthermore, memory controller 1110 may also include read-only memory (ROM) for storing code data for host interfacing.

[0118] The memory system 1100 with the above configuration can be a solid-state drive (SSD) or a memory card that combines a memory device 1120 and a memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external device (e.g., a host) via one of a variety of interface protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), PCI-E, Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0119] Figure 24 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment.

[0120] Reference Figure 24 The computing system 1200 according to the embodiment may include a CPU 1220, random access memory (RAM) 1230, user interface 1240, modem 1250, and memory system 1210 electrically connected to a system bus 1260. Additionally, when the computing system 1200 is a mobile device, it may further include a battery for providing operating voltage to the computing system 1200, and may also include an application chipset, camera image processor, mobile DRAM, etc.

[0121] The memory system 1210 may include components similar to those described above. Figure 23 The memory device 1212 and memory controller 1211 described herein.

[0122] According to embodiments of this disclosure, because the semiconductor device is configured such that the selected pattern includes nickel silicide, RC delay can be minimized.

[0123] Cross-reference to related applications

[0124] This application claims priority to Korean Patent Application No. 10-2020-0121645, filed on September 21, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A stacked structure comprising multiple conductive patterns and multiple insulating patterns that are alternately stacked on top of each other; A unit plug that passes through the stacked structure; Select plug, which is connected to the unit plug; as well as Select a pattern that surrounds the selected plug. The selected pattern includes a first conductive portion and a second conductive portion covering the sidewalls and top surface of the first conductive portion. The plurality of conductive patterns, the first conductive portion, and the second conductive portion comprise different materials. The selection plug protrudes further than the selection pattern in the opposite direction to the unit plug. The semiconductor device further includes a spacer surrounding the upper portion of the select plug, the upper portion of the select plug being positioned above the select pattern, and The bottom surface of the spacer contacts the top surface of the selected pattern.

2. The semiconductor device according to claim 1, wherein, The selection plug includes a selection channel layer and a selection overlay pattern located above the selection channel layer, and The selected overlay pattern comprises the same material as the second conductive portion.

3. The semiconductor device according to claim 2, wherein, The select plug also includes a gate insulating layer surrounding the select channel layer and the select overlay pattern, and The gate insulating layer passes through the selected pattern.

4. The semiconductor device according to claim 1, wherein, The second conductive portion comprises a metal silicide.

5. The semiconductor device according to claim 4, wherein, The first conductive portion comprises polycrystalline silicon.

6. The semiconductor device according to claim 1, wherein, The first conductive portion includes a protrusion that passes through the second conductive portion.

7. A semiconductor device comprising: A stacked structure comprising multiple conductive patterns and multiple insulating patterns that are alternately stacked on top of each other; A unit plug that passes through the stacked structure; Select plug, which is connected to the unit plug; as well as Select a pattern that surrounds the selected plug. The selected pattern includes a first conductive portion and a second conductive portion covering the sidewalls and top surface of the first conductive portion. The select plug includes a select channel layer connected to the unit plug and a select overlay pattern located above the select channel layer. The second conductive portion and the selected overlay pattern are made of the same material. The selection plug protrudes further than the selection pattern in the opposite direction to the unit plug. The semiconductor device further includes a spacer surrounding the upper portion of the select plug, the upper portion of the select plug being positioned above the select pattern, and The bottom surface of the spacer contacts the top surface of the selected pattern.

8. The semiconductor device according to claim 7, wherein, The first conductive portion, the second conductive portion, and the plurality of conductive patterns comprise different materials.

9. The semiconductor device according to claim 7, wherein, The unit plug includes a unit channel layer and a unit overlay pattern located above the unit channel layer, and The lowermost portion of the selected channel layer is located within the unit coverage pattern.

10. The semiconductor device according to claim 7, wherein, The second conductive portion and the selected overlay pattern comprise metal silicides.

11. The semiconductor device according to claim 9, wherein, The top surface of the unit covering pattern contacts the bottom surface of the selected channel layer, and The top surface of the unit covering pattern and the bottom surface of the selected channel layer are curved.

12. The semiconductor device according to claim 7, wherein, The unit plug includes a unit channel layer, a tunnel insulation layer surrounding the unit channel layer, a data storage layer surrounding the tunnel insulation layer, a unit overlay pattern located above the unit channel layer, and a barrier layer surrounding the data storage layer and the unit overlay pattern. The selected channel layer contacts the cell cover pattern and the barrier layer.

13. A semiconductor device comprising: A stacked structure comprising multiple conductive patterns and multiple insulating patterns that are alternately stacked on top of each other; A unit plug that passes through the stacked structure; Select plug, which is connected to the unit plug; as well as Select a pattern that surrounds the selected plug. The selected pattern includes a first conductive portion and a second conductive portion covering the sidewalls and top surface of the first conductive portion. The second conductive portion comprises a metal silicide. The selection plug protrudes further than the selection pattern in the opposite direction to the unit plug. The semiconductor device further includes a spacer surrounding the upper portion of the select plug, the upper portion of the select plug being positioned above the select pattern, and The bottom surface of the spacer contacts the top surface of the selected pattern.

14. The semiconductor device of claim 13, further comprising a first insulating layer covering the selected pattern. in, The first conductive portion is spaced apart from the first insulating layer by the second conductive portion.

15. The semiconductor device of claim 13, further comprising a second insulating layer covering the cell plug. in, The select plug includes a select channel layer passing through the second insulating layer and a gate insulating layer surrounding the select channel layer, and The bottom surface of the gate insulating layer is disposed in the second insulating layer.

16. The semiconductor device according to claim 13, wherein, The select plug includes a select channel layer, a select overlay pattern above the select channel layer, and a gate insulating layer surrounding the select channel layer.

17. The semiconductor device according to claim 16, wherein, The height of the bottom surface of the selected overlay pattern is lower than the height of the top surface of the gate insulating layer.

18. The semiconductor device according to claim 17, wherein, The height of the top surface of the gate insulating layer is higher than the height of the top surface of the selected channel layer.

19. The semiconductor device of claim 13, further comprising a bit line contact connected to the select plug. in, The selection plug includes a selection channel layer and a selection overlay pattern located above the selection channel layer, and The selected overlay pattern connects the bit line contact to the selected channel layer.

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