Semiconductor element and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a conductive layer disposed on a semiconductor substrate; and a conductive contact disposed on the conductive layer. The semiconductor device also includes a conductive line disposed on the conductive contact. In a first cross-sectional view along a longitudinal axis of the conductive line, an upper portion of the conductive contact has a tapered profile; and in a second cross-sectional view along a line segment orthogonal to the longitudinal axis of the conductive line, the upper portion of the conductive contact has a non-tapered profile.

Description

Technical Field

[0001] This application claims priority to and the benefit of U.S. regular application No. 17 / 031,073, filed on September 24, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a conductive contact point with a tapered profile and a method for manufacturing the same. Background Art

[0003] Semiconductor components are indispensable for many modern applications. With advancements in electronics technology, semiconductor components are becoming increasingly smaller, while simultaneously providing improved functionality and incorporating a greater number of integrated circuits. As semiconductor components become increasingly miniaturized, different types and sizes of semiconductor components, each fulfilling a different function, are being integrated and packaged into a single module. Furthermore, numerous manufacturing steps are required to integrate these various types of semiconductor devices.

[0004] However, the manufacturing and integration of semiconductor devices involves many complex steps and operations. Integration within semiconductor devices is becoming increasingly complex. This increased complexity in semiconductor device manufacturing and integration can lead to numerous defects. Consequently, there is a need for continuous improvement in semiconductor device manufacturing processes to address these defects.

[0005] The above description of “prior art” is merely to provide background technology, and does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0006] One embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a conductive layer disposed on a semiconductor substrate; and a conductive contact disposed on the conductive layer. The semiconductor device also includes a conductive line disposed on the conductive contact. In a first cross-sectional view along a longitudinal axis of the conductive line, an upper portion of the conductive contact has a tapered profile; and in a second cross-sectional view along a line segment perpendicular to the longitudinal axis of the conductive line, the upper portion of the conductive contact has a non-tapered profile.

[0007] In one embodiment, the tapered profile of the upper portion of the conductive contact in the first cross-sectional view tapers gradually from an upper surface of the conductive contact. In one embodiment, a lower portion of the conductive contact has a non-tapered profile in the first cross-sectional view. In one embodiment, an interface area between the conductive contact and the conductive line is greater than an interface area between the conductive contact and the conductive layer. In one embodiment, the conductive contact is completely covered by the conductive line. In one embodiment, a width of the conductive line in the second cross-sectional view is approximately the same as a width of the conductive contact. In one embodiment, the semiconductor element further includes a source / drain region disposed in the semiconductor substrate, wherein the conductive line is electrically connected to the source / drain region via the conductive contact and the conductive layer.

[0008] Another embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a conductive layer disposed on a semiconductor substrate; and a conductive wire disposed on the conductive layer. The semiconductor element also includes a conductive contact point disposed between the conductive layer and the conductive wire, and electrically connecting the conductive layer and the conductive wire. The conductive contact point includes: a base; and a first expansion portion and a second expansion portion extending laterally from the base. The first expansion portion and the second expansion portion are disposed separately from the conductive layer, and wherein the first expansion portion and the second expansion portion have a tapered profile, gradually becoming thinner from the conductive wire toward the conductive layer.

[0009] In one embodiment, the first expansion portion of the conductive contact point and the second expansion portion of the conductive contact point are separately provided, and the first expansion portion and the second expansion portion are completely covered by the conductive wire. In one embodiment, the first expansion portion and the second expansion portion of the conductive contact point are in direct contact with the conductive wire. In one embodiment, the upper surfaces of the first expansion portion and the second expansion portion of the conductive contact point are approximately coplanar with an upper surface of the base of the conductive contact point. In one embodiment, in a cross-sectional view along a longitudinal axis of the conductive wire, a height of the base of the conductive contact point is greater than a height of the first expansion portion of the conductive contact point and a height of the second expansion portion of the conductive contact point. In one embodiment, the first expansion portion and the second expansion portion of the conductive contact point each have a curved side wall.

[0010] Another embodiment of the present disclosure provides a method for preparing a semiconductor element. The preparation method includes forming a conductive layer on a semiconductor substrate; and forming a dielectric layer to cover the conductive layer. The preparation method also includes etching the dielectric layer to form an opening to expose the conductive layer; and etching the dielectric layer to form a first recess and a second recess connected to the opening. A depth of the opening is greater than a depth of the first recess and a depth of the second recess, and wherein the first recess and the second recess have a tapered profile that gradually tapers toward the conductive layer. The preparation method also includes forming a conductive contact point on the conductive layer. The opening, the first recess, and the second recess are filled with the conductive contact point. In addition, the preparation method includes forming a conductive line on the conductive contact point.

[0011] In one embodiment, the opening has a non-tapered profile. In one embodiment, etching the dielectric layer to form the first and second recesses includes: depositing a liner film to cover the dielectric layer and line the opening; etching the liner film to expose portions of the dielectric layer adjacent to the opening; and etching portions of the dielectric layer exposed through the liner film to form the first and second recesses. In one embodiment, after etching the liner film, the conductive layer is exposed. In one embodiment, the fabrication method further includes removing the liner film after forming the first and second recesses. In one embodiment, forming the conductive contact on the conductive layer includes: forming a conductive material on the dielectric layer, wherein the opening, the first recess, and the second recess are filled with the conductive material. Furthermore, forming the conductive contact on the conductive layer includes: polishing the conductive material to form the conductive contact. In one embodiment, an upper surface area of ​​the conductive contact point is larger than a lower surface area of ​​the conductive contact point, and the upper surface of the conductive contact point is completely covered by the conductive line.

[0012] The present disclosure provides multiple embodiments of a semiconductor device. In some embodiments, the semiconductor device includes a conductive contact and a conductive line. The conductive contact is disposed on a conductive layer, and the conductive line is disposed on the conductive contact. In a cross-sectional view along a longitudinal axis of the conductive line, an upper portion of the conductive contact has a tapered profile. This reduces contact resistance between the conductive contact and the conductive line, thereby improving overall device performance.

[0013] The above has provided a fairly broad overview of the technical features and advantages of the present disclosure, allowing for a better understanding of the detailed description of the present disclosure below. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure pertains that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure pertains that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete understanding of the disclosure of this application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which like reference numerals refer to like elements.

[0015] Figure 1 A schematic top view of a semiconductor device illustrating some embodiments of the present disclosure is shown.

[0016] Figure 2 The semiconductor device illustrating some embodiments of the present disclosure is Figure 1 Schematic cross-sectional view of line segment XX'.

[0017] Figure 3 The semiconductor device illustrating some embodiments of the present disclosure is Figure 1 Schematic cross-sectional view of line segment Y-Y'.

[0018] Figure 4 A schematic cross-sectional view of an improved semiconductor device illustrating some embodiments of the present disclosure is shown.

[0019] Figure 5 A schematic flow chart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure is provided.

[0020] Figure 6 A top view schematically illustrates an intermediate stage of etching a dielectric layer to form a plurality of openings during the formation of the semiconductor device according to some embodiments of the present disclosure.

[0021] Figure 7 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 6 Schematic cross-sectional view of line segment XX'.

[0022] Figure 8 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 6 Schematic cross-sectional view of line segment Y-Y'.

[0023] Figure 9A schematic top view illustrating an intermediate stage of forming a liner film on the dielectric layer and lining the opening during formation of the semiconductor device according to some embodiments of the present disclosure is shown.

[0024] Figure 10 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 9 Schematic cross-sectional view of line segment XX'.

[0025] Figure 11 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 9 Schematic cross-sectional view of line segment Y-Y'.

[0026] Figure 12 A top view schematically illustrates an intermediate stage of forming a patterned mask on the liner film during formation of the semiconductor device according to some embodiments of the present disclosure.

[0027] Figure 13 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 12 Schematic cross-sectional view of line segment XX'.

[0028] Figure 14 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 12 Schematic cross-sectional view of line segment Y-Y'.

[0029] Figure 15 A cross-sectional view illustrating an intermediate stage of etching the liner film to expose the dielectric layer by using the patterned mask as a mask during formation of the semiconductor device according to some embodiments of the present disclosure is provided.

[0030] Figure 16 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 15 Schematic cross-sectional view of line segment XX'.

[0031] Figure 17 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 15 Schematic cross-sectional view of line segment Y-Y'.

[0032] Figure 18 A schematic cross-sectional view illustrating an intermediate stage of etching the dielectric layer exposed through the liner film during formation of the semiconductor device according to some embodiments of the present disclosure.

[0033] Figure 19 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 18 Schematic cross-sectional view of line segment XX'.

[0034] Figure 20 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 18 Schematic cross-sectional view of line segment Y-Y'.

[0035] Figure 21 A schematic cross-sectional view illustrating an intermediate stage of removing the liner film during formation of the semiconductor device according to some embodiments of the present disclosure.

[0036] Figure 22 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 21 Schematic cross-sectional view of line segment XX'.

[0037] Figure 23 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 21 Schematic cross-sectional view of line segment Y-Y'.

[0038] Figure 24 A schematic cross-sectional view illustrating an intermediate stage of forming a conductive contact during the formation of the semiconductor device according to some embodiments of the present disclosure is shown.

[0039] Figure 25 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 24 Schematic cross-sectional view of line segment XX'.

[0040] Figure 26 An intermediate stage during the formation of the semiconductor device according to some embodiments of the present disclosure is illustrated. Figure 24 Schematic cross-sectional view of line segment Y-Y'.

[0041] The description of the accompanying drawings is as follows:

[0042] 10: Preparation method

[0043] 100a: semiconductor components

[0044] 100b: semiconductor components

[0045] 101: Semiconductor substrate

[0046] 103: Insulation structure

[0047] 105: Source / drain region

[0048] 107: Dielectric layer

[0049] 109: Conductive layer

[0050] 111: Dielectric layer

[0051] 111S: Sloped sidewalls

[0052] 120: Opening

[0053] 123: Liner film

[0054] 125: Patterned Mask

[0055] 130: Opening

[0056] 143: Base

[0057] 145a: First expansion portion

[0058] 145a': first expansion portion

[0059] 145b: Second expansion portion

[0060] 145b': Second expansion portion

[0061] 147: Conductive contact point

[0062] 147': Conductive contact point

[0063] 147B: Lower surface area

[0064] 147'B: Lower surface area

[0065] 147L: lower part

[0066] 147'L: Lower part

[0067] 147T: Upper surface area

[0068] 147'T: Upper surface area

[0069] 147U: Upper

[0070] 147'U: upper part

[0071] 151: Dielectric layer

[0072] 153: Conductive thread

[0073] D1: Depth

[0074] D2: Depth

[0075] D3: Depth

[0076] H1: Height

[0077] H2: Height

[0078] H3: Height

[0079] L1: length

[0080] L2: length

[0081] S11: Steps

[0082] S13: Steps

[0083] S15: Steps

[0084] S17: Steps

[0085] S19: Steps

[0086] S21: Steps

[0087] S23: Steps

[0088] S25: Steps

[0089] S27: Steps

[0090] W: width

[0091] θ: tilt angle DETAILED DESCRIPTION

[0092] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the components are not limited to the disclosed ranges or values, but may depend on the process conditions and / or the desired properties of the device. In addition, the following description of a first feature being formed "on" or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing the first and second features from being in direct contact. For the sake of brevity and clarity, various features may be drawn at different scales. In the accompanying drawings, some layers / features may be omitted for simplicity.

[0093] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0094] Figure 1 A schematic top view of a semiconductor device 100 a is shown, illustrating some embodiments of the present disclosure. Figure 2The semiconductor device 100a illustrating some embodiments of the present disclosure is Figure 1 Schematic cross-sectional view of line segment XX'. Figure 3 The semiconductor device 100a illustrating some embodiments of the present disclosure is Figure 1 Schematic cross-sectional view of line segment Y-Y'.

[0095] like Figures 1 to 3 As shown, semiconductor device 100a includes a semiconductor substrate 101, multiple source / drain regions 105, multiple conductive layers 109, multiple conductive contacts 147, and multiple conductive lines 153. Multiple source / drain regions 105 are disposed in semiconductor substrate 101; multiple conductive layers 109 are disposed on the source / drain regions 105; multiple conductive contacts 147 are disposed on the conductive layers 109; and multiple conductive lines 153 are disposed on the conductive contacts 147. In some embodiments, the conductive lines 153 are electrically connected to the source / drain regions 105 via the conductive contacts 147 and the conductive layers 109. In some embodiments, each conductive contact 147 includes a base 143, a first expanded portion 145a, and a second expanded portion 145b.

[0096] In some embodiments, the semiconductor device 100a includes an insulating structure 103 and multiple active regions (not shown); the insulating structure 103 is disposed in the semiconductor substrate 101; the active regions are defined by the insulating structure 103. The source / drain regions 105 are disposed in the active regions. In some embodiments, the semiconductor device 100a also includes a dielectric layer 107, a dielectric layer 111, and a dielectric layer 151; the dielectric layer 107 is disposed on the semiconductor substrate 101 and surrounds the conductive layer 109; the dielectric layer 111 is disposed on the dielectric layer 107 and surrounds the conductive contact 147 (including the base 143, the first expansion portion 145a, and the second expansion portion 145b); and the dielectric layer 151 is disposed on the dielectric layer 111 and surrounds the conductive line 153.

[0097] Please refer to Figure 1 According to some embodiments, the conductive lines 153 are parallel to each other. In some embodiments, the conductive lines 153 extend along the X-direction. In particular, each conductive line 153 has a longitudinal axis along the X-direction, and section line XX' is the longitudinal axis of one of the conductive lines 153. Furthermore, section line YY' extends along the Y-direction. That is, section line YY' is orthogonal to the longitudinal axis of the conductive line 153.

[0098] Furthermore, according to some embodiments, such as Figure 2As shown, in a cross-sectional view taken along the longitudinal axis of the conductive line 153, an upper portion 147U of the conductive contact 147 has a tapered profile, while a lower portion 147L of the conductive contact 147 has a non-tapered profile. Specifically, the tapered profile of the upper portion 147U of the conductive contact 147 tapers gradually from the conductive line 153 toward the conductive layer 109. In some embodiments, the upper surface area 147T of the conductive contact 147 is larger than the lower surface area 147B of the conductive contact 147. Consequently, the contact resistance between the conductive contact 147 and the conductive line 153 can be reduced.

[0099] Steering Figure 3 According to some embodiments, in a cross-sectional view taken along a line segment perpendicular to the longitudinal axis of the conductive line 153, the conductive contact point 147 has a non-tapered profile. In some embodiments, the cross-sectional view is depicted along the line segment perpendicular to the longitudinal axis of the conductive line 153. In some embodiments, the cross-sectional view is cut through the base 143 of the conductive contact point 147, but not through the first bulged portion 145a and the second bulged portion 145b of the conductive contact point 147. Therefore, the first bulged portion 145a and the second bulged portion 145b are not shown. Figure 3 middle.

[0100] Furthermore, according to some embodiments, such as Figure 1 and Figure 3 As shown, each conductive contact point 147 has a width that is substantially the same as the width (denoted by W) of a corresponding conductive line 153. In this disclosure, the term "substantially" preferably means at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%. Because the first and second expanded portions 145a, 145b do not extend beyond the edges of the corresponding conductive lines 153, crosstalk (e.g., signal interference) between adjacent conductive lines 153 or between adjacent conductive contact points 147 can be prevented or reduced.

[0101] In some embodiments, semiconductor device 100a is a dynamic random access memory (DRAM), and the conductive lines 153 serve as multiple bit lines (BLs) or storage nodes for the DRAM. In some embodiments, the conductive contact 147 has multiple expansion portions (e.g., first expansion portion 145a and second expansion portion 145b) extending outward from the base 143 and laterally along the longitudinal axis of the conductive line 153. Consequently, the upper surface areas of the contacts 147 (e.g., upper surface areas 147T) are larger than the lower surface areas of the conductive contacts 147 (e.g., lower surface areas 147B), thereby reducing the contact resistance between the conductive contacts 147 and the conductive lines 153. Furthermore, the conductive lines 147 do not expand beyond the edges of the conductive lines 153, thereby avoiding or reducing crosstalk between adjacent conductive lines 153 or between adjacent conductive contacts 147. Consequently, overall device performance can be improved.

[0102] Figure 4 The cross-sectional view of an improved semiconductor device 100b is shown in some embodiments of the present disclosure. The improved semiconductor device 100b is another embodiment of the semiconductor device 100a. Figure 2 , Figure 4 Along parallel to Figure 1 For the sake of consistency and clarity, the line X-X' is a sectional view of a line segment. Figure 2 and Figure 4 Similar components will be marked with the same component number.

[0103] Similar to semiconductor device 100b, improved semiconductor device 100b includes a conductive contact 147' having a first expanded portion 145a' and a second expanded portion 145b' that extend laterally outward from base 143. In some embodiments, an upper portion 147'U of conductive contact 147' has a tapered profile, and a lower portion 147'L of conductive contact 147' has a non-tapered profile. In particular, the tapered profile of upper portion 147'U of conductive contact 147' tapers from conductive line 153 toward conductive layer 109. In some embodiments, an upper surface area 147'T of conductive contact 147' is larger than a lower surface area 147'B of conductive contact 147'.

[0104] According to some embodiments, Figure 4 As shown, one difference between the semiconductor devices 100a and 100b is that the first expansion portion 145a' and the second expansion portion 145b' of the conductive contact 147' of the improved semiconductor device 100b each have curved sidewalls.

[0105] Figure 5A flow chart illustrating a method 10 for fabricating a semiconductor device (including a semiconductor device 100a and an improved semiconductor device 100b) according to some embodiments of the present disclosure is provided. The method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, and S27. Figure 5 Steps S11 to S27 are described in detail with reference to the following figures.

[0106] Figure 6 、 Figure 9 、 Figure 12 、 Figure 15 、 Figure 18 、 Figure 21 as well as Figure 24 schematic top views illustrating various intermediate stages in the formation of a semiconductor device 100a according to some embodiments, and Figure 7 、 Figure 8 、 Figure 10 、 Figure 11 、 Figure 13 、 Figure 14 、 Figure 16 、 Figure 17 、 Figure 19 、 Figure 20 、 Figure 22 、 Figure 23 、 Figure 25 as well as Figure 26 Schematic cross-sectional views of various intermediate stages in the formation of the semiconductor device 100a in some embodiments are illustrated. It should be understood that Figure 7 、 Figure 10 、 Figure 13 、 Figure 16 、 Figure 19 、 Figure 22 and Figure 25 For respectively Figure 6 、 Figure 9 、 Figure 12 、 Figure 15 、 Figure 18 、 Figure 21 as well as Figure 24 A schematic cross-sectional view of the section line X-X', and Figure 8 、 Figure 11 、 Figure 14 、 Figure 17 、 Figure 20 、 Figure 23 and Figure 26 For respectively Figure 6 、 Figure 9 、 Figure 12 、 Figure 15 、 Figure 18 、 Figure 21 as well as Figure 24 Schematic cross-sectional view of the section line Y-Y'.

[0107] like Figure 6 、 Figure 7 and Figure 8 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 may include an elementary semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0108] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 includes an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SIO) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is disposed on the substrate, and the semiconductor layer is disposed on the buried oxide layer. The SIO substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SIO substrate may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0109] In some embodiments, an insulating structure 103 is formed in the semiconductor substrate 101 to define a plurality of active regions, and the insulating structure 103 is a shallow trench isolation (STI) structure. Furthermore, the insulating structure 103 comprises silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials. Forming the insulating structure 103 may include forming a patterned mask (not shown) on the semiconductor substrate 101; etching the semiconductor substrate 101 using the patterned mask as a mask to form a plurality of openings (not shown); depositing a dielectric material in the openings and on the semiconductor substrate 101; and polishing the dielectric material until the semiconductor substrate 101 is exposed.

[0110] Furthermore, the source / drain regions 105 are formed in the active region. In some embodiments, the source / drain regions 105 are formed using one or more ion implantation processes. Depending on the conductivity type of the semiconductor device 100a, P-type dopants or N-type dopants may be implanted into the active region to form the source / drain regions 105. P-type dopants include, for example, boron (B), gallium (Ga), or indium (In), and N-type dopants include, for example, phosphorus (P) or arsenic (As).

[0111] According to some embodiments, Figure 6 、 Figure 7 and Figure 8 As shown, after the source / drain regions 105 and the insulating structure 103 are formed, the conductive layer 109 and the dielectric layer 107 surrounding the conductive layer 109 are formed on the semiconductor substrate 101. The individual steps are shown in FIG. Figure 5 Step S11 of method 10 is shown. Each conductive layer 109 can be a single layer or multiple layers. In some embodiments, the conductive layer 109 comprises aluminum, copper, tungsten, titanium, tantalum, or other applicable conductive materials. Furthermore, the dielectric layer 107 can be a single layer or multiple layers, and the dielectric layer 107 can comprise silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials.

[0112] The manufacturing technology of the conductive layer 109 and the dielectric layer 107 includes depositing the dielectric layer 107 on the semiconductor substrate 101; etching the dielectric layer 107 to form a plurality of openings (not shown) to expose the semiconductor substrate 101; depositing a conductive material (not shown) in the openings and on the dielectric layer 107; and grinding the conductive material to form the conductive layer 109 surrounded by the dielectric layer 107.

[0113] The deposition process for the dielectric layer 107 may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PV) process, an atomic layer deposition (ALD) process, a spin coating process, or other applicable processes. The dielectric layer 107 may be etched by a wet etching process, a dry etching process, or a combination thereof. The deposition process for the conductive material may include a CVD process, a PVD process, an ALD process, a metal-organic chemical vapor deposition (MOCVD) process, a sputtering process, a plating process, or other applicable processes. The conductive material may be polished by a chemical mechanical polishing (CMP) process.

[0114] Then, according to some embodiments, a dielectric layer 111 is formed on the dielectric layer 107, and the conductive layer 109 is covered by the dielectric layer 111. The respective steps are shown in FIG. Figure 5 Some materials and processes used to form the dielectric layer 111 in step S13 of the method 10 are similar to or the same as those used to form the dielectric layer 107 , and their detailed descriptions are not repeated herein.

[0115] Next, according to some embodiments, such as Figure 6 、 Figure 7 and Figure 8 As shown, an etching process is performed on the dielectric layer 111 to form a plurality of openings 120, which expose the conductive layer 109. The individual steps are shown in FIG. Figure 5 The etching process may include a wet etching process, a dry etching process, or a combination thereof. In some embodiments, each opening 120 exposes a corresponding conductive layer 109 .

[0116] Then, according to some embodiments, such as Figure 9 、 Figure 10 and Figure 11 As shown, a liner film 123 is deposited to cover the dielectric layer 111 and line the opening 120. The individual steps are shown in FIG. Figure 5 Step S17 of method 10 is shown. In some embodiments, the liner film 123 comprises a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, and its fabrication technique comprises a deposition process, such as a CVD process, a PVD process, an ALD process, or a spin coating process.

[0117] In some embodiments, the liner film 123 is formed from a material that has a high etch selectivity compared to the material of the dielectric layer 111. It should be understood that the liner film 123 is conformally deposited on the Figure 6 、 Figure 7 and Figure 8In some embodiments, the upper surface and sidewalls of the dielectric layer 111 and the exposed upper surfaces of the conductive layer 109 are covered by the liner film 123 .

[0118] According to some embodiments, Figure 12 、 Figure 13 and Figure 14 As shown, after the liner film 123 is formed, a patterned mask 125 is formed on the liner film 123. In some embodiments, the patterned mask 125 has a plurality of openings 130 that expose portions of the liner film 123 within the openings 120. It should be understood that each opening 130 is larger than each corresponding opening 120 in the dielectric layer 111. Therefore, portions of the liner film 123 located on the upper surface of the dielectric layer 111 and adjacent to the openings 120 are exposed through the patterned mask 125.

[0119] Specifically, each opening 120 has a length L1 along the X-direction, and each opening 130 has a length L2 along the X-direction. In some embodiments, length L2 is greater than length L1. Furthermore, each opening 120 has a width along the Y-direction that is substantially the same as the width (denoted as W) of a corresponding opening 130 along the Y-direction.

[0120] Then, according to some embodiments, such as Figure 15 、 Figure 16 and Figure 17 As shown, the liner film 123 is etched by using the patterned mask 125 as a mask. The individual steps are shown in FIG. Figure 5 This is step S19 of method 10. In some embodiments, after the liner film 123 is etched, the conductive layer 109 is partially exposed.

[0121] In particular, the liner film 123 is etched by a directional or anisotropic etching process, thereby etching vertically through the liner film 123 with minimal lateral etching. The etching process can be a dry etching process, a wet etching process, or a combination thereof. Therefore, according to some embodiments, portions of the liner film 123 covered by the patterned mask 125 and vertical portions of the liner film 123 located on the sidewalls of the opening 120 are retained, and the upper surface of the dielectric layer 111 and the upper surfaces of the conductive layer 109 are partially exposed. After portions of the upper surface of the dielectric layer 111 adjacent to the opening 120 are exposed, the patterned mask 125 is removed.

[0122] exist Figure 16 In the cross-sectional view of FIG. 1 , according to some embodiments, since the length L2 of the opening 130 is greater than the length L1 of the opening 120 (see FIG. 1 ), the length L2 of the opening 130 is greater than the length L1 of the opening 120 (see FIG. 1 ). Figure 13), so the portion of the upper surface of the dielectric layer 111 adjacent to the opening 120 is exposed through the remaining portion of the liner film 1123. Figure 17 In the cross-sectional view in FIG, according to some embodiments, since the width of the opening 130 is substantially the same as the width W of the opening 120 (see FIG. Figure 14 ), so Figure 17 The upper surface of the dielectric layer 111 is shown to be completely covered by the remaining portion of the liner film 123 .

[0123] According to some embodiments, Figure 18 、 Figure 19 and Figure 20 As shown, after etching the liner film 123, portions of the dielectric layer 111 exposed through the liner film 1213 are etched to form a plurality of first recesses 140a and a plurality of second recesses 140b. In some embodiments, each opening 120 is connected to one of the first recesses 140a and one of the second recesses 140b. The respective steps are shown in FIG. Figure 5 Step S21 in method 10 is shown.

[0124] The dielectric layer 111 can be etched using a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the liner film 123 is formed from a material having a high etch selectivity compared to the material of the dielectric layer 111. Therefore, the dielectric layer 111 is etched using the liner film 123 as a mask.

[0125] In some embodiments, as Figure 19 As shown, the first recess 140a and the second recess 140b have a plurality of inclined sidewalls 111S. Each inclination angle θ between the inclined sidewalls 111S and the liner film 123 is related to the etching time, temperature, and pressure of the etching gas. In the case of a shorter etching time, a lower temperature, and / or a lower pressure, a smaller inclination angle θ is obtained. In some embodiments, the first recess 140a and the second recess 140b each have a curved sidewall. In addition, as shown in FIG. Figure 19 As shown, the first recess 140a has a depth D1, the second recess 140b has a depth D2, and the opening 120 has a depth D3. In some embodiments, the depth D3 is greater than the depth D1 and the depth D2.

[0126] Then, according to some embodiments, such as Figure 21 、 Figure 22 and Figure 23 As shown, the liner film 123 is removed. The individual steps are shown in FIG. Figure 5In some embodiments, the liner film 123 is removed by an etching process, such as a dry etching process or a wet etching process. In some embodiments, the section line Y-Y' is a cross-sectional view cut through the opening 120, but not through the first recess 140a and the second recess 140b. Therefore, the first recess 140a and the second recess 140b are not shown. Figure 23 middle.

[0127] According to some embodiments, Figure 24 、 Figure 25 and Figure 26 As shown, after the liner film 123 is removed, a plurality of conductive contact points 147 are formed on the conductive layer 109, and the opening 120, the first recess 140a and the second recess 140b are filled with the conductive contact points 147. The individual steps are shown in FIG. Figure 5 In step S25 of the method 10 shown, in particular, the first recess 140a is filled by the first expanded portion 145a of the conductive contact 147, the second recess 140b is filled by the second expanded portion 145b of the conductive contact 147, and the opening 120 is filled by the base 143 of the conductive contact 147.

[0128] Some materials of the conductive contacts 147 are similar to or identical to those used to form the conductive layer 109, and their detailed description is not repeated herein. In some embodiments, the conductive contacts 147 are formed by depositing a conductive material (not shown) on the upper surface of the dielectric layer 111 to fill the opening 120, the first recess 140a, and the second recess 140b; and polishing the conductive material to form the conductive contacts 147. The conductive material can be deposited by a CVD process, a PCD process, an ALD process, an MOCVD process, a sputtering process, a plating process, or other applicable processes. Furthermore, the conductive material can be polished by a CMP process.

[0129] In some embodiments, the upper surfaces of the first expansion portion 145a, the upper surfaces of the second expansion portion 145b, and the upper surfaces of the base portion 143 are coplanar with the upper surface of the dielectric layer 111. Figure 25 As shown, the first expansion portion 145a has a height H1, the second expansion portion 145b has a height H2, and the base portion 143 has a height H3. In some embodiments, the height H3 is greater than the height H1 and the height H2.

[0130] Next, please refer back to Figure 1 、 Figure 2 and Figure 3 According to some embodiments, the dielectric layer 151 and the conductive line 153 are formed on the dielectric layer 111 and the conductive contact point 147. The respective steps are shown in FIG. Figure 5 Step S27 of method 10 is shown. The materials and processes used to form dielectric layer 151 and conductive lines 153 are similar or identical to those used to form dielectric layer 107 and conductive layer 109, and their detailed descriptions are not repeated herein. After conductive lines 153 are formed, semiconductor device 100a is obtained.

[0131] In some embodiments, the first recess 140a and the second recess 140b (see Figure 22 ) each having a curved side wall. Therefore, the first expansion portion and the second expansion portion formed next each have a curved side wall, for example Figure 4 The improved semiconductor device 100b is shown with a first expansion portion 145a' and a second expansion portion 145b'.

[0132] The present disclosure provides some embodiments of semiconductor devices 100a and 100b. In some embodiments, conductive contacts 147 and 147' each have an expanded portion (e.g., first expanded portion 145a, 145a' and second expanded portion 145b, 145b') extending outward from base 143 and laterally along the longitudinal axis of conductive line 153. Consequently, the upper surface areas (e.g., upper surface areas 147T, 147'T) of conductive contacts 147 and 147' are larger than the lower surface areas (e.g., upper surface areas 147B, 147'B) of conductive contacts 147 and 147', thereby reducing contact resistance between conductive contacts 147 and 147' and conductive line 153. Furthermore, conductive contacts 147 and 147' do not expand beyond the edges of conductive line 153, thereby preventing or reducing crosstalk between adjacent conductive lines 153 or between adjacent conductive contacts 147 and 147'. Therefore, the performance of the entire device can be improved.

[0133] One embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a conductive layer disposed on a semiconductor substrate; and a conductive contact disposed on the conductive layer. The semiconductor device also includes a conductive line disposed on the conductive contact. In a first cross-sectional view along a longitudinal axis of the conductive line, an upper portion of the conductive contact has a tapered profile; and in a second cross-sectional view along a line segment perpendicular to the longitudinal axis of the conductive line, the upper portion of the conductive contact has a non-tapered profile.

[0134] Another embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a conductive layer disposed on a semiconductor substrate; and a conductive wire disposed on the conductive layer. The semiconductor element also includes a conductive contact point disposed between the conductive layer and the conductive wire, and electrically connecting the conductive layer and the conductive wire. The conductive contact point includes: a base; and a first expansion portion and a second expansion portion extending laterally from the base. The first expansion portion and the second expansion portion are disposed separately from the conductive layer, and wherein the first expansion portion and the second expansion portion have a tapered profile, gradually becoming thinner from the conductive wire toward the conductive layer.

[0135] Another embodiment of the present disclosure provides a method for preparing a semiconductor element. The preparation method includes forming a conductive layer on a semiconductor substrate; and forming a dielectric layer to cover the conductive layer. The preparation method also includes etching the dielectric layer to form an opening to expose the conductive layer; and etching the dielectric layer to form a first recess and a second recess connected to the opening. A depth of the opening is greater than a depth of the first recess and a depth of the second recess, and wherein the first recess and the second recess have a tapered profile that gradually tapers toward the conductive layer. The preparation method also includes forming a conductive contact point on the conductive layer. The opening, the first recess, and the second recess are filled with the conductive contact point. In addition, the preparation method includes forming a conductive line on the conductive contact point.

[0136] The embodiments of the present disclosure have several advantages. By forming a conductive contact point having a tapered profile in a cross-sectional view along a longitudinal axis of a conductive line, the contact resistance between the conductive contact point and the conductive line can be reduced. Consequently, the overall device performance can be improved.

[0137] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0138] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor element comprising: a source / drain region disposed in a semiconductor substrate; a conductive layer disposed on the semiconductor substrate; a conductive contact point disposed on the conductive layer; as well as a conductive wire, disposed on the conductive contact point; wherein the conductive line is electrically connected to the source / drain region via the conductive contact point and the conductive layer; wherein, in a first cross-sectional view along a longitudinal axis of the conductive line, an upper portion of the conductive contact point has a tapered profile, and a lower portion of the conductive contact point is in direct contact with the conductive layer and has a non-tapered profile in the first cross-sectional view; and in a second cross-sectional view along a line segment orthogonal to the longitudinal axis of the conductive line, the upper portion of the conductive contact point has a non-tapered profile, wherein the tapered profile of the upper portion of the conductive contact has curved sidewalls extending inwardly toward the conductive layer; A width of the conductive layer is greater than a width of the lower portion of the conductive contact point. 2 . The semiconductor device as claimed in claim 1 , wherein the tapered profile of the upper portion of the conductive contact in the first cross-sectional view tapers gradually from an upper surface of the conductive contact. 3 . The semiconductor device as claimed in claim 1 , wherein an interface area between the conductive contact point and the conductive line is larger than an interface area between the conductive contact point and the conductive layer. The semiconductor device as claimed in claim 1 , wherein the conductive contact point is completely covered by the conductive line. 5 . The semiconductor device as claimed in claim 1 , wherein in the second cross-sectional view, a width of the conductive line is substantially the same as a width of the conductive contact.

6. A method for preparing a semiconductor element, comprising: Disposing a source / drain region in a semiconductor substrate; forming a conductive layer on the source / drain region; forming a conductive line on the conductive layer; forming a conductive contact point between the conductive layer and the conductive line to electrically connect the conductive layer and the conductive line; as well as electrically connecting the conductive line to the source / drain region via the conductive contact point and the conductive layer; The forming of the conductive contact point comprises: configuring an upper portion of the conductive contact point to have a tapered profile and to contact the conductive line; making a lower portion of the conductive contact point directly contact the conductive layer, wherein a width of the upper portion of the conductive contact point gradually decreases from a top surface of the conductive contact point to a lower portion thereof to configure the tapered profile; The lower portion of the conductive contact is configured to have a non-tapered profile in a first cross-sectional view along a longitudinal axis of the conductive line and to contact the conductive layer, wherein the lower portion of the conductive contact has a uniform width and extends integrally from the upper portion thereof, wherein a width of the conductive layer is greater than a width of the lower portion of the conductive contact; forming a base portion on the upper and lower portions of the conductive contact point so as to be between the contact conductive line and the conductive layer, thereby contacting the conductive line; and A first expansion portion and a second expansion portion are formed, which extend laterally from the base at the upper portion of the conductive contact point, wherein the first expansion portion and the second expansion portion are separately arranged from the conductive layer, and wherein the first expansion portion and the second expansion portion have a tapered profile in the first cross-sectional view, gradually becoming thinner from the conductive line toward the conductive layer, forming the first expansion portion and the second expansion portion, which extend laterally from the base at the upper portion of the conductive contact point to form the tapered profile of the upper portion, wherein the upper portion of the conductive contact point has a non-tapered profile in a second cross-sectional view along a line orthogonal to the longitudinal axis of the conductive line, wherein the first expansion portion and the second expansion portion are separated from the conductive layer, and wherein the first expansion portion and the second expansion portion have a tapered profile gradually becoming thinner from the conductive line to the conductive layer.

7. A method for preparing a semiconductor element as described in claim 6, wherein the first expansion portion of the conductive contact point and the second expansion portion of the conductive contact point are separately arranged, and the first expansion portion and the second expansion portion are completely covered by the conductive line, wherein the first expansion portion and the second expansion portion each have an inclined side wall inclined toward the conductive line to form a tapered profile of the upper portion of the conductive contact point. 8 . The method for fabricating a semiconductor device as claimed in claim 6 , wherein the first expansion portion and the second expansion portion of the conductive contact point directly contact the conductive wire, and wherein an upper surface of the base directly contacts the conductive wire.

9. The method for fabricating a semiconductor device according to claim 6, wherein the upper surfaces of the first expansion portion and the second expansion portion of the conductive contact are substantially coplanar with an upper surface of the base portion of the conductive contact, wherein: The upper surface of the base, the first expansion portion of the conductive contact point, and the second expansion portion are all planes in contact with the conductive wire.

10. A method for preparing a semiconductor element as described in claim 6, wherein in a cross-sectional view along a longitudinal axis of the conductive line, a height of the base of the conductive contact point is greater than a height of the first expansion portion of the conductive contact point and a height of the second expansion portion of the conductive contact point, wherein a height of the upper portion of the conductive contact point is less than a height of the lower portion of the conductive contact point.

11. The method for fabricating a semiconductor device as claimed in claim 6, wherein the first expansion portion and the second expansion portion of the conductive contact each have a curved sidewall, and wherein a height of the upper portion of the conductive contact is smaller than a height of the lower portion of the conductive contact.

12. A method for preparing a semiconductor element, comprising: Disposing a source / drain region in a semiconductor substrate; forming a conductive layer on the source / drain region; forming a dielectric layer to cover the conductive layer; etching the dielectric layer to form an opening to expose the conductive layer, wherein the opening is formed to have an upper portion and a lower portion integrally extending from the upper portion; Etching the dielectric layer to form a first recess and a second recess connected to the upper portion of the opening, wherein a depth of the opening is greater than a depth of the first recess and a depth of the second recess, and wherein the first recess and the second recess have tapered profiles that taper toward the conductive layer, such that the upper portion of the opening integrated with the first and second grooves is configured to have a tapered profile, and the lower portion of the opening is configured to have a non-tapered profile; forming a conductive contact on the conductive layer, wherein the opening, the first recess, and the second recess are filled by the conductive contact, such that an upper portion of the conductive contact is configured to have a tapered profile, and a lower portion of the conductive contact is configured to have a non-tapered profile, wherein a width of the upper portion of the conductive contact gradually decreases from a top surface of the conductive contact to a lower portion thereof, wherein a height of the upper portion of the opening is less than a height of the lower portion of the opening, wherein the lower portion of the conductive contact is in direct contact with the conductive layer, and wherein a width of the conductive layer is greater than a width of the lower portion of the conductive contact; and A conductive wire is formed on the conductive contact point so that the top surface of the upper portion of the conductive contact point contacts the conductive wire, wherein a tapered profile of the upper portion of the conductive contact point is formed in a first cross-sectional view along the longitudinal axis of the conductive wire, wherein the tapered profile of the upper portion of the conductive contact point has a non-tapered profile in a second cross-sectional view along a line orthogonal to the longitudinal axis of the conductive wire, wherein the non-tapered profile of the lower portion of the conductive contact point is formed in the first cross-sectional view.

13. The method for preparing a semiconductor element as described in claim 12, wherein the opening has a non-tapered profile at its lower portion so that the width of the lower portion of the opening is uniform, wherein the conductive contact point has two inclined sidewalls, and the inclined sidewalls are inclined from the conductive line to the lower portion of the conductive contact point, thereby forming a tapered profile at the upper portion of the conductive contact point.

14. The method for fabricating a semiconductor device as claimed in claim 12, wherein etching the dielectric layer to form the first recess and the second recess comprises: depositing a liner film to cover the dielectric layer and line the opening; etching the liner film to expose portions of the dielectric layer adjacent to the opening; as well as Portions of the dielectric layer exposed through the liner film are etched to form the first recess and the second recess. 15 . The method for fabricating a semiconductor device as claimed in claim 14 , wherein after etching the liner film, the conductive layer is exposed.

16. The method for preparing a semiconductor device according to claim 14, further comprising: After the first recess and the second recess are formed, the liner film is removed.

17. The method for fabricating a semiconductor device according to claim 12, wherein forming the conductive contact on the conductive layer comprises: forming a conductive material on the dielectric layer, wherein the opening, the first recess, and the second recess are filled with the conductive material; as well as The conductive material is ground to form the conductive contact point.

18. A method for preparing a semiconductor element as described in claim 12, wherein an upper surface area of ​​the conductive contact point is larger than a lower surface area of ​​the conductive contact point, and the upper surface of the conductive contact point is completely covered by the conductive line, wherein the upper portion of the conductive contact point has two curved sidewalls extending inwardly to the conductive layer to form the tapered profile.

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