Method of forming a device having a memory cell, a high voltage device, and a logic device

Abstract

The present invention discloses a method for forming a memory cell, an HV device and a logic device on a substrate, the method comprising: making the upper surface of the memory cell region and the HV device region of the substrate concave; forming a polysilicon layer in the memory cell region and the HV device region; forming a first groove through the first polysilicon layer and entering the silicon substrate in the memory cell region and the HV device region; filling the first groove with an insulating material; forming a second groove in the substrate in the logic device region to form a fin extending upward; removing a portion of the polysilicon layer in the memory cell region to form a floating gate; forming an erase gate and a word line gate in the memory cell region, forming an HV gate in the HV device region, and forming a dummy gate from the second polysilicon layer in the logic device region; and replacing the dummy gate with a metal gate wrapped around the fin.

Description

Technical Field

[0001] The present invention relates to methods of forming devices having non-volatile memory cells, high voltage devices, and fin field effect transistor (FINFET) logic devices. Background Art

[0002] Split gate non-volatile flash memory cells with select gates, floating gates, control gates, and erase gates are well known in the art. See, for example, U.S. Patents 6,747,310 and 7,868,375, which are incorporated herein by reference. Split gate non-volatile flash memory cells with select gates, floating gates, and erase gates are also well known in the art. See, for example, U.S. Patents 7,315,056 and 8,711,636, which are incorporated herein by reference. It is also known to form logic devices (i.e., low voltage and / or high voltage logic devices) on the same silicon wafer, and to do so share some of the processing steps used to form portions of both the memory cell and the logic device (e.g., using the same polysilicon deposition process to form the gates of both the memory cell and the logic device). However, other processing steps to form the memory cell can adversely affect previously prepared logic devices, and vice versa, so it is often difficult and complicated to form both types of devices on the same wafer.

[0003] In order to solve the problem of reduced channel width by reducing the lithographic size, a FinFET type structure for a memory cell structure has been proposed. In a FinFET type structure, a fin-shaped member of a semiconductor material connects a source region to a drain region. The fin-shaped member has a top surface and two side surfaces. Then, the current from the source region to the drain region can flow along the top surface and the two side surfaces of the fin-shaped member. Therefore, the effective width of the channel region increases, thereby increasing the current. However, the effective width of the channel region is increased by "folding" the channel region into two side surfaces without sacrificing more semiconductor substrate surface, thereby reducing the "coverage area" of the channel region. Non-volatile memory cells using such FinFETs have been disclosed. Some examples of prior art FinFET non-volatile memory structures include U.S. Patent Nos. 7,423,310, 7,410,913, 8,461,640, and 9,985,042 and U.S. Patent Application No. 16 / 724,010, the entire contents of each of which are incorporated herein by reference. This SST 351913-980140-MTI No.20074.CN01

[0004] What these prior art references do not contemplate is a FinFET type configuration for logic devices, a non-FinFET type configuration of both, formed on the same wafer substrate as both non-volatile memory cells and high voltage transistor devices utilizing improved manufacturing techniques.

[0005] US Patent Nos. 9,972,630 and 10,249,631 (each of which is incorporated herein by reference in its entirety) disclose memory devices having FinFET type logic devices and non-FinFET memory cells. However, these patents fail to contemplate the simultaneous formation of high voltage transistor devices in non-FinFET type configurations. Summary of the invention

[0006] The foregoing problems and needs are solved by a method of forming a device, the method comprising:

[0007] Providing a silicon substrate with an upper surface and having a first region, a second region, and a third region;

[0008] recessing the upper surface in the first region and the second region of the substrate, but not recessing the upper surface in the third region of the substrate;

[0009] forming a first polysilicon layer, the first polysilicon layer being located above the upper surface in the first region and the second region and being insulated from the upper surface;

[0010] forming a first trench using at least a first silicon etch, the first trench penetrating the first polysilicon layer and into the silicon substrate in the first region and the second region but not in the third region;

[0011] filling the first trench with an insulating material;

[0012] forming a second trench in the silicon substrate in the third region using at least a second silicon etch after the filling of the first trench to form an upwardly extending fin of the silicon substrate, the upwardly extending fin having a pair of side surfaces extending upwardly and terminating at a top surface;

[0013] After said forming of said fins, forming a pair of material blocks over said first polysilicon layer in said first region;

[0014] removing a portion of the first polysilicon layer in the first region to form a pair of floating gates of the first polysilicon layer, each of the floating gates being disposed below one of the pair of material blocks;

[0015] performing a first implant to form a first source region in the silicon substrate in the first region between the pair of floating gates;

[0016] SST 351913-980140-MTI No.20074.CN01

[0017] forming a second polysilicon layer over the silicon substrate in the first region, the second region, and the third region;

[0018] removing a portion of the second polysilicon layer to form:

[0019] a first polysilicon block of the second polysilicon layer, the first polysilicon block being disposed above the first source region in the first region and insulated from the first source region,

[0020] a second polysilicon block of the second polysilicon layer, the second polysilicon block being disposed above and insulated from the silicon substrate and adjacent to one of the pair of floating gates in the first region,

[0021] a third polysilicon block of the second polysilicon layer, the third polysilicon block being disposed above and insulated from the silicon substrate and adjacent to the other floating gate of the pair of floating gates in the first region,

[0022] a fourth polysilicon block of the second polysilicon layer, the fourth polysilicon block being disposed above the silicon substrate in the second region and insulated from the silicon substrate, and

[0023] a fifth polysilicon block of the second polysilicon layer, the fifth polysilicon block being disposed above and insulated from the pair of side surfaces and the top surface of the silicon fin in the third region;

[0024] Perform one or more injections to form:

[0025] a first drain region located in the first region of the substrate and adjacent to the second polysilicon block,

[0026] a second drain region located in the first region of the substrate and adjacent to the third polysilicon block,

[0027] a second source region located in the second region of the substrate and adjacent to the fourth polysilicon block,

[0028] a third drain region located in the second region of the substrate and adjacent to the fourth polysilicon block,

[0029] a third source region located in the fin and adjacent to the fifth polysilicon block, and

[0030] a fourth drain region located in the fin and adjacent to the fifth polysilicon block;

[0031] removing the fifth polycrystalline silicon block;

[0032] forming a high-K material layer in the third region along the pair of side surfaces and the top surface of the fin; and

[0033] SST 351913-980140-MTI No.20074.CN01

[0034] A metal material block is formed on the high-K material layer in the third region such that the metal block extends along and is insulated from the pair of side surfaces and the top surface of the fin.

[0035] Other objects and features of the present invention will become apparent by examining the specification, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figures 1A to 15A is a side cross-sectional view showing a step of forming a nonvolatile memory cell in a memory cell region of a semiconductor substrate.

[0037] Figures 1B to 15B is a side cross-sectional view showing a step of forming a high voltage device in an HV device region of a semiconductor substrate.

[0038] Figures 1C to 15C is a side cross-sectional view showing a step of forming a logic device in a logic device region of a semiconductor substrate.

[0039] Fig.16 is a side cross-sectional view of a memory cell in a memory cell region.

[0040] Fig.17 is a side cross-sectional view of a high voltage device in the HV device area.

[0041] Figure 18 to Figure 19 is a side cross-sectional view of a logic device in a logic device area.

[0042] FIG. 20A to FIG. 21A is a side cross-sectional view illustrating a step of forming a nonvolatile memory cell in a memory cell region of a semiconductor substrate according to an alternative embodiment.

[0043] FIG. 20B to FIG. 21B is a side cross-sectional view illustrating a step of forming a high voltage device in a HV device region of a semiconductor substrate according to an alternative embodiment.

[0044] FIG. 20C to FIG. 21C is a side cross-sectional view illustrating a step of forming a logic device in a logic device region of a semiconductor substrate according to an alternative embodiment. DETAILED DESCRIPTION

[0045] See also Figures 1A to 15A , Figures 1B to 15B and Figures 1C to 15C , showing a pair of memory cells in a memory cell region 2 (first region) of a semiconductor wafer substrate (also referred to as a substrate) 10 (see Figures 1A to 15A ), the high voltage transistor device in the HV device region 6 (second region) of the substrate 10 (see Figures 1B to 15B ) and the logic devices in the logic device region 4 (third region) of the substrate 10 (see Figures 1C to 15C ) is a side cross-sectional view of a step in a process of forming a silicon dioxide (also called oxide) layer 12 on a planar surface 10a of a substrate 10, wherein the substrate 10 may be formed of P-type single crystal silicon. The oxide layer 12 may be formed by SST 351913-980140-MTI No.20074.CN01

[0046] Overdeposition or by thermal oxidation. A silicon nitride layer 14 (also referred to as a nitride layer 14) is formed on the oxide layer 12. A photolithography mask process is then used to pattern the nitride layer 14 and the oxide layer 12 (i.e., selectively remove some portions of the layer and not other portions). The photolithography mask process includes coating a photoresist material on the nitride layer 14, followed by exposure and development of the photoresist to remove the photoresist material from the memory cell area and the HV device area 2 / 6, while keeping the photoresist in the logic device area 4. Nitride etching and oxide etching are then used to remove the exposed nitride layer and oxide layer 14 / 12 from the memory cell area and the HV device area 2 / 6, thereby exposing the upper surface 10a of the substrate 10 in the memory cell area and the HV device area 2 / 6 (the photoresist protects these layers from etching in the logic device area 4). After the remaining photoresist is removed from the logic device region 4, silicon oxidation is used alone or in combination with silicon etching to recess the exposed upper surface 10a of the substrate 10 in the memory cell region and the HV device region 2 / 6. For example, the silicon oxidation can be a thermal oxidation that consumes silicon at the upper surface 10a of the substrate. The oxide layer and nitride layer 12 / 14 protect the logic device region 4 from this oxidation / etching. Then, oxide etching is used to remove the oxide formed by the thermal oxidation. The resulting structure is shown in Figures 1A to 1C , wherein the upper surface 10a of the substrate 10 in the HV / memory cell region 6 / 2 is recessed below the surface 10a of the substrate 10 in the logic device region 4 by a recess amount R. Non-limiting examples of the recess amount R may include approximately 20 nm-70 nm.

[0047] The nitride layer and oxide layer 14 / 12 are removed from the logic device region 4 (e.g., by one or more etches), thereby exposing the surface 10a of the substrate 10. At this stage, the upper surface 10a of the substrate 10 is stepped, wherein portions of the upper surface 10a of the substrate 10 in the memory cell region and the HV device region 2 / 6 are recessed (i.e., lowered) by a recess amount R relative to portions of the upper surface 10a of the substrate 10 in the logic device region 4. Then, an oxide (insulating material) layer 16 is formed on the surface 10a of the substrate 10 in all three regions 2 / 4 / 6 (e.g., by deposition or thermal oxidation), followed by forming a polysilicon (also referred to as polysilicon (poly)) layer 18 (first polysilicon layer) by performing polysilicon deposition on the oxide layer 16. A photolithography mask process is used to cover the structure with a photoresist and remove the photoresist from the logic device region 4. Then, polysilicon etching is used to remove the polysilicon layer 18 from the logic device region 4. The resulting structure is shown in FIG. FIG. 2A to FIG. 2C The polysilicon layer 18 will eventually be used to form the floating gates of the memory cells in the memory cell region 2 .

[0048] An oxide layer 20 is formed on the polysilicon layer 18 in the memory cell region and the HV device region 2 / 6 and on the oxide layer 16 in the logic device region 4, and an SST 351913-980140-MTINo.20074.CN01 is formed on the oxide layer 20

[0049] Nitride layer 22. A photolithographic masking step is used to cover the structure with photoresist and then selectively remove portions of the photoresist to expose selected portions of the underlying nitride layer 22. One or more etches are then performed in those selected areas to form trenches 23 that extend through the nitride layer 22, oxide layer 20, polysilicon layer 18, oxide layer 16 and into substrate 10 in the memory cell region and HV device region 2 / 6. After the photoresist is removed, the structure is covered in an oxide (i.e., shallow trench isolation (STI) oxide) layer 24, thereby filling the trenches 23 with oxide 24. The structure is then planarized (e.g., by chemical mechanical polishing - CMP) to expose the top surface of the nitride layer 22. The resulting structure is shown in FIG. FIG. 3A to FIG. 3C middle.

[0050] A material layer 26 (e.g., polysilicon) is formed on the nitride layer 22. The material layer 26 is patterned by forming a photoresist 28; selectively removing strips of the photoresist 28 in the logic device region 4; and removing the underlying exposed portion of the layer 26 to form trenches 30 in the layer 26 extending downward to the underlying nitride layer 22 and exposing the underlying nitride layer in the logic device region 4, as shown in FIG. FIG. 4A to FIG. 4C As shown. After the photoresist is removed, spacers 29 are then formed in the trenches 30. The formation of spacers is well known in the art and involves the deposition of material over the contours of the structure, followed by an anisotropic etching process, thereby removing the material from the horizontal surfaces of the structure while the material remains largely intact (often with a rounded upper surface) on the vertically oriented surfaces of the structure. In this case, the spacers 29 are formed along the sidewalls of the trenches 30 and are preferably formed of an oxide or nitride. Next, the remaining portions of layer 26 are removed by etching. Next, the structure is covered with a photoresist, which is exposed and developed to remove the photoresist from the logic device area 4. A nitride etch is then used to remove the exposed portions of the nitride layer 22 between the spacers 29 in the logic device area, followed by an oxide etch to remove the exposed portions of the oxide layers 20 and 16 in the logic device area 4 and the oxide layer 20 in the memory cell area and the HV device area 2 / 6. Then, silicon etching is used to recess the exposed surface of substrate 10 in logic device region 4, thereby forming trenches 31 extending into substrate 10, wherein fins 10b of the silicon substrate are located between trenches 31. Each fin 10b is an upwardly extending member having a pair of side surfaces 10c that extend upwardly and terminate at a top surface 10d, as described below with respect to Fig.19 The resulting structure is shown in FIG. 5A to FIG. 5C in (after photoresist removal).

[0051] The spacers 29 are removed by etching. Oxide deposition and CMP are used to fill the spaces between the fins 10b with STI oxide 32. The HV device region may have a PMOS region and an NMOS region. Photoresist is formed over the structure and removed from the PMOS region of the HV device region 6. Then, SST 351913-980140-MTI No.20074.CN01

[0052] An implantation into the substrate 10 is performed to form an N-well (NW). Then, an etch is performed to recess the oxide 24 in the HV device region 6 and remove the nitride layer 22. After the photoresist removal, a photoresist is formed over the structure and removed from the NMOS region of the HV device region 6 and from the memory cell region 2. Then, an implantation into the substrate 10 is performed to form a P-well (PW). Then, an etch is performed to recess the oxide 24 in the memory cell region 2 and remove the nitride layer 22. The resulting structure is shown in FIG. FIG. 6A to FIG. 6C in (after photoresist removal).

[0053] Oxide etching is used to remove oxide layer 20 from the memory cell area and HV device area 2 / 6 (and to lower the upper surface of oxide 24 in these areas). An insulating layer 34 (preferably comprising three sub-layers of oxide, nitride, and oxide (e.g., an ONO layer)) is formed over the structure. A polysilicon layer 36 is formed on the ONO layer 34 by a second polysilicon deposition. A hard mask layer (e.g., nitride or other suitable insulating material) 38 is formed on the polysilicon layer 36. The resulting structure is shown in FIG. 7A to 7C . A photoresist is formed over the structure and is partially removed to fully expose the logic device region 4, fully expose the HV device region 6, and expose portions of the memory cell region 2, thereby exposing portions of the hard mask layer 38. A nitride etch is used to remove the exposed portions of the hard mask layer 38, thereby exposing portions of the polysilicon layer 36. A polysilicon etch is used to remove the exposed portions of the polysilicon layer 36, thereby exposing portions of the insulating layer 34. An etch is used to remove the exposed portions of the insulating layer 34, thereby exposing portions of the polysilicon layer 18. After the photoresist is removed, ON (oxide and nitride) spacers 40 / 42 are formed by oxide deposition, nitride deposition, and subsequent nitride anisotropic etching and oxide anisotropic etching. The resulting structure is shown in FIG. 8A to FIG. 8C In. Fig. 8A As shown, a pair of stacked structures S1 and S2 are formed in the memory cell region 2, the stacked structures including a hard mask material block 38a retained from the hard mask layer 38, the hard mask material block being located on a polysilicon block 36a retained from the polysilicon layer 36 and on an insulating block 34a retained from the insulating layer 34, wherein oxide spacers and nitride spacers 40 / 42 are formed along the sides of the stacked structures S1 and S2. For each pair of stacked structures S1 / S2, the region between the stacked structures S1 and S2 is referred to herein as an inner region IR, and the regions on opposite sides of the stacked structures S1 and S2 are referred to herein as outer regions OR.

[0054] Then, polysilicon etching is used to remove the exposed portions of the polysilicon layer 18 in the memory cell region and the HV device region 2 / 6 (i.e., all portions except those portions protected by the stacked structures S1 and S2). Then, oxide spacers 44 are formed on the sides of the stacked structures S1 and S2 by oxide deposition and anisotropic etching. The stacked structures S1 and S2 now also include SST 351913-980140-MTI No.20074.CN01 at their lower portions.

[0055] Polysilicon chunks 18a retained from polysilicon layer 18 are removed. A photoresist is formed over the structure and removed only from HV device region 6. An optional implantation into substrate 10 in HV device region 6 may be performed. Then, an oxide etch is used to remove oxide layer 16 from HV device region 6. Oxide layer 46 is formed on exposed substrate surface 10a in HV device region 6 (e.g., by thermal oxidation or deposition) to have a thickness suitable for forming HV device operations in that region. The resulting structure is shown in Figures 9A to 9C in (after photoresist removal).

[0056] The structure is then covered with a photoresist that is selectively removed to expose the inner region IR between the paired stacked structures S1 and S2 in the memory cell region 2. Implantation is then performed to form a source region 48 in the memory cell region 2 in the substrate 10 between each pair of stacked structures S1 and S2. Oxide etching is then used to remove the oxide spacers 44 on the inner sidewalls of the stacked structures S1 and S2 (i.e., those sidewalls facing each other in the inner region IR). An oxide (tunnel oxide) layer 50 is formed on the inner sidewalls of the stacked structures S1 and S2 and on the substrate surface 10a between the stacked structures S1 and S2 (e.g., by thermal oxidation and / or oxide deposition) to have a thickness suitable for electron tunneling. Thermal oxidation and high dopant concentrations of the source region 48 may cause the oxide layer 50 to be thicker on the substrate surface 10a. The structure is covered with a photoresist that is removed from the outer region OR in the memory cell region 2. An implant (referred to as a word line voltage implant) is performed in the substrate 10 in the outer region OR. An oxide etch is used to remove the oxide layer 16 from the outer region OR in the memory cell region 2. The resulting structure is shown in FIGS. Fig. 10C in (after photoresist removal).

[0057] A photoresist is formed on the structure and removed from the logic device area 4. Etching is used to remove the nitride layer 22 from the logic device area 4. Implantation is performed to form a well in the substrate 10 in the logic device area 4. Oxide etching is used to remove the oxide layers 20 and 16 from the logic device area 4 and to recess the oxide 32 in the trench 31 surrounding the fin 10b. After the photoresist is removed, a dielectric (insulating) layer 52 is formed on the exposed surface 10a of the substrate in the memory cell area and the logic device area 2 / 4 and along the side of the fin 10b in the logic device area 4. The dielectric layer 52 also becomes part of the oxide layer 46 in the HV device area 6. The dielectric layer 52 may be an oxide, an oxynitride, or other suitable insulating material. Then, a polysilicon layer 54 (a second polysilicon layer) is deposited on the structure around the side including the fin 10b in the logic device area 4. The CMP process and the etch-back process are used to reduce the thickness of the polysilicon layer 54 (ie, so that the upper surface of the polysilicon layer 54 is flush with or below the top of the stacked structure S1 / S2 in the memory cell region 2). The resulting structure is shown in FIG. FIG. 11A to FIG. 11C middle.

[0058] SST 351913-980140-MTI No.20074.CN01

[0059] A hard mask layer 56 is formed over the structure, which may be a single layer of material or multiple layers of material (two layers are shown in the figure). The hard mask layer 56 is patterned using one or more photolithography processes, thereby exposing portions of the hard mask layer 56. The exposed portions of the hard mask layer 56 are removed by one or more etches, thereby exposing portions of the polysilicon layer 54. The exposed portions of the polysilicon layer 54 are removed by one or more etches, wherein those portions of the polysilicon layer 54 that are located below and protected by the remaining portions of the hard mask 56 are protected from the one or more etches and remain. The resulting structure is shown in FIG. FIG. 12A to FIG. 12C Among them Fig. 12C is along Fig. 11C The line AA is perpendicular to Figure 1C to Figure 11C10b of the view of FIG. The patterning of the hard mask and polysilicon layer can be performed in two stages. For example, a first hard mask etch can be performed in the memory cell area and the HV device area 2 / 6 and in a local area in the logic device area 4, followed by a separate second hard mask etch for only the local area in the logic device area 4. After the photoresist is removed, a separate polysilicon etch is then performed. The resulting structure has first polysilicon blocks 54a retained from the polysilicon layer 54, each of which is disposed above one of the source regions 48, second and third polysilicon blocks 54b retained from the polysilicon layer 54, each of which is disposed in an outer region in the outer region OR adjacent to one of the stacked structures S1 / S2, fourth polysilicon blocks 54c retained from the polysilicon layer 54, each of which is disposed in the HV device region 6, and fifth polysilicon blocks 54d retained from the polysilicon layer 54, each of which is disposed in the logic device region 4. Each of the fifth polysilicon blocks 54d is wrapped around the fin 10b.

[0060] Insulating spacers (e.g., nitride) 58 are formed on the sides of the structure by deposition and anisotropic etching. A series of masking steps and implants are performed to form a drain region 60 in the substrate 10 adjacent to the polysilicon block 54b in the memory cell region 2, a source region 62 and a drain region 64 in the substrate 10 adjacent to the polysilicon block 54c in the HV device region 6, and a source region 66 and a drain region 68 in the substrate 10 adjacent to the polysilicon block 54d. Forming the source region 66 and the drain region 68 in the logic device region 4 may include removing portions of the fin 10b adjacent to the polysilicon block 54d and replacing them with epitaxially grown material, wherein the source region 66 and the drain region 68 are epitaxially grown material portions of the fin 10b. Optionally, the drain region 60 in the memory cell region 2 and / or the source and drain regions 62 / 64 in the HV device region 6 may also be replaced with epitaxially grown material in a similar manner. Additional oxide spacers 70 and nitride spacers 72 may be formed along the nitride spacers 58. The resulting structure is shown in FIG. 13A to FIG. 13C middle.

[0061] SST 351913-980140-MTI No.20074.CN01

[0062] An etch stop material layer 74 is formed over the structure. A thick insulating material layer (ILD) 76 is formed over the structure. Then, chemical mechanical polishing and etching are performed to reduce the ILD layer 76, remove the hard mask layer 56, and expose the polysilicon blocks 54a, 54b, 54c, and 54d (e.g., CMP is stopped after exposing the polysilicon blocks 54a-54d), as shown in FIG. FIG. 14A to FIG. 14C As shown. Etching is used to remove the polysilicon block 54d from the logic device area 4 (thereby exposing the dielectric layer 52) and remove the exposed dielectric layer 52. A high-K material layer 78 (i.e., having a dielectric constant K greater than the dielectric constant of silicon dioxide (such as HfO2, ZrO2, TiO2, Ta2O5 or other suitable materials)) is formed on the structure. A metal material layer is formed above the structure. CMP is used to remove the metal material and the high-K material layer except for the metal block 80 that is set above the fin 10b and insulated therefrom by the high-K material layer 78. An ILD insulating layer 82 is formed above the structure, and contact holes are formed in the ILD and other insulating layers to expose various source and drain regions, polysilicon blocks, and metal blocks. The contact holes are then filled with a contact material (such as a metal) to form electrical contacts 84. The final structure is shown in FIG. 15A to FIG. 15C middle.

[0063] Fig.16 is a cross-sectional view showing a pair of nonvolatile memory cells 100 formed in the memory cell region 2. Each pair of nonvolatile memory cells 100 includes a (first) source region 48 and two (first and second) drain regions 60, which define a planar channel region 90 in the substrate 10 therebetween. For each nonvolatile memory cell 100, a floating gate formed by a polysilicon block 18a is disposed over a first portion of the channel region 90 and controls the first portion, and a word line (select) gate formed by a polysilicon block 54b is disposed over a second portion of the channel region 90 and controls the second portion. A control gate formed by a polysilicon block 36a is disposed over a floating gate formed by a polysilicon block 18a, and an erase gate formed by a polysilicon block 54a is disposed over a source region 48. The nonvolatile memory cells 100 are formed end-to-end in pairs, wherein each memory cell pair shares a common drain region 60, and adjacent pairs of nonvolatile memory cells 100 share a common erase gate formed by the polysilicon block 54a and the source region 48. The dielectric layer 52 under the word line gate formed by the polysilicon block 54b is preferably thinner than the oxide layer 16 under the floating gate formed by the polysilicon block 18a to obtain better word line gate performance.

[0064] Fig.17The present invention includes a cross-sectional view of HV (high voltage) devices 102 formed in the HV device region 6. Each HV device 102 includes a (second) source region 62 and a (third) drain region 64, which define a planar channel region 92 in the substrate 10 therebetween. The HV gate formed by the polysilicon block 54c is disposed above the planar channel region 92 and controls the conductivity of the planar channel region. The HV gate formed by the polysilicon block 54c is insulated from the substrate by the oxide layer 46. Because the oxide layer is formed separately, the oxide layer may have a similar conductivity to the oxide layer 16 (for the HV gate formed by the polysilicon block 54c, the HV gate 54c ... HV gate 16) (for the HV gate formed by the polysilicon block 54c, the HV gate 54c may have a similar conductivity to the HV gate 16).

[0065] The floating gate formed by the polysilicon block 18 a ) and the dielectric layer 52 (for the word line gate formed by the polysilicon block 54 b ) have different thicknesses for improving the performance of the HV device 102 .

[0066] Fig.18 and Fig.19 4 is a cross-sectional view of logic devices 104 formed in the logic device region 4. Each logic device 104 includes a (third) source region 66 and a (fourth) drain region 68, which define a channel region 94 in the fin 10b therebetween. Fig.19 As best shown, the channel region 94 includes a top surface portion 94a extending along the top of the fin 10b, and a side surface portion 94b extending along the side of the fin 10b. The logic gate 80 is wrapped around the fin 10b (i.e., the logic gate formed by the metal block 80 is disposed above the top surface portion of the channel region 94, particularly above the top surface portion 94a, and laterally adjacent to the side surface portion 94b for controlling the conductivity of the channel region 94).

[0067] Although only two nonvolatile memory cells 100 , two HV devices 102 , and two logic devices 104 are shown in the drawings, those skilled in the art will appreciate that many devices of each type are simultaneously formed in their respective regions.

[0068] The above-described memory device method and resulting structure provide many advantages, including high operating performance and ease of manufacturing of a planar non-volatile memory cell 100 (i.e., a non-volatile memory cell 100 formed on a planar region of a substrate 10 and having a planar channel region 90) and a planar HV device 102 (i.e., a device formed on a planar region of a substrate 10 and having a planar channel region 92), with the advantages of an advanced combination of an embedded logic device and a memory device, wherein the logic device 104 is a compressed non-planar logic device (i.e., a logic device formed on and around the fin 10b and having a non-planar channel region 94). The FinFET transistor architecture of the logic device 104 provides enhanced channel control with a tri-gate configuration and enables further scaling of transistor size.

[0069] Another advantage is that the upper surface 10a of the substrate 10 is recessed in the memory cell region and the HV device region 2 / 6 relative to the logic device region 4. Specifically, the planar upper surface 10a of the substrate 10 constituting the channel region in the memory cell region and the HV device region 2 / 6 has a height below the top of the fin 10b in the logic device region 4 by a recess amount R, as shown in FIG. Figures 1A to 1C As shown, it accommodates the higher gate stack thickness and topology of the memory cell device and HV device 100 / 102 relative to the logic device 104. In addition, common processing in the logic device region 4 and the memory cell region and HV device region 2 / 6 is facilitated. For example, raising the fin 10b in the logic device region 4 to a height above the substrate surface in the memory cell region simplifies the common formation steps of the polysilicon layer 54, the hard mask layer 56, and the blocks of spacers 58 / 70 / 72. Similarly, a common implantation step can be used to form the memory cell drain region 60, the HV device source region / drain region 62 / 64, and the logic device source SST 351913-980140-MTI No.20074.CN01

[0070] Region / drain region 66 / 68. In addition, the erase gate formed by the polysilicon block 54a, the word line gate formed by the polysilicon block 54b, the HV gate formed by the polysilicon block 54c and the dummy polysilicon block 54d are all formed using the same polysilicon deposition process. Another advantage is that the polysilicon block 54d of the polysilicon layer 54 is used as a dummy block, which is removed and replaced with a high-K material and a metal gate 80. This means that a single polysilicon layer is used to form the erase gate formed by the polysilicon block 54a and the word line gate formed by the polysilicon block 54b in the memory cell region 2, to form the high voltage gate formed by the polysilicon block 54c in the HV device region 6, and to form the dummy polysilicon block 54d in the logic region 4. Most of the process manufacturing for the memory cell and HV device (including the formation of all polysilicon blocks for the gates of the memory cell and HV device) is performed before the logic gate is formed, which reduces the processing impact on the CMOS baseline. Before the fin 10b is formed in the logic device region 4, STI insulation for the memory cell region and the HV device region 2 / 6 is formed, which means that the depth of the STI extending into the substrate can vary between the memory cell region and the HV device region 2 / 6 and the logic device region (i.e., the trench 23 can extend deeper into the substrate 10 than the trench 31, and vice versa).

[0071] FIG. 20A to FIG. 20C and FIG. 21A to FIG. 21C An alternative embodiment is shown, which begins with FIG. 6A to FIG. 6C In this alternative embodiment, except that the formation of the insulating layer 34 and the polysilicon layer 36 is omitted, the above-mentioned 7A to 7C The steps described above enable the hard mask layer 38 to be formed directly on the polysilicon layer 18, such as FIG. 20A to FIG. 20C Except for any steps involving the insulating layer 34 and the polysilicon layer 36, the remaining processing steps are performed as described above, thereby obtaining FIG. 21A to FIG. 21C The final structure shown. In this first alternative embodiment, the only significant difference in the final structure is that there is no control gate (a block of material from polysilicon layer 36) above the floating gate formed by polysilicon block 18a in memory cell area 2. Instead, each memory cell includes only three gates (a floating gate formed by polysilicon block 18a, a word line gate formed by polysilicon block 54b, and an erase gate formed by polysilicon block 54a). In this embodiment, the block of material located above the floating gate is a block of nitride layer 38. Omitting the control gate will allow the height of the memory cell to be further reduced.

[0072] It should be understood that the present invention is not limited to one or more embodiments described above and shown herein. For example, reference to the present invention herein is not intended to limit the scope of any claim or claim term, but only to refer to one or more features that may be covered by one or more claims. The examples of materials, processes and values ​​described above are merely exemplary and should not be considered to limit the claims. In addition, it is apparent from the claims and description that not all method steps need to be performed in the exact order shown or claimed, but in an order that allows the present invention to be performed in the same manner as described herein.

[0073] Any order of appropriate formation of memory cells and logic devices is accomplished (unless there are expressly delineated limitations on any order). Finally, a single material layer may be formed as multiple such or similar material layers, and vice versa.

[0074] It should be noted that, as used herein, the terms "above" and "on" both include inclusively "directly on" (without intermediate materials, elements, or spaces disposed therebetween) and "indirectly on" (with intermediate materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (without intermediate materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (with intermediate materials, elements, or spaces disposed therebetween), "mounted to" includes "mounted directly to" (without intermediate materials, elements, or spaces disposed therebetween) and "mounted indirectly to" (with intermediate materials, elements, or spaces disposed therebetween), and "electrically connected to" includes "directly electrically connected to" (without intermediate materials or elements electrically connecting the elements together) and "indirectly electrically connected to" (with intermediate materials or elements electrically connecting the elements together). For example, forming an element "above a substrate" may include forming the element directly on the substrate without intermediate materials / elements therebetween, and indirectly forming the element on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. A method of forming a device, the method comprising: Providing a silicon substrate with an upper surface and having a first region, a second region, and a third region; recessing the upper surface in the first region and the second region of the substrate, but not recessing the upper surface in the third region of the substrate; forming a first polysilicon layer, the first polysilicon layer being located above the upper surface in the first region and the second region and being insulated from the upper surface; forming a first trench using at least a first silicon etch, the first trench penetrating the first polysilicon layer and into the silicon substrate in the first region and the second region but not in the third region; filling the first trench with an insulating material; forming a second trench in the silicon substrate in the third region using at least a second silicon etch after the filling of the first trench to form an upwardly extending fin of the silicon substrate, the upwardly extending fin having a pair of side surfaces extending upwardly and terminating at a top surface; After the forming of the fin, forming a pair of material blocks over the first polysilicon layer in the first region, wherein the pair of material blocks are formed of polysilicon or insulating material; removing a portion of the first polysilicon layer in the first region to form a pair of floating gates of the first polysilicon layer, each of the floating gates being disposed below one of the pair of material blocks; performing a first implant to form a first source region in the silicon substrate in the first region between the pair of floating gates; forming a second polysilicon layer over the silicon substrate in the first region, the second region, and the third region; removing a portion of the second polysilicon layer to form: a first polysilicon block of the second polysilicon layer, the first polysilicon block being disposed above the first source region in the first region and insulated from the first source region, a second polysilicon block of the second polysilicon layer, the second polysilicon block being disposed above and insulated from the silicon substrate and adjacent to one of the pair of floating gates in the first region, a third polysilicon block of the second polysilicon layer, the third polysilicon block being disposed above and insulated from the silicon substrate and adjacent to the other floating gate of the pair of floating gates in the first region, a fourth polysilicon block of the second polysilicon layer, the fourth polysilicon block being disposed above the silicon substrate in the second region and insulated from the silicon substrate, and a fifth polysilicon block of the second polysilicon layer, the fifth polysilicon block being disposed above and insulated from the pair of side surfaces and the top surface of the fin in the third region; Perform one or more injections to form: a first drain region located in the first region of the substrate and adjacent to the second polysilicon block, a second drain region located in the first region of the substrate and adjacent to the third polysilicon block, a second source region located in the second region of the substrate and adjacent to the fourth polysilicon block, a third drain region located in the second region of the substrate and adjacent to the fourth polysilicon block, a third source region located in the fin and adjacent to the fifth polysilicon block, and a fourth drain region located in the fin and adjacent to the fifth polysilicon block; removing the fifth polycrystalline silicon block; forming a high-K material layer in the third region along the pair of side surfaces and the top surface of the fin; as well as A metal material block is formed on the high-K material layer in the third region such that the metal block extends along and is insulated from the pair of side surfaces and the top surface of the fin. 2 . The method of claim 1 , wherein the pair of material blocks are formed of polysilicon and are insulated from the pair of floating gates. 3 . The method of claim 2 , wherein the pair of material blocks are insulated from the pair of floating gates by an oxide-nitride-oxide layer. The method according to claim 1 , wherein the pair of material blocks are formed of an insulating material.

5. The method according to claim 1, the forming of the second trench comprising: forming a material layer over the upper surface in the third region; forming a third trench in the material layer; forming a material spacer in the third trench; removing the material layer; as well as The second silicon etch is performed in portions of the silicon substrate located between the material spacers.

6. The method according to claim 1, wherein the forming of the third source region and the fourth drain region comprises: Before removing the fifth polysilicon block, a material adjacent to the fifth polysilicon block is epitaxially grown on the fin, wherein the third source region and the fourth drain region are formed in the epitaxially grown material.

7. The method according to claim 1, wherein the second polysilicon block and the third polysilicon block are insulated from the upper surface of the substrate by an insulating material, and the thickness of the insulating material is smaller than the thickness of the insulating material insulating the floating gate from the upper surface. 8 . The method of claim 1 , wherein the fourth polysilicon block is insulated from the upper surface of the substrate by an insulating material having a thickness different from a thickness of an insulating material insulating the floating gate from the upper surface.

9. The method of claim 1, wherein the first trench extends deeper into the substrate than the second trench.

10. The method of claim 1, wherein the second trench extends deeper into the substrate than the first trench.

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