A floating gate type split-gate flash memory process method

Abstract

The application provides a floating gate type split-gate flash memory process method, which comprises the following steps: growing a floating gate oxide layer and a first silicon nitride layer on a P-type substrate; forming a P-type well, removing the first silicon nitride layer, and forming a silicon oxide layer, a second silicon nitride layer, a sacrificial silicon oxide layer and a third silicon nitride layer on a floating gate polysilicon layer; removing the third silicon nitride layer; depositing a fourth silicon nitride layer and forming a side wall; removing the fourth silicon nitride layer; removing the side wall and the sacrificial silicon oxide layer, the second silicon nitride layer, the silicon oxide layer, the floating gate polysilicon layer and the floating gate oxide layer; removing the fourth silicon nitride layer on the sacrificial silicon oxide layer and removing the exposed sacrificial silicon oxide layer; depositing a select gate medium layer, forming a select gate polysilicon layer and doping; forming a protective oxide layer on the top of the select gate polysilicon layer; removing the third and fourth silicon nitride layers; etching the sacrificial silicon oxide layer, the second silicon nitride layer, the silicon oxide layer and the floating gate polysilicon layer to form an LDD area; forming a first and a second side wall medium layer; and forming a source-drain heavily doped area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a floating-gate type split-gate flash memory process method. Background Technology

[0002] Split-gate flash memory technology is widely used in various embedded electronic products, such as financial IC cards and automotive electronics, because it can tolerate over-erasure effects. Increasing memory integration density helps save chip area and reduce manufacturing costs.

[0003] The structure of an existing 2-bit / cell (also known as NROM) charge-trapping flash memory is shown in the lower right figure, and its operation is shown in the lower left figure. This device structure has the following characteristics: the storage medium layer is a charge-trapping material, nitride. Utilizing the property that trapped charges cannot move freely within nitride, a single gate structure can form a localized charge storage region above the source and drain junctions, thus achieving 2-bit storage, as shown in the lower right figure. This device uses channel hot electron programming, band-to-band tunneling-generated hot holes for erasure, and reverse read operations for data reading, as shown in the lower left figure.

[0004] Because this device structure lacks a select-gate (SG), meaning it's not a gate-based structure, it cannot tolerate over-erasure effects. To avoid over-erasure, more complex peripheral circuitry is required to prevent it. Furthermore, the storage medium is nitride, and using a conductive floating gate material cannot achieve 2-bit storage. Compared to charge-trapping dielectric layers, because the floating gate is a conductive storage material, electrons injected above the source-drain junction and stored in the floating gate can be erased anywhere on the floating gate. Therefore, it avoids mismatch caused by different locations of charge injection during programming and erasure operations. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a floating gate type split-gate flash memory process method to solve the problem of programming and erasing mismatch caused by different positions of charge injected into the floating gate during programming and erasing operations.

[0006] To achieve the above and other related objectives, the present invention provides a floating-gate type split-gate flash memory process method, comprising at least:

[0007] Step 1: Provide a P-type substrate and grow a floating gate oxide layer on the P-type substrate; then grow a floating gate polysilicon layer and a first silicon nitride layer on the floating gate oxide layer in sequence; then form an STI region on the P-type substrate and define the active region at the same time.

[0008] Step 2: A medium-to-high voltage P-type well is formed by implantation in the active region, and the first silicon nitride layer is removed. Then, a silicon oxide layer, a second silicon nitride layer, a sacrificial silicon oxide layer, and a third silicon nitride layer are sequentially formed on the floating gate polysilicon layer. Next, the opening region of the flash memory cell area is defined by photolithography, and the third silicon nitride layer in the opening region is etched away using the sacrificial silicon oxide layer as an etch stop layer to form a groove. Then, a fourth silicon nitride layer is deposited, and a sidewall is formed on the fourth silicon nitride layer on the sidewall of the groove.

[0009] Step 3: Remove the fourth silicon nitride layer located between the sidewalls and on the sacrificial silicon oxide layer; then remove the sidewalls.

[0010] Step 4: Remove the exposed sacrificial silicon oxide layer and the second silicon nitride layer, the silicon oxide layer, the floating gate polysilicon layer, and the floating gate oxide layer below the exposed sacrificial silicon oxide layer;

[0011] Step 5: Remove the fourth silicon nitride layer on the sacrificial silicon oxide layer in the groove area, partially exposing the sacrificial silicon oxide layer, and remove the exposed sacrificial silicon oxide layer located on the second silicon nitride layer;

[0012] Step 6: Deposit a selected gate dielectric layer to cover the upper surface of the groove, then fill the groove with a selected gate polysilicon layer and dope the selected gate polysilicon layer; then grind the selected gate polysilicon layer with the third silicon nitride layer as a stop layer; finally, form a protective oxide layer on top of the selected gate polysilicon layer.

[0013] Step 7: Etch away the third and fourth silicon nitride layers; then, with the protective oxide layer and the selected gate dielectric layer as self-alignment, etch the sacrificial silicon oxide layer, the second silicon nitride layer, the silicon oxide layer, and the floating gate polysilicon layer in sequence, and implant to form LDD regions;

[0014] Step 8: Form a first sidewall dielectric layer and a second sidewall dielectric layer attached to the first sidewall dielectric layer; then perform source / drain heavy doping implantation to form source / drain heavy doped regions.

[0015] Preferably, in step one, the active region is defined by the process of forming the STI region, and the active region is the active region of the floating gate flash memory and the peripheral logic region.

[0016] Preferably, the fourth silicon nitride layer deposited in step two covers the bottom and sidewalls of the groove and the upper surface of the third silicon nitride layer.

[0017] Preferably, the method for forming the sidewall in step two is as follows: depositing polysilicon to fill the groove, and then using anisotropic etching to remove the polysilicon on the fourth silicon nitride layer at the bottom of the groove and on both sides of the groove, thereby forming a sidewall on the fourth silicon nitride layer of the groove sidewall.

[0018] Preferably, the method for removing the fourth silicon nitride layer between the sidewalls and on the sacrificial silicon oxide layer in step three is as follows: using the sidewalls as a mask, self-aligned etching is performed to remove the fourth silicon nitride layer.

[0019] Preferably, the method for removing the sidewall in step three is as follows: using the sacrificial silicon oxide layer, the third silicon nitride layer, and the fourth silicon nitride layer as masks, the sidewall is removed by wet etching.

[0020] Preferably, in step four, while etching the second silicon nitride layer, a portion of the third silicon nitride layer and the fourth silicon nitride layer are also etched.

[0021] Preferably, in step six, a protective oxide layer is formed on top of the selected gate polysilicon layer by thermal oxidation.

[0022] Preferably, the LDD region is formed by light doping implantation in step seven.

[0023] Preferably, in step eight, the source / drain heavily doped region 110 is formed by implanting Hao ions.

[0024] As described above, the floating gate type split-gate flash memory process method of the present invention has the following beneficial effects: The method of the present invention removes the conductive floating gate polysilicon layer by self-aligned etching in the middle of the gate to form two independent conductive floating gates. Therefore, it can realize the storage of two bits of data in the floating gate type conductive memory material. The introduction of a select gate device makes the device tolerant to over-erasure operations. In addition, this process is a self-aligned process, which can further reduce the area of ​​the flash memory cell, while not being limited by the photolithography process. Attached Figure Description

[0025] Figure 1 The diagram shows a cross-sectional view of the floating gate oxide layer, floating gate polysilicon layer, silicon nitride layer, and STI region formed in this invention in the width direction.

[0026] Figure 2 The diagram shows a cross-sectional view of the silicon oxide layer, silicon nitride layer, sacrificial silicon oxide layer, and second silicon nitride layer formed in this invention along the length direction.

[0027] Figure 3The diagram shows a cross-sectional view along the length of the invention after the fourth silicon nitride layer and sidewalls have been removed.

[0028] Figure 4 The diagram shows a cross-sectional view along the length of the structure after etching away the second silicon nitride layer, silicon oxide layer, floating gate polysilicon layer, and floating gate oxide layer in this invention.

[0029] Figure 5 The diagram shows a cross-sectional structure of the fourth silicon nitride layer and the exposed sacrificial silicon oxide layer after the removal of the sacrificial silicon oxide layer in this invention.

[0030] Figure 6 The diagram shows a cross-sectional view of the selected gate dielectric layer and the selected gate polysilicon layer in the longitudinal direction after they are formed in this invention.

[0031] Figure 7 The diagram shows a cross-sectional view along the length of the structure after the third and fourth silicon nitride layers are removed and the LDD region is formed in this invention.

[0032] Figure 8 The diagram shows a cross-sectional view of the first and second sidewall dielectric layers and the source / drain heavily doped regions in the longitudinal direction of this invention.

[0033] Figure 9 The figure shown is a simulation graph of the read current and voltage relationship curves of the device formed by the floating gate type split-gate flash memory process in this invention under programming and erasing conditions. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] This invention provides a floating-gate type split-gate flash memory process method, comprising at least:

[0037] Step 1: Provide a P-type substrate, and grow a floating gate oxide layer on the P-type substrate; then, sequentially grow a floating gate polysilicon layer and a silicon nitride layer on the floating gate oxide layer; next, form an STI region on the P-type substrate, and simultaneously define the active region; as follows... Figure 1 As shown, Figure 1 The diagram shows a cross-sectional view of the floating gate oxide layer, floating gate polysilicon layer, silicon nitride layer, and STI region formed in this invention along the width direction. In step one, a P-type substrate 101 is provided, and a floating gate oxide layer 102 is grown on the P-type substrate. Then, a floating gate polysilicon layer 103 and a silicon nitride layer 502 are sequentially grown on the floating gate oxide layer 102. Next, an STI region 501 is formed on the P-type substrate, simultaneously defining the active region. That is, the silicon nitride layer 502, the floating gate polysilicon layer 103, and the floating gate oxide layer 102 are etched from top to bottom, such that the floating gate oxide layer 102, the floating gate polysilicon layer 103, and the silicon nitride layer 502 are formed as shown... Figure 1 The multiple independent stacked structures shown have the silicon nitride layer 502, the floating gate polysilicon layer 103, and the floating gate oxide layer 102 on the STI region 501 removed.

[0038] Furthermore, in step one of this embodiment, the active region is defined by the process of forming the STI region 501, and the active region is the active region of the floating gate flash memory and the peripheral logic region.

[0039] Step 2: A medium-to-high voltage P-type well is formed by implantation in the active region, and the first silicon nitride layer is removed. Then, a silicon oxide layer, a second silicon nitride layer, a sacrificial silicon oxide layer, and a third silicon nitride layer are sequentially formed on the floating gate polysilicon layer. Next, the opening region of the flash memory cell area is defined by photolithography. Using the sacrificial silicon oxide layer as an etch stop layer, the third silicon nitride layer in the opening region is etched away to form a groove. Then, a fourth silicon nitride layer is deposited, and sidewalls are formed on the fourth silicon nitride layer on the sidewalls of the groove. Figure 2 As shown, Figure 2 The diagram shows a cross-sectional view of the silicon oxide layer, the second silicon nitride layer, the sacrificial silicon oxide layer, and the third silicon nitride layer formed in this invention along their length. In this invention, the length direction and the width direction are perpendicular to each other.

[0040] Step two involves implanting a medium-to-high voltage P-type well in the active region and removing the first silicon nitride layer 502. Then, a silicon oxide layer 104-1, a second silicon nitride layer 104-2, a sacrificial silicon oxide layer 503, and a third silicon nitride layer 504 are sequentially formed on the floating gate polysilicon layer 103. Next, photolithography defines the opening region of the flash memory cell area. Using the sacrificial silicon oxide layer 503 as an etch stop layer, the third silicon nitride layer 504 in the opening region is etched away to form a groove. Then, a fourth silicon nitride layer 505 is deposited, and a sidewall 506 is formed on the fourth silicon nitride layer 505 on the sidewall of the groove.

[0041] Furthermore, in step two of this embodiment, the fourth silicon nitride layer 505 deposited covers the bottom and sidewalls of the groove and the upper surface of the third silicon nitride layer 504.

[0042] In a further step of this invention, the method for forming the sidewall 506 in step two of this embodiment is as follows: polysilicon is deposited to fill the groove, and then anisotropic etching is used to remove the polysilicon on the fourth silicon nitride layer 505 at the bottom of the groove and on both sides of the groove, thereby forming the sidewall 506 on the fourth silicon nitride layer 505 on the sidewall of the groove.

[0043] Step 3: Remove the fourth silicon nitride layer located between the sidewalls and on the sacrificial silicon oxide layer; then remove the sidewalls; as shown. Figure 3 As shown, Figure 3 The diagram shows a cross-sectional view along the length direction after the fourth silicon nitride layer and sidewalls have been removed in this invention. In step three, the fourth silicon nitride layer 505 located between the sidewalls 506 and on the sacrificial silicon oxide layer 503 is removed; then the sidewalls 506 are removed.

[0044] In a further step of this invention, the method for removing the fourth silicon nitride layer 505 between the sidewalls 506 and on the sacrificial silicon oxide layer 503 in step three of this embodiment is as follows: using the sidewalls 506 as a mask, self-aligned etching is performed to remove the fourth silicon nitride layer 505.

[0045] In a further step of this invention, the method for removing the sidewall 506 in step three of this embodiment is as follows: using the sacrificial silicon oxide layer 503, the third silicon nitride layer 504, and the fourth silicon nitride layer 505 as masks, the sidewall 506 is removed by wet etching.

[0046] Step 4: Remove the exposed sacrificial silicon oxide layer and the second silicon nitride layer, the silicon oxide layer, the floating gate polysilicon layer, and the floating gate oxide layer below the exposed sacrificial silicon oxide layer. For example... Figure 4 As shown, Figure 4The diagram shows a cross-sectional view along the length of the structure after etching away the second silicon nitride layer, silicon oxide layer, floating gate polysilicon layer, and floating gate oxide layer in this invention. Step four removes the exposed sacrificial silicon oxide layer 503 and the second silicon nitride layer 104-2, silicon oxide layer 104-1, floating gate polysilicon layer 103, and floating gate oxide layer 102 below the exposed sacrificial silicon oxide layer 503.

[0047] Furthermore, in step four of this embodiment, while etching the second silicon nitride layer 104-2, a portion of the third silicon nitride layer 504 and the fourth silicon nitride layer 505 are also etched.

[0048] Step 5: Remove the fourth silicon nitride layer on the sacrificial silicon oxide layer within the groove region, partially exposing the sacrificial silicon oxide layer, and remove the exposed sacrificial silicon oxide layer located on the second silicon nitride layer; as... Figure 5 As shown, Figure 5 The diagram shows a cross-sectional structure after removing the fourth silicon nitride layer on the sacrificial silicon oxide layer and the exposed sacrificial silicon oxide layer in this invention. In step five, the fourth silicon nitride layer 505 on the sacrificial silicon oxide layer 503 in the groove region is removed, partially exposing the sacrificial silicon oxide layer 503, and the exposed sacrificial silicon oxide layer 503 located on the second silicon nitride layer 104-2 is removed.

[0049] Step Six: Deposit a selected gate dielectric layer to cover the upper surface of the groove, then fill the groove with a selected gate polysilicon layer and dope the selected gate polysilicon layer; next, use the third silicon nitride layer as a stop layer to grind the selected gate polysilicon layer; then form a protective oxide layer on top of the selected gate polysilicon layer; as shown. Figure 6 As shown, Figure 6 The diagram shows a cross-sectional view of the selected gate dielectric layer and the selected gate polysilicon layer in the longitudinal direction after they are formed in this invention.

[0050] In step six, a selected gate dielectric layer 105 is deposited to cover the upper surface of the groove. Then, a selected gate polysilicon layer 106 is filled into the groove and the selected gate polysilicon layer 106 is doped. Next, the selected gate polysilicon layer 106 is polished with the third silicon nitride layer 504 as a stop layer. Finally, a protective oxide layer 107 is formed on the top of the selected gate polysilicon layer 106.

[0051] In a further step of this invention, in step six of this embodiment, a protective oxide layer 107 is formed on top of the selected gate polysilicon layer 106 by thermal oxidation.

[0052] Step 7: Etch away the third and fourth silicon nitride layers; then, using the protective oxide layer and the select gate dielectric layer as self-alignments, sequentially etch the sacrificial silicon oxide layer, the second silicon nitride layer, the silicon oxide layer, and the floating gate polysilicon layer, and implant to form LDD regions; as shown Figure 7 As shown, Figure 7 The diagram shows a cross-sectional view along the length of the structure after the third and fourth silicon nitride layers are removed and the LDD region is formed, as described in this invention.

[0053] In step seven, the third silicon nitride layer 504 and the fourth silicon nitride layer 505 are etched away; then, the sacrificial silicon oxide layer 503, the second silicon nitride layer 104-2, the silicon oxide layer 104-1, and the floating gate polysilicon layer 103 are etched sequentially with the protective oxide layer 107 and the select gate dielectric layer 105 in self-alignment, and the LDD region 109 is implanted.

[0054] In a further step of this invention, the LDD region 109 in step seven of this embodiment is formed by light doping implantation.

[0055] Step 8: Form a first sidewall dielectric layer and a second sidewall dielectric layer attached to the first sidewall dielectric layer; then perform source / drain heavy doping implantation to form source / drain heavily doped regions. For example... Figure 8 As shown, Figure 8 The diagram shows a cross-sectional view of the first and second sidewall dielectric layers and the source / drain heavily doped regions in the longitudinal direction of this invention.

[0056] In step eight, a first sidewall dielectric layer 108-1 and a second sidewall dielectric layer 108-2 attached to the first sidewall dielectric layer 108-1 are formed; then, source / drain heavy doping implantation is performed to form a source / drain heavy doped region 110. Further, in this embodiment, step eight involves implanting Hao ions to form the source / drain heavy doped region 110.

[0057] like Figure 9 As shown, Figure 9 The figure shown is a simulation curve of the read current and voltage relationship of the device formed by the floating gate type split-gate flash memory process in this invention under programming and erasing conditions. The simulation results show that although the threshold voltage window of the device is only about 2.0V, the read current (Ir01 and Ir10) under the worst case of programming and erasing differs by 6 orders of magnitude.

[0058] In summary, the method of this invention removes the conductive floating gate polysilicon layer in the center of the gate through self-aligned etching, forming two independent conductive floating gates. This enables the storage of two bits of data in the floating gate conductive memory material. The introduction of a select gate device allows the device to tolerate over-erasure operations. Furthermore, this process is self-aligned, which can further reduce the area of ​​the flash memory cell, while being unrestricted by photolithography processes. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A floating gate type split-gate flash memory process method, characterized by, At least comprising: Step one, providing a P-type substrate, growing a floating gate oxide layer on the P-type substrate, then growing a floating gate polysilicon layer and a first silicon nitride layer on the floating gate oxide layer in sequence, then forming an STI region on the P-type substrate and defining an active region; Step two, implanting a medium-high voltage P-type well in the active region and removing the first silicon nitride layer, then forming a silicon oxide layer, a second silicon nitride layer, a sacrificial silicon oxide layer and a third silicon nitride layer on the floating gate polysilicon layer in sequence, then defining an opening region of a flash memory cell area by photolithography, etching and removing the third silicon nitride layer in the opening region with the sacrificial silicon oxide layer as an etching stop layer to form a groove, then depositing a fourth silicon nitride layer and forming a side wall on the fourth silicon nitride layer on the sidewall of the groove; Step three, etching and removing the fourth silicon nitride layer on the sacrificial silicon oxide layer between the side walls with the side wall as a mask to expose a part of the sacrificial silicon oxide layer, then removing the side wall; Step four, removing the exposed sacrificial silicon oxide layer and the second silicon nitride layer, the silicon oxide layer, the floating gate polysilicon layer and the floating gate oxide layer below the exposed sacrificial silicon oxide layer; Step five, removing the fourth silicon nitride layer on the sacrificial silicon oxide layer in the groove region to expose a part of the sacrificial silicon oxide layer and removing the exposed sacrificial silicon oxide layer on the second silicon nitride layer; Step six, depositing a select gate medium layer to cover the upper surface of the groove, then filling a select gate polysilicon layer in the groove and doping the select gate polysilicon layer, then grinding the select gate polysilicon layer with the third silicon nitride layer as a stop layer, then forming a protective oxide layer on the top of the select gate polysilicon layer; Step seven, etching and removing the third and fourth silicon nitride layers, then etching the sacrificial silicon oxide layer, the second silicon nitride layer, the silicon oxide layer and the floating gate polysilicon layer in sequence with the protective oxide layer and the select gate medium layer as a self-alignment etching stop layer and implanting an LDD region; Step eight, forming a first side wall medium layer and a second side wall medium layer adhered to the first side wall medium layer, then performing a source-drain heavy doping implantation to form a source-drain heavy doping region.

2. The floating gate type split-gate flash process method according to claim 1, wherein: In step one, the active region is defined by the process of forming the STI region, and the active region is the active region of the floating gate flash memory and the peripheral logic region.

3. The floating gate type split-gate flash process method according to claim 1, wherein: In step two, the fourth silicon nitride layer deposited covers the bottom and sidewall of the groove and the upper surface of the third silicon nitride layer.

4. The floating gate type split-gate flash process method according to claim 3, wherein: In step two, the method of forming the side wall is to fill the groove with polysilicon and then remove the polysilicon on the fourth silicon nitride layer on the bottom of the groove and both sides of the groove by anisotropic etching to form a side wall on the fourth silicon nitride layer on the sidewall of the groove.

5. The floating gate type split-gate flash process method of claim 1, wherein: In step three, the method of removing the side wall is to remove the side wall by wet etching with the sacrificial silicon oxide layer, the third silicon nitride layer and the fourth silicon nitride layer as a mask.

6. The floating gate type split-gate flash process method of claim 1, wherein: In step four, while etching the second silicon nitride layer, part of the third silicon nitride layer and the fourth silicon nitride layer will be etched.

7. The floating gate type split-gate flash process method of claim 1, wherein: In step six, a protective oxide layer is formed on top of the select gate polysilicon layer by thermal oxidation.

8. The floating gate type split-gate flash process method of claim 1, wherein: In step seven, the LDD region is formed by a light doping implant.

9. The floating gate type split-gate flash process method of claim 1, wherein: In step eight, the source / drain heavily doped region is formed by implanting Hao ions.

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