High-Voltage Transistor Structure and Method of Manufacturing the Same

Abstract

The present invention discloses a high-voltage transistor structure and a manufacturing method thereof. The high-voltage transistor structure includes a substrate. An epitaxial doping structure of a first conductivity type is formed in the substrate, wherein the top of the epitaxial doping structure includes an undoped epitaxial top layer. A gate structure is disposed on the substrate and at least overlaps the undoped epitaxial top layer. Source / drain regions of a second conductivity type are formed in the epitaxial doping structure on the sides of the gate structure. The first conductivity type is different from the second conductivity type.

Description

Technical Field

[0001] The present invention relates to semiconductor manufacturing, and particularly to a high-voltage transistor structure and a method for manufacturing the same. Background Art

[0002] With the diverse functions of electronic products, their control circuits need to be able to drive both high-voltage components operating at high voltages and low-voltage components operating at low voltages simultaneously. In response to the operation of high-voltage components and low-voltage components, for example, a power module needs to be able to provide a high-voltage power supply and a low-voltage power supply. The high-voltage circuit plays an important role in the control of the power module. That is to say, in order to increase more driving capabilities, the overall integrated circuit will include high-voltage transistors to drive different operations.

[0003] High-voltage transistors operate at relatively high voltages, and the breakdown voltage of the voltage transistors is an important factor determining their quality. A high-voltage transistor with a higher breakdown voltage can withstand high-voltage operation for a relatively long time without breakdown, and thus can also maintain the lifespan of the product.

[0004] In order to increase the breakdown voltage of high-voltage transistors, in addition to increasing the thickness of the gate insulating layer, the doping structure serving as the source and drain is also adjusted so that the channel of the transistor can operate normally and stably at high voltages.

[0005] The design of the doping structure of the source and drain affects the breakdown voltage of high-voltage transistors. Therefore, how to design the doping structure of the source and drain of high-voltage transistors is still under continuous research and development. Summary of the Invention

[0006] The present invention provides a structure of a high-voltage transistor and a method for manufacturing the same, in which the doping structure of the source and drain can effectively increase the breakdown voltage and also maintain a large operating current.

[0007] In one embodiment, the present invention provides a high-voltage transistor structure, which includes a substrate. An epitaxial doping structure of a first conductivity type is formed in the substrate. The top of the epitaxial doping structure includes an undoped epitaxial top layer. A gate structure is disposed on the substrate and at least overlaps the undoped epitaxial top layer. Source / drain regions of a second conductivity type are formed in the epitaxial doping structure on the sides of the gate structure. The first conductivity type is different from the second conductivity type.

[0008] In one embodiment, for the high-voltage transistor structure described above, the epitaxial doping structure includes a plurality of doped epitaxial layers below the undoped epitaxial top layer, and the doping concentration of the first conductivity type decreases downward.

[0009] In one embodiment, for the high-voltage transistor structure, the epitaxial doping structure includes an undoped epitaxial bottom layer connected to the substrate.

[0010] In one embodiment, for the high-voltage transistor structure, the substrate is a silicon substrate, and the epitaxial doping structure includes a plurality of silicon epitaxial layers. The top silicon epitaxial layer is the undoped epitaxial top layer, and the bottom silicon epitaxial layer is the undoped epitaxial bottom layer. A part of the plurality of silicon epitaxial layers between the undoped epitaxial top layer and the undoped epitaxial bottom layer is the doped epitaxial layer.

[0011] In one embodiment, for the high-voltage transistor structure, the first conductivity type is N conductivity type or P conductivity type, and the plurality of doped epitaxial layers are doped with N-type dopants or P-type dopants respectively.

[0012] In one embodiment, for the high-voltage transistor structure, the plurality of doped epitaxial layers include SiP of N conductivity type or SiGe of P conductivity type.

[0013] In one embodiment, for the high-voltage transistor structure, the gate structure includes a high-voltage gate insulating layer disposed on the substrate. A gate layer is disposed on the high-voltage gate insulating layer. Spacer walls are disposed on the substrate and on the sidewalls of the gate layer. The undoped epitaxial top layer is under the spacer walls and extends under the high-voltage gate insulating layer.

[0014] In one embodiment, the present invention also provides a method for manufacturing a high-voltage transistor, including providing a substrate. The manufacturing method further includes forming a recess in the substrate. Forming an epitaxial doping structure of a first conductivity type in the recess of the substrate, wherein the top of the epitaxial doping structure includes an undoped epitaxial top layer. Forming a gate structure on the substrate and at least overlapping the undoped epitaxial top layer. Forming source / drain regions of a second conductivity type in the epitaxial doping structure on the sides of the gate structure. The first conductivity type is different from the second conductivity type.

[0015] In one embodiment, for the method of manufacturing a high-voltage transistor, the formed epitaxial doping structure includes a plurality of doped epitaxial layers under the undoped epitaxial top layer, and the doping concentration of the first conductivity type decreases downward.

[0016] In one embodiment, for the method of manufacturing a high-voltage transistor, the formed epitaxial doping structure includes an undoped epitaxial bottom layer connected to the substrate.

[0017] In one embodiment, for the method of manufacturing a high-voltage transistor, the provided substrate is a silicon substrate, and the formed epitaxial doping structure includes a plurality of silicon epitaxial layers. The top silicon epitaxial layer is the undoped epitaxial top layer, the bottom silicon epitaxial layer is the undoped epitaxial bottom layer, and a part of the plurality of silicon epitaxial layers between the undoped epitaxial top layer and the undoped epitaxial bottom layer is the doped epitaxial layer.

[0018] In one embodiment, for the method of manufacturing a high-voltage transistor, the first conductivity type is N conductivity type or P conductivity type, and the plurality of doped epitaxial layers are doped with N-type dopants or P-type dopants respectively.

[0019] In one embodiment, for the method of manufacturing a high-voltage transistor, the plurality of doped epitaxial layers include SiP of N conductivity type or SiGe of P conductivity type.

[0020] In one embodiment, for the method of manufacturing a high-voltage transistor, the formed gate structure includes a high-voltage gate insulating layer disposed on the substrate. A gate layer is disposed on the high-voltage gate insulating layer. Spacer walls are disposed on the substrate and on the sidewalls of the gate layer. The undoped epitaxial top layer is under the spacer walls and extends under the high-voltage gate insulating layer.

[0021] In one embodiment, for the method of manufacturing a high-voltage transistor, the step of forming the epitaxial doping structure includes an in-situ doping process to form a plurality of doped epitaxial layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0023] Figure 1 is a schematic diagram of a high-voltage transistor structure according to an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a high-voltage transistor structure according to an embodiment of the present invention; and

[0025] Figures 3 to 4 is a schematic flowchart of forming an epitaxial doping structure according to an embodiment of the present invention.

[0026] REFERENCE NUMERAL DESCRIPTION

[0027] 100: Substrate

[0028] 102: High-voltage gate insulating layer

[0029] 104: Gate layer

[0030] 106: Spacer wall

[0031] 108: Doped region

[0032] 108a, 108b, 108c: Doped layer

[0033] 200: Substrate

[0034] 202: High-voltage gate insulating layer

[0035] 204: Gate layer

[0036] 206: Spacer wall

[0037] 208: Gate structure

[0038] 210: Undoped epitaxial bottom layer

[0039] 212, 214: Doped epitaxial layer

[0040] 218: Undoped epitaxial top layer

[0041] 220: Doped region

[0042] 230: Depression

[0043] 250: Epitaxial doping structure Detailed implementation mode

[0044] The present invention relates to a structure and a manufacturing method of a high-voltage transistor. Different conductivity-type epitaxial doping structures are added below the source and drain of the high-voltage transistor, which can effectively increase the breakdown voltage and maintain a large operating current.

[0045] For an integrated circuit that can operate at both high voltage and low voltage, the high-voltage transistor is a main component for high-voltage operation. The high-voltage transistor with a higher breakdown voltage can improve the quality and lifespan of the integrated circuit.

[0046] The present invention proposes a design of a high-voltage transistor that can effectively increase the breakdown voltage. The following presents multiple embodiments to illustrate the present invention, but the present invention is not limited to presenting multiple embodiments.

[0047] Before presenting the design of a high-voltage transistor that can increase the breakdown voltage, the present invention first explores the structure of a more straightforward high-voltage transistor, and then further proposes a high-voltage transistor that can effectively increase the breakdown voltage.

[0048] Figure 1 It is a schematic diagram of the structure of a high-voltage transistor explored according to an embodiment of the present invention. Refer to Figure 1, according to the structure of the field-effect transistor, in the metal-oxide-semiconductor (MOS) structure, such as a general low-voltage field-effect transistor, it is still based on the silicon substrate 100, on which a gate insulating layer 102, a gate layer 104, and spacer walls 106 on the sidewalls of the gate layer 104 are formed. In response to high-voltage operation, the thickness of the gate insulating layer 102 is increased to withstand high-voltage operation. In addition, the doped regions 108 serving as the source or drain are also formed in the substrate 100, on both sides of the gate layer 104. The high-voltage transistor can be a P-type transistor or an N-type transistor. In this embodiment, a P-type transistor is taken as an example, and its doped region 108 is of P-conductivity type. The conductivity type of the N-type transistor is opposite to that of the P-type transistor.

[0049] In order to increase the breakdown voltage of the transistor, the doped region 108, for example, adopts the control of the doping concentration. Using multiple doping processes, the doped region 108 has multiple doping layers according to different doping concentrations, for example, including a doping layer 108a, a doping layer 108b, and a doping layer 108c. The doping concentration decreases from the surface of the substrate 100 downward (gradient decreasing). For example, the doping concentration of the doping layer 108c is greater than that of the doping layer 108b. The doping concentration of the doping layer 108b is greater than that of the doping layer 108a.

[0050] Figure 1 For the high-voltage transistor structure in which the doped region 220 adopts a design with a decreasing concentration, the breakdown voltage can be increased, but it is observed after investigation that its operating current may still not be large enough. The present invention further proposes a high-voltage transistor structure that can increase the breakdown voltage and maintain a large operating current.

[0051] Figure 2 FIG. is a schematic diagram of a high-voltage transistor structure according to an embodiment of the present invention. Refer to Figure 2 , taking the substrate 200 as the structural basis of the high-voltage transistor. In this embodiment, a P-type high-voltage transistor is taken as an example for illustration. For an N-type high-voltage transistor, the conductivity type of its dopant can be replaced with an N-type dopant.

[0052] The high-voltage transistor structure includes a substrate 200. An epitaxial doping structure 250 having a first conductivity type, such as N conductivity type, is formed in the substrate 200. The epitaxial doping structure 250 forms a recess in the substrate 200, and then an epitaxial process is performed in the recess to form an epitaxial layer in the recess. During the formation of the epitaxial layer, in-situ doping is simultaneously employed, so that the epitaxial doping structure 250 includes multiple doped epitaxial layers 212, 214. Additionally, an undoped epitaxial top layer 218 is included on the top of the epitaxial doping structure 250. At the bottom of the epitaxial doping structure 250, in one embodiment, an undoped epitaxial bottom layer 210 is also included for interfacing with the substrate 200. The epitaxial doping structure 250 includes, for example, an undoped epitaxial bottom layer 210, a doped epitaxial layer 212, a doped epitaxial layer 214, and an undoped epitaxial top layer 218. This will be described in more detail later. Figure 3 and Figure 4 will be described in more detail.

[0053] A gate structure 208 is disposed on the substrate 200 and at least overlaps the undoped epitaxial top layer 218. A doping region 220 having a second conductivity type relative to the first conductivity type, such as P+, serves as the source / drain region of the transistor and is formed in the epitaxial doping structure 250 on the sides of the gate structure 208.

[0054] The gate structure 208 includes a high-voltage gate insulating layer 202 disposed on the substrate 200. The thickness of the high-voltage gate insulating layer 202 is adjusted to be sufficient to withstand high voltage according to the high voltage, and is not limited to a specific value. The gate layer 204 is, for example, a polysilicon layer disposed on the high-voltage gate insulating layer 202. Spacer walls 206 are disposed on the substrate 200 and on the sidewalls of the gate layer 204.

[0055] The undoped epitaxial top layer 218 is under the spacer walls 206 and extends under the high-voltage gate insulating layer 202. This undoped epitaxial top layer 218 overlaps with the gate layer 204 thereunder. The undoped epitaxial top layer 218 can produce a high-impedance effect and can further prevent voltage breakdown.

[0056] The first conductivity type is, for example, N-type, which is different from the second conductivity type of the doped region 220. The second conductivity type is P-type in this embodiment, denoted as P+. In the silicon epitaxial process, for example, phosphorus is used to provide the N-type dopant. That is, phosphorus combines with silicon to form the epitaxial material of SiP. According to the concentration of phosphorus, the doped epitaxial layer 212 and the doped epitaxial layer 214 are formed in sequence, and the concentration increases upward as indicated by the arrow, and the concentrations are denoted as N-- and N-. The undoped epitaxial bottom layer 210 and the undoped epitaxial top layer 218 are substantially free of phosphorus or the content is close to zero. The doped region 220 is formed by a subsequent implantation process, rather than an epitaxial process. Its concentration is P+, which acts as the source and drain, and will be formed in the epitaxial doping structure 250, covering a part of the undoped epitaxial top layer 218.

[0057] Herein, if an N-type high-voltage transistor is to be manufactured, the N-type dopant of phosphorus can be changed to a P-type dopant such as Ge, the material of the doped epitaxial layers 212 and 214 is changed to SiGe, and the doped region 220 acting as the source and drain is changed to N+ doping, which is formed by a subsequent implantation process.

[0058] Herein, the structure of the epitaxial doping structure 250 replaces Figure 1 the way of directly implanting into the substrate, which can effectively increase the drive current, and the control of the dopant can improve the breakdown voltage. The undoped epitaxial top layer 218 further provides a high-impedance effect, which can also improve the breakdown voltage.

[0059] Figures 3 to 4 is a schematic flow chart of forming an epitaxial doping structure according to an embodiment of the present invention. Refer to Figure 3 , in the substrate 200, for example, a recess 230 is first formed at a predetermined position using a mask layer and a wet etching process. Refer to Figure 4 , taking the structure of the N-type epitaxial doping structure 250 as an example, an epitaxial process of SiP is applied, and the content of phosphorus (P) determines the concentration of N-type doping. For the undoped epitaxial bottom layer 210 and the undoped epitaxial top layer 218, the content of phosphorus (P) is substantially zero. Herein, the geometric shape of the undoped epitaxial top layer 218 is only schematic, and actually it may not be a layer with equal thickness. It is like Figure 2 , it can extend under the gate layer 204 to provide a high-impedance effect. The number of the doped epitaxial layers 212 and 214 between the undoped epitaxial top layer 218 and the undoped epitaxial bottom layer 210 is multiple layers, not limited to the two layers in the embodiment. The undoped epitaxial top layer 218 can be formed by other suitable processes in semiconductor manufacturing, not limited to the epitaxial process. In addition, before forming the gate structure 208 subsequently, for example, a polishing and planarization process can also be applied first. That is, the process of forming the epitaxial doping structure 250 of the present invention can achieve the desired structure according to the processes available in semiconductor manufacturing technology.

[0060] In one embodiment, the present invention also provides a method of manufacturing a high-voltage transistor, which includes providing a substrate 200 as a structural basis for manufacturing. Next, a recess 230 is formed in the substrate 200. An epitaxial doping structure 250 of a first conductivity type, such as N-type, is formed in the recess 230 of the substrate 200. The top of the epitaxial doping structure 250 includes an undoped epitaxial top layer 218. A gate structure 208 is formed on the substrate 200 and at least overlaps the undoped epitaxial top layer 218. A doping region 220 of a second conductivity type, such as P-type, is formed in the epitaxial doping structure 250, on the sides of the gate structure 208. The first conductivity type, such as N-type, is different from the second conductivity type, such as P-type.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-voltage transistor structure, characterized in that, Comprising: A substrate; An epitaxial doping structure of a first conductivity type, formed in the substrate, wherein the top of the epitaxial doping structure includes an undoped epitaxial top layer, the epitaxial doping structure includes a plurality of doped epitaxial layers below the undoped epitaxial top layer, and the doping concentration of the first conductivity type decreases downward; A gate structure, disposed on the substrate and at least overlapping the undoped epitaxial top layer; And Source / drain regions of a second conductivity type, formed in the epitaxial doping structure and on the sides of the gate structure, Wherein the first conductivity type is different from the second conductivity type.

2. The high-voltage transistor structure according to claim 1, characterized in that The epitaxial doping structure includes an undoped epitaxial bottom layer connected to the substrate.

3. The high-voltage transistor structure according to claim 1, characterized in that, The substrate is a silicon substrate, and the epitaxial doping structure includes a plurality of silicon epitaxial layers, Wherein, the silicon epitaxial top layer is the undoped epitaxial top layer, the silicon epitaxial bottom layer is the undoped epitaxial bottom layer, and a part of the plurality of silicon epitaxial layers between the undoped epitaxial top layer and the undoped epitaxial bottom layer is the doped epitaxial layer.

4. The high-voltage transistor structure according to claim 1, characterized in that, The first conductivity type is N conductivity type or P conductivity type, and the plurality of doped epitaxial layers are respectively doped with N conductivity type dopants or P conductivity type dopants.

5. The high-voltage transistor structure according to claim 4, characterized in that, The plurality of doped epitaxial layers include SiP of N conductivity type or SiGe of P conductivity type.

6. The high-voltage transistor structure according to claim 1, characterized in that, The gate structure includes: A high-voltage gate insulating layer, disposed on the substrate; A gate layer, disposed on the high-voltage gate insulating layer; And A spacer, disposed on the substrate and on the sidewalls of the gate layer, Wherein the undoped epitaxial top layer is under the spacer and extends under the high-voltage gate insulating layer.

7. A method for manufacturing a high-voltage transistor, characterized in that, Comprising: Providing a substrate; Forming a recess in the substrate; Forming an epitaxial doping structure of a first conductivity type in the recess of the substrate, wherein the top of the epitaxial doping structure includes an undoped epitaxial top layer, the formed epitaxial doping structure includes a plurality of doped epitaxial layers below the undoped epitaxial top layer, and the doping concentration of the first conductivity type decreases downward; Forming a gate structure on the substrate and at least overlapping the undoped epitaxial top layer; And Forming source / drain regions of a second conductivity type in the epitaxial doping structure and on the sides of the gate structure, Wherein the first conductivity type is different from the second conductivity type.

8. The method of manufacturing a high-voltage transistor according to claim 7, characterized in that, The formed epitaxial doping structure includes an undoped epitaxial bottom layer connected to the substrate.

9. The method for manufacturing a high-voltage transistor according to claim 7, wherein The provided substrate is a silicon substrate, and the formed epitaxial doping structure includes a plurality of silicon epitaxial layers, Wherein, the silicon epitaxial top layer is the undoped epitaxial top layer, the silicon epitaxial bottom layer is the undoped epitaxial bottom layer, and a part of the plurality of silicon epitaxial layers between the undoped epitaxial top layer and the undoped epitaxial bottom layer is the doped epitaxial layer.

10. The method for manufacturing a high-voltage transistor according to claim 7, characterized in that, The first conductivity type is N conductivity type or P conductivity type, and the plurality of doped epitaxial layers are respectively doped with N conductivity type dopants or P conductivity type dopants.

11. The method for manufacturing a high-voltage transistor according to claim 10, characterized in that, The plurality of doped epitaxial layers include SiP of N conductivity type or SiGe of P conductivity type.

12. The method for manufacturing a high-voltage transistor according to claim 7, wherein, The formed gate structure includes: A high-voltage gate insulating layer, disposed on the substrate; A gate layer, disposed on the high-voltage gate insulating layer; and A spacer wall is disposed on the substrate and on the sidewalls of the gate layer. The undoped epitaxial top layer is under the spacer wall and extends under the high-voltage gate insulating layer.

13. The method for manufacturing a high-voltage transistor according to claim 7, characterized in that, The step of forming the epitaxial doping structure includes an in-situ doping process to form a plurality of doped epitaxial layers.

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