Semiconductor structure and its fabrication method

Abstract

The present invention provides a semiconductor structure comprising a resistive random access memory (RRAM), a first spacer structure located on both sides of the resistive random access memory, a second spacer structure located outside the first spacer structure, wherein the second spacer structure comprises a metal material or a metal oxide material, and a third spacer structure located outside the second spacer structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a resistive random access memory (RRAM) with a reinforced spacer wall structure. Background Technology

[0002] Resistive random access memory (RRAM) offers advantages such as simple structure, low operating voltage, high operating speed, good durability, and compatibility with CMOS fabrication processes. RRAM is the most promising alternative to traditional flash memory, enabling the reduction of device size. RRAM is widely used in various devices, such as optical discs and non-volatile memory arrays.

[0003] RRAM cells store data within material layers capable of undergoing phase transitions. Within all or part of these layers, the material can initiate a phase transition, switching between high-resistance and low-resistance states. These different resistance states, once detected, can be represented as "0" or "1". In a typical RRAM cell, the data storage layer comprises an amorphous metal oxide. Applying a sufficient voltage creates a metal bridge across the data storage layer, resulting in a low-resistance state. This bridge can then be broken by applying a high-current-density pulse or otherwise decomposing or melting all or part of the metal structure, restoring the high-resistance state. When the data storage layer is then rapidly cooled, it transitions back to a low-resistance state. Summary of the Invention

[0004] The present invention provides a semiconductor structure comprising a resistive random access memory (RRAM), a first spacer structure located on both sides of the resistive random access memory, a second spacer structure located outside the first spacer structure, wherein the second spacer structure comprises a metal material or a metal oxide material, and a third spacer structure located outside the second spacer structure.

[0005] The present invention also provides a method for fabricating a semiconductor structure, comprising providing a resistive random access memory (RRAM), forming a first gap wall junction on both sides of the resistive random access memory, forming a second gap wall structure on the outside of the first gap wall structure, wherein the second gap wall structure comprises a metal material or a metal oxide material, and forming a third gap wall structure on the outside of the second gap wall structure.

[0006] In some embodiments of the present invention, the spacer structure of the resistive random access memory is strengthened. Furthermore, a second spacer and a third spacer are added outside and above the first spacer. Since the material of the second spacer includes metal, metal oxide, metal nitride, etc., which is significantly different from the material properties of the first or third spacer, and the second spacer has a sufficient thickness to cover the top of the first spacer, the second spacer can effectively protect the resistive random access memory, especially the area between the resistive random access memory and the spacer, when an opening is created by the etching process. This prevents the formation of gaps in this area, which would allow the subsequently formed conductive layer to fill the gaps and affect the performance of the resistive random access memory. Attached Figure Description

[0007] Figures 1 to 2 This is a schematic diagram of a semiconductor structure fabricated according to a first preferred embodiment of the present invention.

[0008] Figures 3 to 6 This is a schematic diagram of a semiconductor structure fabricated according to a second preferred embodiment of the present invention.

[0009] Figures 7 to 9 This is a schematic diagram of a semiconductor structure fabricated according to a third preferred embodiment of the present invention.

[0010] Explanation of main component symbols

[0011] 100.........................Resistive Random Access Memory

[0012] 101.........................wire

[0013] 102.........................Dielectric layer

[0014] 103.........................Dielectric layer

[0015] 104.........................Contact Structure

[0016] 110.........................lower electrode

[0017] 112.........................Resistor Transformer Layer

[0018] 114.........................Upper Electrode

[0019] 116.........................First gap wall

[0020] 117.........................Dielectric layer

[0021] 118.........................Dielectric layer

[0022] 120.........................Contact Structure

[0023] 122.........................Tip

[0024] 124.........................Second spacer wall

[0025] 124'........................Second spacer wall material layer

[0026] 126.........................Third interstitial wall

[0027] 126'........................Third gap wall material layer

[0028] 130.........................Dielectric layer

[0029] 132.........................Contact Structure

[0030] T1..........................thickness Detailed Implementation

[0031] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0032] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art as referring to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0033] Please refer to Figures 1 to 2 , Figures 1 to 2 A schematic diagram illustrating the fabrication of a semiconductor structure according to a first preferred embodiment of the present invention is shown. Figure 1 As shown, a resistive random access memory (RRAM) 100 is first provided and electrically connected to a contact structure 104. The contact structure 104 may be located within a single or multiple dielectric layers, and may be electrically connected to another contact structure or a wire below it. In this embodiment, the contact structure 104 is located within dielectric layers 103 and 117. Below the contact structure 104, there is another wire 101, which is electrically connected to the contact structure. The wire 101 is located within dielectric layer 102. The dielectric layers 102 and 117 described here are, for example, one layer of an intermetallic dielectric (IMD) layer in a semiconductor structure. Dielectric layer 103 may be a pad layer, and the wire 101 and contact structure 104 may be, for example, wires or vias located within the IMD. The dielectric layers 102, 103 and 117 may be made of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, while the contact structure 104 may contain conductive materials such as metals such as tungsten, cobalt, copper, and aluminum, or other conductive materials. This invention is not limited to these.

[0034] The resistive random access memory 100 is located on the dielectric layer 102 and is electrically connected to the contact structure 104. Generally, the resistive random access memory 100 may include at least a lower electrode 110, a resistive switching layer 112, and an upper electrode 114. The lower electrode 110 and the upper electrode 114 are made of conductive materials such as titanium, tantalum, titanium nitride, and tantalum nitride. The resistivity conversion layer 112 contains a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium siliconoxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicate oxide (ZrSiO4), and hafnium zirconium oxide. The group consisting of oxides, HfZrO4, strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST), or combinations thereof.

[0035] In addition to the materials mentioned above, the resistive random access memory 100 may also contain more material layers, which are also within the scope of this invention. Taking one embodiment of this invention as an example, the resistive random access memory 100, from bottom to top, includes a lower electrode (made of TaN), a resistive conversion layer (made of Ta2O5), a metal layer (made of iridium (Ir)), and an upper electrode (made of TaN). This structure is also within the scope of this invention. However, it is worth noting that this structure is only one example of this invention, and resistive random access memories composed of other materials are also within the scope of this invention.

[0036] After the resistive random access memory 100 is formed, a first spacer wall 116 is formed on the side of the resistive random access memory 100. The function of the first spacer wall 116 is to protect the resistive random access memory 100. The material of the first spacer wall 116 is, for example, silicon nitride. It is also worth noting that in this embodiment, before forming the first spacer wall 116, the dielectric layer 102 surrounding the resistive random access memory 100 may be partially etched, and then the first spacer wall 116 may be formed by deposition, etch-back, or other methods. Therefore, the top surface of the first spacer wall 116 may be lower than the top surface of the upper electrode 114. In addition, an L-shaped dielectric layer 117 may be formed below the first spacer wall 116 due to etching.

[0037] Then as Figure 2 As shown, a dielectric layer 118 is formed above the resistive random access memory 100, and another contact structure 120 is located within the dielectric layer 118. The contact structure 120 is electrically connected to the upper electrode 114 of the resistive random access memory 100. The contact structure 120 described herein is, for example, another conductive via in a semiconductor structure, used to connect the resistive random access memory 100 to other cells of the semiconductor element via a conductive via or wire.

[0038] However, as Figure 2 As shown, the applicant discovered that in one embodiment of the present invention, when forming the contact structure 120 to electrically connect the upper electrode 114 of the resistive random access memory 100, an etching step is required to form an opening (not shown) in the dielectric layer 118 and expose the upper electrode 114. Then, conductive material is filled into the opening to form the contact structure 120. However, in some embodiments, when the alignment between the opening and the upper electrode is offset, or when the size of the opening is larger than the size of the upper electrode 114, the opening will also expose a portion of the first gap wall 116 adjacent to the upper electrode 114. The upper electrode 114 and the first gap wall 116 contain different materials, and the interface between them is prone to forming a weak point. During the etching process, etching may be performed from this weak point, creating a gap between the upper electrode 114 and the first gap wall 116. This causes the conductive material to be filled into the gap along with the opening, resulting in a tip 122 (at the same location as the aforementioned weak point) in the contact structure 120 located between the upper electrode 114 and the first gap wall 116. The tip 122 of the contact structure 120 may affect the quality of the semiconductor device and negatively impact the yield of the semiconductor manufacturing process.

[0039] To avoid the above situation, in another embodiment of the present invention, the spacer wall structure next to the resistive random access memory 100 is strengthened to prevent gaps from forming between the resistive random access memory and the spacer wall during the etching process, which would affect the quality of the semiconductor device. Please refer to the following. Figures 3 to 6 .

[0040] Figures 3 to 6 A schematic diagram illustrating the fabrication of a semiconductor structure according to a second preferred embodiment of the present invention is shown. In this embodiment, as... Figure 3 As shown, where Figure 3 Continued Figure 1 The steps shown form as follows Figure 1 The structure shown (including resistive random access memory 100 and first spacer 116, etc.) will not be processed yet. Figure 2 Instead of the steps shown, a second spacer material layer (not shown) is additionally formed above and outside the first spacer wall 116. Then, an etching step or a planarization step is performed to remove part of the second spacer material layer, exposing the upper electrode 114 of the resistive random access memory 100. The remaining second spacer material layer is defined as the second spacer wall 124. In this embodiment, the second spacer wall 124 covers the upper and sidewalls of the first spacer wall 116 and directly contacts the first spacer wall 116. In this embodiment, the second spacer wall 124 is selected from a material different from the first spacer wall 116, and the two materials have a sufficient etch selectivity. Preferably, the material of the second spacer wall 124 can be selected from metals, metal oxides, metal nitrides, etc., which are different from general dielectric layers (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.), so that it is not easily removed during the etching process. In this embodiment, the material of the second spacer wall 124 is, for example, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, aluminum nitride, aluminum oxide, etc., but the invention is not limited to these.

[0041] Furthermore, viewed from a vertical direction, for example Figure 3 In the longitudinal direction, the second spacer wall 124 covers the first spacer wall 116 with a thickness of more than 20 nanometers, for example... Figure 3 The thickness T1 shown is between 20 nanometers and 60 nanometers in some embodiments to effectively protect the first spacer wall 116 and the resistive random access memory 100. Furthermore, due to the planarization or etch-back step performed on the second spacer wall material layer in this embodiment, a top surface of the resistive random access memory 100 (i.e., the top surface of the upper electrode 114) and a top surface of the second spacer wall 124 are flush with each other.

[0042] Next, as Figure 4As shown, a third spacer material layer (not shown) is formed, for example, by deposition, covering the second spacer 124 and the resistive random access memory 100. A subsequent etching step or planarization step can be performed to remove part of the third spacer material layer, exposing the upper electrode 114 of the resistive random access memory 100. The remaining third spacer material layer is defined as the third spacer 126. In this embodiment, the material of the third spacer 126 is, for example, silicon oxide, but it is not limited to this.

[0043] In this embodiment, the first gap wall 116, the second gap wall 124, and the third gap wall 126 are made of different materials. Furthermore, the first gap wall 116 and the third gap wall 126 can be made of non-conductive dielectric materials, while the second gap wall 124, located between the first gap wall 116 and the third gap wall 126, is preferably made of a metal (e.g., titanium or tantalum). Because its material properties differ significantly from those of dielectric materials, it has a relatively higher etching selectivity, thus effectively protecting the resistive random access memory 100.

[0044] Please refer to the following: Figure 5 and Figure 6 ,like Figure 5 As shown, a dielectric layer 130 is formed covering the resistive random access memory 100 and the third spacer wall 126. The dielectric layer 130 is, for example, an ultra-low-k (ULK) dielectric material, preferably with a dielectric constant below 2.9, but not limited to this. Commonly used ULK materials may include Black Diamond (a low-dielectric-coefficient material of carbon-doped silicon oxide from Applied Materials), MSQ (methylsilsesquioxane), porous SiLK (a low-dielectric-coefficient material developed by Dow Chemical), etc., but are not limited to these. Then, as... Figure 6 As shown, an opening (not shown) is formed in the dielectric layer 130, and after filling the opening with a conductive material (not shown), planarization and other steps are performed to form a contact structure 132 in the opening. The contact structure 132 is electrically connected to the upper electrode 114 of the resistive random access memory 100. The contact structure 132 may contain a conductive material, such as tungsten, cobalt, copper, aluminum, etc.

[0045] Compared with the first embodiment described above ( Figures 1-2In contrast, this embodiment strengthens the spacer structure of the resistive random access memory 100. Furthermore, a second spacer 124 and a third spacer 126 are added outside and above the first spacer 116. Since the material of the second spacer 124 includes metal, metal oxide, metal nitride, etc., it has a significantly different material properties from the first spacer 116 or the third spacer 126. Moreover, the second spacer 124 (greater than 20 nanometers) has a sufficient thickness to cover the top of the first spacer 116. Therefore, when an opening is created through the etching process, the second spacer 124 can effectively protect the resistive random access memory 100, especially the area between the resistive random access memory 100 and the spacer, preventing the formation of gaps in this area, which would allow the subsequently formed conductive layer to fill the gaps and affect the performance of the resistive random access memory 100.

[0046] The following description will focus on different embodiments of the semiconductor structure and its fabrication method of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0047] In the second embodiment described above Figures 3-4 After forming the second and third spacer wall material layers, an etch-back step or a planarization step is performed to partially remove the second and third spacer wall material layers, exposing the upper electrode 114 of the resistive random access memory 100. However, in other embodiments of the present invention, the planarization or etch-back step may be omitted. Please refer to... Figures 7-9 , Figures 7 to 9 A schematic diagram illustrating the fabrication of a semiconductor structure according to a third preferred embodiment of the present invention is shown. Figure 7 Continued Figure 1 The steps shown form as follows Figure 1 Following the structure shown (including resistive random access memory 100 and first spacer 116, etc.), a second spacer material layer 124' is formed above and outside the first spacer 116. Then, the planarization or etch-back steps are temporarily omitted, so the second spacer material layer 124' will cover the top of the upper electrode 114. Next, a patterning step can be performed to partially remove the entire second spacer material layer 124' to prevent conduction with adjacent circuit components. Next, as... Figure 8As shown, a third spacer material layer 126' is formed above and outside the second spacer material layer 124', and subsequently, the third spacer material layer 126' is not subjected to a planarization step or an etch-back step. In this way, compared with the second embodiment, the manufacturing process used in this embodiment is simpler, and since both the second spacer material layer 124' and the third spacer material layer 126' directly cover the top of the upper electrode 114, the upper electrode 114 can be better protected.

[0048] The following is as follows Figure 9 As shown, after forming the dielectric layer 130, it is preferable to form an opening (not shown) in the dielectric layer 130 through multiple etching steps. The opening extends through a portion of the third spacer material layer 126' and the second spacer material layer 124'. Then, a conductive material is filled into the opening to form a contact structure 132 for electrical connection to the upper electrode 114. The remaining second spacer material layer 124' and third spacer material layer 126' are then defined as the second spacer 124 and the third spacer 126, respectively. The dielectric layer 130 is made of, for example, ULK material, and the contact structure 132 contains, for example, a conductive metal. The features of this part are the same as described in the second embodiment above, and will not be repeated here.

[0049] In addition, since no planarization or etch-back step is performed on the second spacer wall material layer in this embodiment, a top surface of the resistive random access memory 100 (i.e., the top surface of the upper electrode 114) is lower than a top surface of the second spacer wall 124. This embodiment is also within the scope of the present invention.

[0050] In summary Figures 1-9 In one embodiment of the present invention, a semiconductor structure is provided, comprising a resistive random access memory (RRAM), a first spacer structure located on both sides of the resistive random access memory, a second spacer structure located outside the first spacer structure, wherein the second spacer structure comprises a metal material or a metal oxide material, and a third spacer structure located outside the second spacer structure.

[0051] In some embodiments of the present invention, the material of the first spacer wall structure comprises silicon nitride.

[0052] In some embodiments of the present invention, the material of the third spacer wall structure comprises silicon oxide.

[0053] In some embodiments of the present invention, the material of the second spacer wall structure includes titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, aluminum nitride, and aluminum oxide.

[0054] In some embodiments of the present invention, a contact structure is also included, located on a top surface of the resistive random access memory and electrically connected to the resistive random access memory.

[0055] In some embodiments of the invention, the top surface of the resistive random access memory and the top surface of the second gap wall structure are flush with each other.

[0056] In some embodiments of the invention, the top surface of the resistive random access memory is lower than a top surface of the second spacer wall structure.

[0057] In some embodiments of the invention, when viewed along a vertical direction, the second gap wall structure covers a portion of the first gap wall structure.

[0058] In some embodiments of the present invention, the second spacer wall structure covers a portion of the first spacer wall structure with a thickness between 20 nanometers and 60 nanometers.

[0059] In some embodiments of the present invention, a dielectric layer is further included covering the third spacer structure, wherein the dielectric layer is made of an ultra-low dielectric constant material.

[0060] In another embodiment of the present invention, a method for fabricating a semiconductor structure includes providing a resistive random access memory (RRAM), forming a first gap wall junction on both sides of the resistive random access memory, forming a second gap wall structure on the outside of the first gap wall structure, wherein the second gap wall structure comprises a metallic material or a metal oxide material, and forming a third gap wall structure on the outside of the second gap wall structure.

[0061] In some embodiments of the present invention, the material of the first spacer wall structure comprises silicon nitride.

[0062] In some embodiments of the present invention, the material of the third spacer wall structure comprises silicon oxide.

[0063] In some embodiments of the present invention, the material of the second spacer wall structure includes titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, aluminum nitride, and aluminum oxide.

[0064] In some embodiments of the present invention, a contact structure is formed on a top surface of the resistive random access memory and electrically connected to the resistive random access memory.

[0065] In some embodiments of the invention, the top surface of the resistive random access memory and the top surface of the second gap wall structure are flush with each other.

[0066] In some embodiments of the invention, the top surface of the resistive random access memory is lower than a top surface of the second spacer wall structure.

[0067] In some embodiments of the invention, when viewed along a vertical direction, the second gap wall structure covers a portion of the first gap wall structure.

[0068] In some embodiments of the present invention, the thickness of the second spacer wall structure covering a region of the first spacer wall structure is between 20 nanometers and 60 nanometers.

[0069] In some embodiments of the present invention, a dielectric layer is further included covering the third spacer structure, wherein the dielectric layer is made of an ultra-low dielectric constant material.

[0070] In summary, in some embodiments of the present invention, the spacer structure of the resistive random access memory is strengthened. Furthermore, a second spacer and a third spacer are added outside and above the first spacer. Since the material of the second spacer includes metal, metal oxide, metal nitride, etc., which is significantly different from the material properties of the first or third spacer, and the second spacer has a sufficient thickness to cover the top of the first spacer, the second spacer can effectively protect the resistive random access memory, especially the area between the resistive random access memory and the spacer, when an opening is created by the etching process. This prevents gaps from forming in this area, which would allow the subsequently formed conductive layer to fill the gaps and affect the performance of the resistive random access memory.

[0071] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising: Resistive random access memory (RRAM) includes a lower electrode, a resistive switching layer, and a upper electrode; The first gap wall structure is located on both sides of the resistive random access memory; A second gap wall structure is located outside the first gap wall structure, with a portion of the second gap wall structure situated above the first gap wall structure and directly contacting the sidewall of the upper electrode. The second gap wall structure comprises a metallic material or a metal oxide material, and the top edge of the interface between the first gap wall structure and the upper electrode is covered by the second gap wall structure. The third gap wall structure is located outside the second gap wall structure.

2. The semiconductor structure of claim 1, wherein the material of the first spacer structure comprises silicon nitride.

3. The semiconductor structure of claim 1, wherein the material of the third spacer structure comprises silicon oxide.

4. The semiconductor structure of claim 1, wherein the material of the second spacer structure comprises titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, aluminum nitride, and aluminum oxide.

5. The semiconductor structure of claim 1, further comprising a contact structure located on the top surface of the resistive random access memory and electrically connected to the resistive random access memory.

6. The semiconductor structure of claim 1, wherein the top surface of the resistive random access memory and the top surface of the second spacer structure are flush with each other.

7. The semiconductor structure of claim 1, wherein the top surface of the resistive random access memory is lower than the top surface of the second spacer structure.

8. The semiconductor structure of claim 1, wherein, viewed along a vertical direction, the second spacer structure covers a portion of the first spacer structure.

9. The semiconductor structure of claim 8, wherein the second spacer structure covers a portion of the first spacer structure with a thickness between 20 nanometers and 60 nanometers.

10. The semiconductor structure of claim 1, further comprising a dielectric layer covering the third spacer structure, wherein the dielectric layer is made of an ultra-low dielectric constant material having a dielectric constant of less than 2.

9.

11. A method for fabricating a semiconductor structure, comprising: It provides resistive random access memory (RRAM), which includes a lower electrode, a resistive switching layer, and a upper electrode; A first gap wall structure is formed on both sides of the resistive random access memory; A second gap wall structure is formed outside the first gap wall structure, wherein a portion of the second gap wall structure is located above the first gap wall structure and directly contacts the sidewall of the upper electrode. The second gap wall structure comprises a metallic material or a metal oxide material, wherein the top of the interface between the first gap wall structure and the upper electrode is covered by the second gap wall structure; and A third gap wall structure is formed on the outside of the second gap wall structure.

12. The fabrication method of claim 11, wherein the material of the first spacer wall structure comprises silicon nitride.

13. The manufacturing method of claim 11, wherein the material of the third spacer wall structure comprises silicon oxide.

14. The manufacturing method of claim 11, wherein the material of the second spacer wall structure comprises titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, aluminum nitride, and aluminum oxide.

15. The manufacturing method of claim 11, further comprising forming a contact structure on the top surface of the resistive random access memory and electrically connecting it to the resistive random access memory.

16. The manufacturing method of claim 11, wherein the top surface of the resistive random access memory and the top surface of the second spacer wall structure are flush with each other.

17. The manufacturing method of claim 11, wherein the top surface of the resistive random access memory is lower than the top surface of the second spacer wall structure.

18. The manufacturing method of claim 11, wherein, viewed along a vertical direction, the second gap wall structure covers a portion of the first gap wall structure.

19. The fabrication method of claim 18, wherein the thickness of the second spacer wall structure covering a region of the first spacer wall structure is between 20 nanometers and 60 nanometers.

20. The manufacturing method of claim 11, further comprising forming a dielectric layer covering the third spacer structure, wherein the dielectric layer is made of an ultra-low dielectric constant material having a dielectric constant of less than 2.9.

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