Gate drive module and circuit configuration

Abstract

The present invention relates to a gate driver module for switching power transistors on and off. The gate driver module comprises at least two switchable voltage sources and at least two outputs to which switch-on and switch-off resistors can be connected. A configuration unit is provided in which a higher-level circuit configuration of the gate driver module is stored or can be recorded. The gate driver module comprises a logic unit configured to receive a PWM signal from a higher-level control unit and to switch the switchable voltage sources based on the signal. The logic unit is configured to store the PWM signal for at least one clock cycle. The gate driver module comprises a fault unit configured to forward internal faults of the gate driver module to at least one adjacent gate driver module and / or the control unit and to receive fault messages from at least one adjacent gate driver module and / or the control unit. The logic unit is configured to generate a PWM signal based on the fault message, the circuit configuration, and the stored PWM signal.

Description

Technical Field

[0001] The present invention relates to a gate driving module and a circuit configuration having a plurality of gate driving modules. Background Art

[0002] Such gate driver modules are used to switch power transistors on and off, which can be connected in various circuit configurations. Examples include AC voltage rectifiers with, for example, three half-bridges or three-level half-bridge circuits, each with four power transistors. In the event of a fault, these gate driver modules must disconnect the defective power transistor.

[0003] DE 10351033 A1 discloses an integrated gate driver circuit for switching power transistors using external control. The integrated gate driver circuit detects desaturation of a power transistor and protects the desaturated transistor from transient overvoltages by softly switching it off via a soft switch-off sequence. A fault control circuit in the integrated gate driver circuit protects against supply undervoltages, and transistor desaturation can be communicated to multiple integrated gate driver circuits in a multiphase system using a dedicated local area network. Summary of the Invention

[0004] The technical problem underlying the present invention is to provide an improved gate driver module and a circuit arrangement having such a gate driver module.

[0005] The solution to this technical problem is achieved by the gate driver module according to the invention and the circuit arrangement according to the invention.

[0006] To this end, a gate driver module for switching power transistors on and off includes at least two switchable voltage sources and at least two outputs to which switch-on and switch-off resistors can be connected. The gate driver module also includes a configuration unit in which a higher-level circuit configuration of the gate driver module relative to other gate driver modules is stored or recorded. For example, the higher-level circuit configuration is transmitted and stored by a higher-level control unit. Additionally or alternatively, this configuration may be encoded using discrete circuits that can then be read or recorded by the configuration unit. For example, the gate driver module knows that it is part of a three-level half-bridge circuit and controls the topmost power transistor. In other words, the gate driver module knows the higher-level circuit configuration and its position within the circuit configuration. The gate driver module also includes a logic unit that is configured to receive a PWM signal from a higher-level control unit and switch the switchable voltage source based on the PWM signal, wherein the logic unit is configured to store at least one clock cycle of the PWM signal. The gate driver module also includes at least one fault unit configured to forward at least one internal fault of the gate driver module to at least one adjacent gate driver module and / or a higher-level control unit and to receive fault messages from at least one adjacent gate driver module and / or a higher-level control unit. The logic unit is further configured to generate a PWM signal based on the fault message of the fault unit, a stored or recorded circuit configuration, and a stored PWM signal to disconnect the connected power transistor, such that the disconnection procedure required for safe disconnection is adhered to if the PWM signal from the higher-level control unit is lost or absent. Thus, if a power transistor in the circuit configuration fails, the power transistors to be disconnected can be disconnected in a predetermined disconnection sequence to avoid adverse effects such as overvoltages in adjacent power transistors. For example, if the topmost gate driver module in a three-level half-bridge circuit detects a fault in its assigned power transistor, it first notifies the other three gate driver modules. Subsequently, the two internal gate driver modules then disconnect their power transistors, followed by the two external gate driver modules. That is, the defective power transistors are not immediately switched off, regardless of the other power transistors. Rather, they are driven in a controlled manner, possibly in a plurality of cycles.

[0007] In the event of a lost or absent control signal (PWM), the shutdown procedure required for safe shutdown is therefore adhered to and impermissibly high voltages cannot build up across the power transistors at any time.

[0008] In one embodiment, the gate driver module is configured to receive at least the temperature of the power transistors and / or the output current of the power transistors, as these parameters allow the most frequently occurring fault conditions to be determined. However, other parameters, such as the voltage load of the power transistors, may also be received. Based on these parameters, future faults can then be predicted or estimated, for example.

[0009] In another embodiment, the gate driver module has at least one third switchable output, to which at least one current source can be switched in parallel with the input and output resistors. The at least one current source can be arranged outside the gate driver module, like the input and output resistors, or else integrated into the gate driver module, like a voltage source. By means of a switchable current source, for example, the switch-on process can be accelerated, after which the current source is switched off again. It is also possible to use such a current source for rapid switching, with the gate state then being maintained by a voltage source during static operation. The design with a third switchable output without a logic unit, a fault unit, and a configuration unit is also an independent invention.

[0010] The circuit configuration has a plurality of gate drive modules, wherein the fault units of the gate drive modules are connected to each other in a daisy-chain manner, so that local control of the circuit configuration can be achieved.

[0011] In another embodiment, higher-level control units are integrated into the daisy chain, so that further faults can also be transmitted.

[0012] In another embodiment, the circuit configuration is configured as a 3-level half-bridge circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Subsequently, the present invention will be described in more detail based on preferred embodiments.

[0014] Figure 1 A schematic block circuit diagram of a gate drive module with an external circuit is shown;

[0015] Figure 2 shows a 3-level half-bridge circuit as a circuit configuration with a daisy chain without a higher-level control unit; and

[0016] Figure 3 A 3-level half-bridge circuit is shown as a circuit configuration of a daisy chain with incorporated higher-level control units. DETAILED DESCRIPTION

[0017] exist Figure 1In FIG. 1 , a schematic block circuit diagram of a gate driver module 1 for switching on and off a power transistor LT is shown. Here, the gate driver module 1 has a first output terminal A1 at which a capacitor C is arranged. dy and the on-resistance R G1 The series circuit is connected to the gate G of the power transistor LT. G2 The current source I0 is located at the second output terminal A2 in parallel with the series circuit. The gate drive module 1 also has a configuration unit 2, a logic unit 3, a fault unit 4 and an isolated voltage supply device 5, which supplies two switchable voltage sources V p 、V s The gate driver module 1 also includes a switching module 6 and an amplifier 7. The switching module includes four switches S1-S4. The configuration unit 2 receives a configuration signal SPI from a higher-level control unit (not shown). From this configuration signal, the higher-level circuit configuration and the position of the gate driver module 1 in the higher-level circuit configuration are derived.

[0018] Alternatively or additionally, this information is encoded via a discrete connection that can be detected at the input D. The logic unit 3 receives a PWM signal from a higher-level control unit (not shown), which is implemented by the logic unit 3 by actuating the switching elements S1-S4. The logic unit 3 can also access the data of the configuration unit 2 and store the PWM signal. The fault unit 4 detects the temperature T of the power transistor LT according to the temperature T jct And the output current I of the power transistor LT out To generate a fault signal, the fault signal is waiting to be processed at the output terminal Fault_out. The temperature T of the power transistor jct For example, it is determined using a temperature sensor 8 and supplied to the fault unit 4 via an amplifier 7. The fault unit 4 also receives a fault message Fault_in from an adjacent gate driver module and / or a higher-level control unit. The fault unit 4 is connected to the logic unit 3 via a connection not shown. If the power transistor LT is now to be switched on very quickly, switch S3 is closed (S1, S2, and S4 remain open). After switching on, S3 is opened and S1 is closed. To switch off, S4 is closed and the other switches S1 to S3 are opened.

[0019] Subsequently, S4 can be opened and S2 closed. This means that only one of the switches S1-S4 is always closed, with switches S1 and S3 being used for switching on and switches S2 and S4 for switching off. It should be noted that the order can also be reversed, i.e., for example, S3 can be closed first and then S1, or S2 can be closed first and then S4.

[0020] In the event of a fault, the logic unit 3 now receives a fault message. The logic unit 3 is aware of the higher-level circuit configuration and can then, using the stored PWM signal, in a next step switch off its assigned power transistor LT in coordination with the other gate driver modules of this circuit configuration, without this having any detrimental adverse effects on the other power transistors.

[0021] exist Figure 2 shows a three-level half-bridge circuit 10 having four power transistors LT, with a center tap M and a neutral point N. Each of these power transistors LT is controlled by a gate driver module 1. These gate driver modules 1 receive their PWM signals PWM1-PWM4 and their configuration signals SPI from a higher-level control unit (not shown). The fault input Fault_in and the fault output Fault_out are connected to one another in a daisy-chain fashion, so that each gate driver module is informed of a fault occurring within the circuit configuration and can then disconnect the power transistors LT in a coordinated manner. It should be noted that a daisy-chain configuration with more than four elements is also possible.

[0022] exist Figure 3 An alternative embodiment is shown in , in which a higher-level control unit 20 is incorporated into a daisy chain.

[0023] Reference Signs List

[0024] 1 Gate drive module

[0025] 2 Configuration Unit

[0026] 3 Logical Units

[0027] 4 Faulty Units

[0028] 5 Voltage supply device

[0029] 6 Switching Module

[0030] 7 Amplifier

[0031] 8 Temperature sensor

[0032] 10 3-level half-bridge circuit

[0033] 20 Control Unit

[0034] LT Power Transistors

[0035] G Gate

[0036] S1-S4 switches

Claims

1. A gate drive module (1) for switching a power transistor (LT) on and off, the gate drive module comprising at least two switchable voltage sources (V p 、V s ) and at least two output terminals (A1, A2), wherein the switch-on and switch-off resistors (R G1 、R G2 ) can be connected to one of the at least two output terminals (A1, A2), wherein a configuration unit (2) is provided, in which a higher-level circuit configuration of the gate drive module (1) relative to other gate drive modules is stored or recorded, wherein the gate drive module (1) further comprises a logic unit (3), which is configured to: receive a PWM signal from a higher-level control unit (20) and control the switchable voltage source (V p 、V s ) is switched, wherein the logic unit (3) is further configured to store the PWM signal for at least one clock cycle, wherein the gate driver module (1) has at least one fault unit (4), and the fault unit is configured to forward at least one internal fault of the gate driver module (1) to at least one adjacent gate driver module and / or the higher-level control unit (20) and receive a fault message from at least one adjacent gate driver module and / or the higher-level control unit (20), wherein the logic unit (3) is further configured to generate a PWM signal based on the fault message of the fault unit (4), the stored or recorded circuit configuration, and the stored PWM signal, so as to cut off the connected power transistor (LT), so that when the PWM signal of the higher-level control unit (20) is lost or does not exist, the cut-off procedure required for safe cut-off is followed.

2. The gate driving module according to claim 1, wherein: The gate drive module (1) is configured to receive at least the temperature (T jct ) and / or the output current (I out ).

3. The gate driving module according to claim 2, wherein: The gate drive module (1) is configured to receive at least one other parameter of the power transistor (LT).

4. The gate drive module according to any one of claims 1 to 3, characterized in that: The gate drive module (1) has at least one third switchable output terminal (A3), at least one current source (I0) capable of switching on and off the resistor (R G1 、R G2 ) is connected in parallel to the third switchable output terminal.

5. A circuit configuration comprising a plurality of gate drive modules according to any one of claims 1 to 4, characterized in that: The fault units (4) of the gate drive module (1) are connected to one another in the form of a daisy chain, wherein corresponding power transistors are driven in a guided manner in multiple cycles.

6. The circuit arrangement according to claim 5, characterized in that The higher-level control unit (20) is incorporated into the daisy chain.

7. The circuit arrangement according to claim 5 or 6, characterized in that The circuit configuration is constructed as a 3-level half-bridge circuit (10).

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