A circuit for entering 100% duty cycle and its control method

Abstract

The present invention belongs to the technical field of analog integrated circuits, and more specifically, relates to a circuit for entering a 100% duty cycle and a control method thereof. The present invention mainly utilizes an internal detection adaptive on timer to generate a signal to compare with an internal FB detection circuit. If the timer has reversed at this time, but the output signal of the fb detection circuit is still at a high level, it is determined that the 100% duty cycle has been entered at this time, and a high duty signal HD is generated. The signal is used to adjust the ea comparator threshold and smoothly extend the high level maintenance length of the fb_low signal. This method can make the system smoothly enter the 100% state, and at the same time, the circuit is in an overall loop and will not destroy the stability of the system.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and particularly relates to a circuit for entering a 100% duty cycle and a control method thereof. Background Art

[0002] In a traditional DCDC structure, especially for a BUCK, after the output voltage and the input voltage are processed by internal logic, there is a duty cycle relationship between the two. Generally, we use D to represent the duty cycle. The duty cycle D is a value between 0 and 1. The higher its value, for the BUCK system, the higher the output voltage and the closer it is to the input voltage. However, due to the presence of parasitic inductance and capacitance in the circuit, when the input and output are close, it is easily affected by parasitic devices, and the system is extremely unstable at this time and it is difficult to maintain the output voltage with extremely small ripple. Therefore, in order to avoid instability in the current traditional circuits, a threshold related to the duty cycle is set in the circuit. Generally, this threshold is called the maximum duty cycle, that is, the maximum duty cycle that the system can support. The output voltage will be clamped at the voltage corresponding to this duty cycle. For a BUCK, in essence, the voltage cannot be directly converted from input to output. Some circuits may also add an LDO (low dropout linear regulator) inside the circuit to meet the requirement that the output voltage of the system is equal to the input voltage. However, this will increase the complexity of the system and also increase the chip area, resulting in additional area waste.

[0003] Currently, a lot of work has been done on how to make the circuit avoid the limitation of the maximum duty cycle so that the output voltage of the circuit can be equal to the input voltage. Generally, the method adopted is to set a logic circuit inside. When the output voltage requirement set externally by the system is higher than the voltage corresponding to the maximum duty cycle, at this time, through internal logic judgment, it is considered that the actual duty cycle of the circuit is higher than the set maximum duty cycle, and then a corresponding logic signal is output. This signal is high, indicating that the system should enter the 100% duty cycle situation at this time. Then the system uses this high-level logic signal to control the upper transistor to always conduct and the lower transistor to turn off, that is, infinitely lengthen the conduction time of the upper transistor, so that the system can be in a state of 100% duty cycle. When it is detected that the output voltage decreases, a low level is output through internal logic judgment, considering that the system needs to exit the 100% duty cycle state at this time, and the upper and lower transistors switch normally. However, there are certain problems with this method, that is, how to effectively set the voltage corresponding to the maximum duty cycle. Because when the chip is manufactured, it is easily affected by PVT, causing the internally set threshold point to drift. Since the internal system of a single flag signal cannot adaptively adjust, the system cannot enter the 100% duty cycle at the optimal threshold point, resulting in problems such as reduced efficiency and uncontrolled output voltage ripple.

[0004] The traditional method uses the internal circuit to detect the difference between the turn-on time of the upper transistor and the internally set time. If the difference is greater than the set value, it is considered that the 100% state needs to be entered at this time, and a corresponding flag signal is generated to control the upper transistor. Careful consideration needs to be given to this flag signal and the internal timing. Controlling the upper transistor directly with the flag is equivalent to controlling by cutting the loop, which is likely to cause stability problems. Summary of the Invention

[0005] Based on the problems of complex circuit for the traditional circuit to enter the 100% duty cycle, non-self-adaptive entry threshold point, and slow speed, etc., the present invention proposes a circuit for entering the 100% duty cycle and its control method.

[0006] The technical solution of the present invention is as follows:

[0007] A circuit for entering the 100% duty cycle includes an error amplifier, a bias voltage source, a resistor, a hysteresis comparator, a comparator hysteresis amount control unit, a drive control unit, a D flip-flop, and a timer; wherein, the non-inverting input terminal of the error amplifier is connected to the feedback voltage, its inverting input terminal is connected to the reference voltage, and its output terminal is connected to the inverting input terminal of the hysteresis comparator and also connected to the non-inverting input terminal of the hysteresis comparator through a resistor; the positive terminal of the bias voltage source is connected to the connection point between the resistor and the non-inverting input terminal of the hysteresis comparator, and the negative terminal of the bias voltage source is grounded; the output terminal of the hysteresis comparator is connected to the D input terminal of the D flip-flop and the input terminal of the drive control unit; the clock signal input terminal of the D flip-flop is connected to the output terminal of the timer, and the two input terminals of the timer are respectively connected to the input voltage and the output voltage of the chip; the Q output terminal of the D flip-flop is connected to the input terminal of the comparator hysteresis amount control unit, and the output terminal of the comparator hysteresis amount control unit is connected to the control terminal of the hysteresis comparator; the comparator hysteresis amount control unit is used to adjust the hysteresis amount of the hysteresis comparator when detecting the output signal of the D flip-flop, thereby controlling the duty cycle, and the drive control unit is used to generate and output a logic control signal.

[0008] Further, the feedback voltage is the voltage after the output voltage is divided by an external resistor network.

[0009] Further, the reference voltage is an internal reference voltage generated by an internal reference circuit.

[0010] Further, the resistor is an internal bias resistor, and the voltage drop generated by the current generated by the error amplifier on the resistor is used for subsequent hysteresis comparison at the input terminal of the hysteresis comparator.

[0011] Further, when the output signal of the hysteresis comparator is high, it indicates that the external output voltage is lower than the set point. When the output signal of the timer flips and the output signal of the hysteresis comparator is high, the comparator hysteresis amount control unit controls the hysteresis comparator to make the circuit enter the 100% duty cycle.

[0012] A control method for a circuit to enter 100% duty cycle. The timer is used to detect the input voltage and the output voltage. The longer the duty cycle it generates, the timer provides a subsequent high-level logic flag bit, indicating that the input voltage and the output voltage of the chip are close at this time, and it starts to approach the situation of 100% duty cycle. At this time, a D flip-flop is used to detect the FBLOW and the high-level logic signal output by the timer. If FBLOW becomes high before the timer output at this time, it is considered that the circuit does not need to enter 100% duty cycle because the output voltage is still relatively low at this time. When the timer output becomes high and then FBLOW becomes high, it is considered that the circuit needs to enter the situation of 100% duty cycle at this time. The D flip-flop correspondingly generates a corresponding percentage duty cycle signal HD, and this signal acts on the subsequent hysteresis control circuit HYS_CONTROL unit.

[0013] Further, it is defined that the circuit for entering 100% duty cycle is used for a voltage converter. The logic control signal output by the drive control unit is used to control the power upper transistor and the power lower transistor of the voltage converter. It is characterized in that the transconductance of the error amplifier is gm, the current of this error amplifier is gm*(FB - VREF), FB is the feedback voltage, VREF is the reference voltage, the voltage drop across the resistor is gm*(FB - VREF)*RBIAS, and RBIAS is the resistance value. When the circuit is not in the 100% duty cycle state and FB is lower than VREF, when the power upper transistor is turned on, the FB voltage rises, and the negative terminal of the hysteresis comparator also rises. When it is higher than the bias voltage vbias, the output of the hysteresis comparator becomes low level, and at the same time the power upper transistor is turned off and the power lower transistor is turned on, causing FB to drop. At this time, the hysteresis amount inside the hysteresis comparator is defined as hys1; when the comparator hysteresis amount control unit is activated, the hysteresis amount hys2 is added to the hysteresis comparator, making the hysteresis amount become hys1 + hys2. Therefore, when the power lower transistor is turned on, the condition for the hysteresis comparator to flip again becomes vbias - hys1 - hys2. Thus, after the power lower transistor is turned off, compared with the circuit state not in 100% duty cycle, FB needs to increase to hys2 + hys1 before it can flip again, so that the conduction time of the power upper transistor increases, making the circuit in the 100% duty cycle circuit state.

[0014] The beneficial effects of the present invention are as follows: By using the signal generated by the internal detection adaptive on timer to compare with the internal FB detection circuit, if the on timer has reversed at this time, but the output signal fb_low of the fb detection circuit is still at a high level, it is determined that the 100% duty cycle is entered at this time, and a high duty signal HD is generated. Using this signal to adjust the threshold of the ea comparator, the high-level maintenance length of the fb_low signal is smoothed and elongated. Using this method, the system can smoothly enter the 100% state. At the same time, this circuit is in the overall loop and will not damage the system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the logic structure of the circuit of the present invention;

[0016] Figure 2 It is a schematic diagram of the simple structure of BUCK.

[0017] Description of the reference numerals in the drawings:

[0018] ea is an error amplifier;

[0019] The sum unit is an internal hysteresis comparator;

[0020] The on_timer unit is a unit that calculates and generates the maximum duty cycle according to the input and output voltages of the chip;

[0021] The hys_control unit is a unit that controls the hysteresis amount of the sun comparator;

[0022] The driver_control unit is a subsequent drive logic generation circuit;

[0023] FB is the voltage after the output voltage is divided by an external resistor network;

[0024] VREF is an internal reference voltage generated by an internal reference circuit;

[0025] VBIAS is a fixed bias voltage provided for the internal circuit, generated by an internal reference circuit;

[0026] RBIAS is an internal bias resistor, and the current generated by ea generates a voltage drop on this resistor for subsequent hysteresis comparison at the input end of the SUM hysteresis comparator. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The present invention will be described in detail below with reference to the accompanying drawings.

[0028] The core idea of the present invention is to utilize the speed difference between various analog quantities and logic signals in the circuit, that is, there is a sequence, and the logic signal processes information faster, and using a latch can enable the circuit to operate safely with high quality.

[0029] As Figure 1 shown, the circuit proposed by the present invention mainly consists of the following parts: ea amplifier, sum amplifier, on-timer, D flip-flop, hys control logic, driver control logic

[0030] The mechanism for smoothly entering the high duty is that the on timer is used to generate the upper transistor turn-on signal. When the input voltage is close to the output voltage, the signal generated by the on timer becomes longer and longer. When its signal flips, the FB_LOW signal is detected. If the signal of FB_LOW is still high at this time, it means that it is necessary to enter the high duty mode at this time, and HD turns to high level, activating the state control circuit of the internal circuit.

[0031] The upper transistor mentioned in the text is Figure 2 the transistor above the sw point in the power stage, and the corresponding lower transistor is defined as the lower transistor. Figure 2 It is a simple schematic diagram of a BUCK.

[0032] Specific circuit analysis: Appropriately adjust the transconductance of ea so that its current is gm*(FB - VREF). Then the voltage drop across the resistor RBIAS is gm*(FB - VREF)*RBIAS. Considering the overall operating structure, the voltage at this point changes in a sawtooth wave shape with the change of the FB voltage. When the circuit is not in the high duty state and fb is lower than VREF, when the upper transistor is conducting, as the FB voltage changes upward, the negative terminal of sum also changes upward accordingly. After it is higher than vbias, fb_low becomes low level, and at the same time the upper transistor turns off and the lower transistor conducts, causing fb to change downward. To prevent oscillation at the VBIAS point, fb needs to be lower than vbias - hys1, where HYS1 is the built-in anti-oscillation hysteresis amount. Only when fb is lower than this value can it flip. When the circuit detects the high duty signal, through the hysteresis control circuit, HYS2 is added to the hysteresis amount of sum. Then, when the lower transistor conducts, the condition for sum to flip again becomes vbias - hys1 - hys2. After the lower transistor turns off, compared with the state when not in high duty, fb needs to increase to hys2 + hys1 before it can flip again. Then, compared with the previous non-high duty state, the conduction time of the upper transistor increases, making the circuit in the 100% duty cycle state. By increasing the duty cycle through the hysteresis amount, the circuit smoothly enters the 100% duty cycle state, relying on the loop change and conforming to the overall circuit change law, without causing instability in the circuit. The hysteresis control unit mainly provides the hysteresis amount of hys2 for the sun hysteresis comparator. This hysteresis amount is directly added inside the comparator, so no additional oscillation problem will occur.

Claims

1. A circuit for entering a 100% duty cycle, characterized in that, It includes an error amplifier, a bias voltage source, a resistor, a hysteresis comparator, a comparator hysteresis control unit, a drive control unit, a D flip-flop, and a timer; wherein, the non-inverting input terminal of the error amplifier is connected to the feedback voltage, the inverting input terminal is connected to the reference voltage, and the output terminal is connected to the inverting input terminal of the hysteresis comparator and also connected to the non-inverting input terminal of the hysteresis comparator through the resistor after passing through the resistor; the positive terminal of the bias voltage source is connected to the connection point between the resistor and the non-inverting input terminal of the hysteresis comparator, and the negative terminal of the bias voltage source is grounded; the output terminal of the hysteresis comparator is connected to the D input terminal of the D flip-flop and the input terminal of the drive control unit; the clock signal input terminal of the D flip-flop is connected to the output terminal of the timer, and the two input terminals of the timer are respectively connected to the input voltage and the output voltage of the chip; the Q output terminal of the D flip-flop is connected to the input terminal of the comparator hysteresis control unit, and the output terminal of the comparator hysteresis control unit is connected to the control terminal of the hysteresis comparator; the comparator hysteresis control unit is used to adjust the hysteresis of the hysteresis comparator when detecting the output signal of the D flip-flop, thereby controlling the duty cycle, and the drive control unit is used to generate and output a logic control signal.

2. The circuit for entering a 100% duty cycle according to claim 1, characterized in that, The feedback voltage is the voltage obtained by dividing the output voltage by an external resistor network.

3. The circuit for entering a 100% duty cycle according to claim 1, wherein The reference voltage is an internal reference voltage generated by an internal reference circuit.

4. A circuit for entering a 100% duty cycle, as claimed in claim 1, wherein The resistor is an internal bias resistor, and the current generated by the error amplifier generates a voltage drop on the resistor for subsequent hysteresis comparison at the input terminal of the hysteresis comparator.

5. A circuit for entering a 100% duty cycle, as claimed in claim 1, wherein When the output signal of the hysteresis comparator is high, it indicates that the external output voltage is lower than the set point. When the output signal of the timer flips and the output signal of the hysteresis comparator is high, the comparator hysteresis control unit controls the hysteresis comparator to make the circuit enter a 100% duty cycle.

6. A control method for a circuit to enter a 100% duty cycle as described in any one of claims 1 to 5, characterized in that As the two input signals of the timer approach, the generated signal becomes longer. When the output signal of the timer flips, the timer outputs a high level to control the operation of the D flip-flop, enabling the D flip-flop to detect the output signal of the hysteresis comparator. When it is detected that the output signal of the hysteresis comparator is high at this time, the D flip-flop outputs a high level to activate the comparator hysteresis control unit. The comparator hysteresis control unit controls the duty cycle by adjusting the hysteresis of the hysteresis comparator, making the circuit enter a 100% duty cycle.

7. A control method for a circuit to enter 100% duty cycle, defining that the circuit for entering 100% duty cycle is used for a voltage converter, and the logic control signal output by the drive control unit is used to control the power upper transistor and the power lower transistor of the voltage converter, characterized in that, Let the transconductance of the error amplifier be gm. The current of this error amplifier is gm*(FB - VREF), where FB is the feedback voltage and VREF is the reference voltage. The voltage drop across the resistor is gm*(FB - VREF)*RBIAS, and RBIAS is the resistance value. When the circuit is not in the 100% duty cycle state and FB is lower than VREF, when the high-side power switch turns on, the FB voltage rises, and the negative terminal of the hysteresis comparator also rises. When it is higher than the bias voltage vbias, the output of the hysteresis comparator becomes low level. At the same time, the high-side power switch turns off and the low-side power switch turns on, causing FB to drop. At this time, the hysteresis amount inside the hysteresis comparator is defined as hys1; when the hysteresis amount control unit of the comparator is activated, the hysteresis amount hys2 is added to the hysteresis comparator, making the hysteresis amount become hys1 + hys2. Therefore, after the low-side power switch turns on, the condition for the hysteresis comparator to flip again becomes vbias - hys1 - hys2. Thus, after the low-side power switch turns off, compared with the circuit state not in the 100% duty cycle, FB needs to increase to hys2 + hys1 before it can flip again, thereby increasing the conduction time of the high-side power switch and making the circuit in the 100% duty cycle circuit state.

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