Adjustable five-stage encryption system, transmitter device and receiver device

Abstract

The present application relates to the field of encryption technology, and specifically provides an adjustable fifth-order encryption system, which includes a sending end device and a receiving end device. The sending end device includes a data generation module and a data encryption module. The data encryption module obtains at least one data packet from the data generation module, encrypts the data packet through a fifth-order encryptor via a selected encryption level, and then outputs an encrypted sequence. The receiving end device includes a data target module and a data decryption module. The data decryption module obtains the encrypted sequence from the sending end device, decrypts the encrypted sequence through a fifth-order decryptor via a selected decryption level, and then outputs the restored data packet to the data target module. The present application can switch the encryption level according to the required encryption level, and can implement different encryption level protections through a set of hardware.

Description

Technical Field

[0001] The present application relates to the field of encryption technology and provides an encryption system, and more particularly, refers to an adjustable five-stage encryption system capable of switching encryption levels and a transmitting end device and a receiving end device thereof. Background Art

[0002] Advanced Encryption Standard (AES), also known as Rijndael encryption in cryptography, is a block encryption standard adopted by the U.S. federal government. This standard is used to replace the original DES, has been analyzed by many parties and is widely used around the world. As of 2006, the only successful attacks against AES are side-channel attacks or social engineering attacks. The National Security Agency of the United States audited all the finalists participating in the AES competition and believed that they all met the security needs of the U.S. government for transmitting non-confidential files.

[0003] The Advanced Encryption Standard has been cracked many times. The 128-bit key version of AES has 10 encryption cycles, the 192-bit key version has 12 encryption cycles, and the 256-bit key version has 14 encryption cycles. As of 2006, the most famous attacks were against the 128-bit key version of AES with 7 encryption cycles, the 192-bit key version with 8 encryption cycles, and the 256-bit key version with 9 encryption cycles. As hardware becomes more efficient, it is estimated that the day when AES can be completely cracked by brute force attacks is not far away.

[0004] In addition, with the continuous upgrading of hardware equipment, artificial intelligence has now reached the stage of commercialization. Through the processing efficiency of hardware equipment and the powerful computing power of artificial intelligence, the encryption standards widely used today are likely to be cracked by artificial intelligence through a large number of calculations. For the above reasons, it is necessary to improve the existing encryption technology. Summary of the invention

[0005] The main purpose of the present application is to provide an adjustable five-stage encryption system including a transmitting device and a receiving device. The transmitting device includes a data generation module and a data encryption module. The data encryption module includes an encryption level setter and a five-stage encryptor. The encryption level setter is used to set the encryption level of the five-stage encryptor. The data encryption module obtains at least one data packet from the data generation module, encrypts the data packet via the encryption level selected by the five-stage encryptor, and then outputs an encrypted sequence. The receiving device includes a data target module and a data decryption module. The data decryption module includes a decryption level setter and a five-stage decryptor. The decryption level setter is used to set the decryption level of the five-stage decryptor according to the encryption level. The data decryption module obtains the encrypted sequence from the transmitting device, decrypts the encrypted sequence via the decryption level selected by the five-stage decryptor, and then outputs the restored data packet to the data target module.

[0006] Another object of the present application is to provide a transmitting end device, comprising a data generation module and a data encryption module. The data encryption module comprises an encryption level setter and a five-stage encryptor, the encryption level setter is used to set the encryption level of the five-stage encryptor, the data encryption module obtains at least one data packet from the data generation module, encrypts the data packet via the encryption level selected by the five-stage encryptor, and then outputs an encrypted sequence.

[0007] Another object of the present application is to provide a receiving end device, comprising a data target module and a data decryption module. The data decryption module comprises a decryption level setter and a five-stage decryptor. The decryption level setter is used to set the decryption level of the five-stage decryptor according to the encryption level. The data decryption module obtains the encryption sequence from the sending end device, decrypts the encryption sequence through the decryption level selected by the five-stage decryptor, and then outputs the restored data packet to the data target module.

[0008] It can be seen that compared with the prior art, the present application can switch the encryption level according to the required encryption degree, and can implement different encryption level protections through a set of hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 Module schematic diagram of the adjustable fifth-order encryption system provided in an embodiment of the present application (I).

[0011] Figure 2 Module schematic diagram of the adjustable fifth-order encryption system provided in an embodiment of the present application (II).

[0012] Figure 3 A schematic diagram of a module of a fifth-order encryptor provided in an embodiment of the present application.

[0013] Figure 4 A schematic diagram of the logical operations of a fifth-order encryptor provided in an embodiment of the present application.

[0014] Figure 5 A schematic diagram of a module of a fifth-order decryptor provided in an embodiment of the present application.

[0015] Figure 6 A schematic diagram of the logical operation of a fifth-order decryptor provided in an embodiment of the present application.

[0016] Figure 7 A schematic diagram of the process flow of the adjustable fifth-order encryption method provided in an embodiment of the present application.

[0017] Figure 8 A schematic diagram of the encryption process of a fifth-order encryptor provided in an embodiment of the present application.

[0018] Fig. 9 A schematic diagram of the decryption process of the fifth-order decryptor provided in an embodiment of the present application.

[0019] 100: adjustable five-level encryption system; 10: transmitting end device; 12: data generation module; 14: data encryption module; 142: encryption level setter; 144: five-level encryptor; 1441: first eight-bit stream encryptor; 1441L: encryption linear feedback shift register; 1441G: encryption logic gate; 1442: second eight-bit stream encryptor; 1442L: encryption linear feedback shift register; 1442G: encryption logic gate; 1443: sixteen-bit stream encryptor; 144 3L: Encrypted linear feedback shift register; 1443G: Encrypted logic gate; 1444: 32-bit stream encryptor; 1444L: Encrypted linear feedback shift register; 1444G: Encrypted logic gate; 1445: 64-bit stream encryptor; 1445L: Encrypted linear feedback shift register; 1445G: Encrypted logic gate; 20: Receiving device; 22: Data target module; 24: Data decryption module; 242: Decryption level setter; 244: Five-level decryptor; 2441: First eight-bit stream decryptor; 2441L: decryption linear feedback shift register; 2441G: decryption logic gate; 2442: second eight-bit stream decryptor; 2442L: decryption linear feedback shift register; 2442G: decryption logic gate; 2443: sixteen-bit stream decryptor; 2443L: decryption linear feedback shift register; 2443G: decryption logic gate; 2444: thirty-two-bit stream decryptor; 2444L: decryption linear feedback shift register; 2444G: decryption logic gate ; 2445: sixty-four-bit stream decryptor; 2445L: decryption linear feedback shift register; 2445G: decryption logic gate; DA: data transmission layer; ES1: first encryption sequence; ES2: second encryption sequence; ES3: third encryption sequence; ES4: fourth encryption sequence; ES5: fifth encryption sequence; PK: data packet; PK1: first data packet; PK2: second data packet; PK3: third data packet; PK4: fourth data packet; PK5: fifth data packet. DETAILED DESCRIPTION

[0020] The detailed description and technical content of this application are described below with reference to the accompanying drawings. Figure 1 , is a module diagram (I) of the adjustable five-stage encryption system of this application, as shown in the figure:

[0021] This embodiment mainly provides an adjustable five-stage encryption system 100, which is used to encrypt and decrypt the data transmitted by each device when multiple devices transmit data to each other. Each device that generates or receives data can be a computer, a server, a mobile device, an Internet of Things device (for example, a monitor, a television, a cloud hard drive, a lamp, etc.), a large number of manufacturing equipment or machines, etc., which are not limited in this application. In this application, each device is defined as a sending end device 10 as a data transmission source and a receiving end device 20 corresponding to the sending end device 10 for receiving data from the sending end device 10 based on the signal transmission and reception relationship. It should be noted that this application is not limited to the sending end device 10 only performing the data encryption function and the receiving end device 20 only performing the data decryption function. Specifically, the sending end device 10 and the receiving end device 20 can generally have encryption and decryption functions at the same time to ensure that the data is encrypted or decrypted with each other's keys during the two-way transmission process. This must be explained in advance.

[0022] Data can be transmitted between the transmitting device 10 and the receiving device 20 via a wired or wireless network. In one preferred embodiment, data can be transmitted between the transmitting device 10 and the receiving device 20 via the Internet, a local area network, or between any wired or wireless communication ports, which is not limited in this application. In order to complete the functions of data encryption, decryption and transmission, the transmitting device 10 and the receiving device 20 should at least include a processor, a storage unit, and a communication unit to cooperate with each other to complete the corresponding functions, such as a physical line network card, a wireless network card, a Bluetooth module, a Zigbee module, etc. The transmission method and transmission interface of the above-mentioned signals are not within the scope of the application.

[0023] In one embodiment, the combination of modules, devices, or units described in the adjustable five-stage encryption system 100 of the present application and the corresponding functions can be executed by a single chip or a combination of multiple chips, and the number of the above chip configurations is not within the scope of the present application. In addition, the chip can be, but is not limited to, a processor, a central processing unit (CPU), a microprocessor (Microprocessor), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), and other similar devices or combinations of these devices that can process, convert or special-purpose information or signals, which are not limited in the present application.

[0024] In one embodiment, the transmitting device 10 mainly includes a data generation module 12 and a data encryption module 14. The data generation module 12 can be, for example, a cache memory, a dynamic random access memory (DRAM), or a persistent memory for storing and managing data to be transmitted and encrypted. The data encryption module 14 obtains at least one data packet from the data generation module 12. The data encryption module 14 can be a processor or a microprocessor for performing encryption calculation processing, which is not limited in the present application. Finally, the data encryption module 14 outputs the encrypted data packet to the receiving device 20. The encrypted data packet output by the data encryption module 14 is defined as an encryption sequence.

[0025] In one embodiment, the data encryption module 14 includes an encryption level setter 142 and a five-stage encryptor 144 whose input end is connected to the encryption level setter 142. Figure 2 as well as Figure 3, is a block diagram of the adjustable fifth-order encryption system of the present application (II), a block diagram of the fifth-order encryptor, as shown in the figure: the encryption level setter 142 is used to set the encryption level of the fifth-order encryptor 144 according to the user setting / automatic configuration. The input end of the fifth-order encryptor 144 is connected to the output end of the data generation module 12 to obtain at least one data packet PK. The fifth-order encryptor 144 includes a first eight-bit stream encryptor 1441, a second eight-bit stream encryptor 1442, a sixteen-bit stream encryptor 1443, a thirty-two-bit stream encryptor 1444, and a sixty-four-bit stream encryptor 1445 connected in sequence (herein, the first eight-bit stream encryptor 1441, the second eight-bit stream encryptor 1442, the sixteen-bit stream encryptor 1443, the thirty-two-bit stream encryptor 1444, and the sixty-four-bit stream encryptor 1445 are collectively referred to as stream encryptors).

[0026] Specifically, an input end of the first eight-bit stream encryptor 1441 is connected to an output end of the encryption level setter 142, and another input end is connected to the data generation module 12 for receiving data packets PK; an input end of the second eight-bit stream encryptor 1442 is connected to the output end of the encryption level setter 142, and another input end is connected to the output end of the first eight-bit stream encryptor 1441; an input end of the sixteen-bit stream encryptor 1443 is connected to the output end of the encryption level setter 142, and another input end is connected to the output end of the second eight-bit stream encryptor 1442; an input end of the thirty-two-bit stream encryptor 1444 is connected to the output end of the encryption level setter 142, and another input end is connected to the output end of the sixteen-bit stream encryptor 1443; an input end of the sixty-four-bit stream encryptor 1445 is connected to the output end of the encryption level setter 142, and another input end is connected to the output end of the thirty-two-bit stream encryptor 1444. In this embodiment, the encryption level setter 142 selects which of the first 8-bit stream encryptor 1441, the second 8-bit stream encryptor 1442, the 16-bit stream encryptor 1443, the 32-bit stream encryptor 1444, and the 64-bit stream encryptor 1445 to activate and which one to output the encrypted data packet PK according to the encryption level (a total of five encryption levels), and when the stream encryptor at the rear of the sequence is activated, the stream encryptor in front of the stream encryptor must also be activated. For example: when the encryption level setter 142 sets the second-order encryption level, the encryption level setter 142 will activate the second eight-bit stream encryptor 1442 and the eight-bit stream encryptor 1441 at the same time, so that the data packet PK is encrypted in sequence by the first eight-bit stream encryptor 1441 and the second eight-bit stream encryptor 1442, and the encrypted data packet PK is output by the second eight-bit stream encryptor 1442, thereby performing encryption at the second-order encryption level (equivalent to a sixteen-bit encryption device); the remaining unused sixteen-bit stream encryptor 1443, thirty-two-bit stream encryptor 1444 and sixty-four-bit stream encryptor 1445 are not activated. When the first-level encryption level only activates the first eight-bit stream encryptor 1441, the encryption system will be able to constitute an eight-bit encryption device; when the second-level encryption level only activates the first eight-bit stream encryptor 1441 and the second eight-bit stream encryptor 1442, the encryption system will be able to constitute a sixteen-bit encryption device; when the third-level encryption level only activates the first eight-bit stream encryptor 1441, the second eight-bit stream encryptor 1442 and the sixteen-bit stream encryptor 1443, the encryption system will be able to constitute a thirty-two-bit encryption device; when the fourth-level encryption level only activates the first eight-bit stream encryptor 1441, the second eight-bit stream encryptor 1442, the sixteen-bit stream encryptor 1443 and the thirty-two-bit stream encryptor 1444, the encryption system will be able to constitute a sixty-four-bit encryption device; when the fifth-level encryption level activates all the stream encryptors, the encryption system will be able to constitute a one hundred and twenty-eight-bit encryption device.

[0027] When only the first eight-bit stream encryptor 1441 is activated, the output of the first eight-bit stream encryptor 1441 is the first encryption sequence ES1; when only the first eight-bit stream encryptor 1441 and the second eight-bit stream encryptor 1442 are activated, the output of the second eight-bit stream encryptor 1442 is the second encryption sequence ES2; when only the first eight-bit stream encryptor 1441, the second eight-bit stream encryptor 1442 and the sixteen-bit stream encryptor 1443 are activated, the output of the sixteen-bit stream encryptor 1443 is the third encryption sequence ES3; when only the first eight-bit stream encryptor 1441, the second eight-bit stream encryptor 1442, the sixteen-bit stream encryptor 1443 and the thirty-two-bit stream encryptor 1444 are activated, the output of the thirty-two-bit stream encryptor 1444 is the fourth encryption sequence ES4; when all the stream encryptors are activated, the output of the sixty-four-bit stream encryptor 1445 is the fifth encryption sequence ES5. Finally, the encryption level selected by the encryption level setter 142 controls the five-stage encryptor 144 to output the first encryption sequence ES1, the second encryption sequence ES2, the third encryption sequence ES3, the fourth encryption sequence ES4 or the fifth encryption sequence ES5 of the corresponding encryption level to the receiving end device 20 via the data transmission layer DA. Specifically, at any encryption level, only one of the aforementioned encryption sequences corresponding to the encryption level is generated.

[0028] In one embodiment, the first 8-bit stream encryptor 1441, the second 8-bit stream encryptor 1442, the 16-bit stream encryptor 1443, the 32-bit stream encryptor 1444 and the 64-bit stream encryptor 1445 of the five-stage encryptor 144 respectively include an encrypted linear feedback shift register (LFSR) and one or more encrypted logic gates. The encrypted linear feedback shift register has an encryption key. The encryption key can be input into the encrypted linear feedback shift register by other devices as a preset key. The devices are not limited to the content of this application and are explained in advance. The encryption linear feedback shift register performs a logic operation on multiple encryption bit taps of the encryption key to obtain an encryption operand. The encryption operand and the data packet PK are operated via the encryption logic gate to obtain an encryption sequence, and the encryption operand is fed back to the first bit of the encryption linear feedback shift register as an update of the encryption key. The update means that the encryption operand will be input into the first bit of the encryption key of the encryption linear feedback shift register, so that the original first bit of the encryption key is moved to the second bit, the original second bit of the encryption key is moved to the third bit, and so on. The original last bit of the encryption key will be covered by the previous bit, thereby achieving the update of the encryption key.

[0029] In one embodiment, see Figure 4 , is a logical operation diagram of the five-stage encryptor of the present application, as shown in the figure: the first eight-bit stream encryptor 1441 includes an encrypted linear feedback shift register 1441L (storing the first encryption key a[1] to a[8], a[n] is the nth bit of the first encryption key) and an encryption logic gate 1441G; the second eight-bit stream encryptor 1442 includes an encrypted linear feedback shift register 1442L (storing the second encryption key b[1] to b[8], b[n] is the nth bit of the second encryption key) and an encryption logic gate 1442G; the sixteen-bit stream encryptor 1443 includes an encrypted linear feedback shift register 1443 L (stores the third encryption key c[1] to c

[16] , c[n] is the nth bit of the third encryption key) and an encryption logic gate 1443G; the thirty-two-bit stream encryptor 1444 includes an encryption linear feedback shift register 1444L (stores the fourth encryption key d[1] to d

[32] , d[n] is the nth bit of the fourth encryption key) and an encryption logic gate 1444G; the sixty-four-bit stream encryptor 1445 includes an encryption linear feedback shift register 1445L (stores the fifth encryption key e[1] to e

[64] , e[n] is the nth bit of the fifth encryption key) and an encryption logic gate 1445G.

[0030] In one embodiment, the encryption logic gates 1441G, 1442G, 1443G, 1444G, 1445G and logic operations all use exclusive OR gates (XOR) as operations. In other embodiments, the logic gates 1441G, 1442G, 1443G, 1444G, 1445G and logic operations can be implemented using AND gates, OR gates, other logic gates or a combination of multiple logic gates, which are not limited in this application.

[0031] In other embodiments, the aforementioned fifth-order encryptor 144 may also be provided with a multiplexer (MUX) at the back end to determine the output encryption sequence, or a control module (Control Module) may be provided at the front end of the fifth-order encryptor 144 to replace the encryption level setter 142 to determine the partial functions of the activated stream encryptor and logic gate. The changes in the above-mentioned implementation modes are not within the scope of the present application.

[0032] In one embodiment, please refer to Figure 1The receiving device 20 includes a data target module 22 and a data decryption module 24. The data target module 22 can also be a cache memory, a dynamic random access memory (DRAM), or a persistent memory to store and manage the received data. The data decryption module 22 can be a processor or a microprocessor for performing decryption calculations, which is not limited in this application. Finally, the data decryption module 24 is used to decrypt the received encrypted sequence through the corresponding encryption level and then output the restored original data packet to the data target module 22 for storage.

[0033] In one embodiment, the data decryption module 24 includes a decryption level setter 242 and a fifth-order decryptor 244 whose input end is connected to the decryption level setter 242. Figure 2 as well as Figure 5, is a block diagram of the adjustable five-level encryption system of the present application (II), a block diagram of the five-level decryptor, as shown in the figure: the decryption level setter 242 is used to set the decryption level of the five-level decryptor 244, and the number of the decryption levels corresponds to the number of the encryption levels. The five-level decryptor 244 obtains at least an encryption sequence from the transmitting end device 10 via the data transmission layer DA, and the five-level decryptor 244 includes a first eight-bit stream decryptor 2441, a second eight-bit stream decryptor 2442, a sixteen-bit stream decryptor 2443, a thirty-two-bit stream decryptor 2444, and a sixty-four-bit stream decryptor 2445 connected in sequence (herein, the first eight-bit stream decryptor 2441, the second eight-bit stream decryptor 2442, the sixteen-bit stream decryptor 2443, the thirty-two-bit stream decryptor 2444, and the sixty-four-bit stream decryptor 2445 are collectively referred to as stream decryptors). Specifically, the input end of the sixty-four-bit stream decryptor 2445 is connected to the output end of the decryption level setting device 242, and the output end of the sixty-four-bit stream decryptor 2445 is connected to the input end of the thirty-two-bit stream decryptor 2444; another input end of the thirty-two-bit stream decryptor 2444 is connected to the output end of the decryption level setting device 242, and the output end of the thirty-two-bit stream decryptor 2444 is connected to the input end of the sixteen-bit stream decryptor 2443; another input end of the sixteen-bit stream decryptor 2443 is connected to the input end of the decryption level setting device 242. The output end, the output end of the sixteen-bit stream decryptor 2443 is connected to the input end of the second eight-bit stream decryptor 2442; the other input end of the second eight-bit stream decryptor 2442 is connected to the output end of the decryption level setter 242, and the output end of the second eight-bit stream decryptor 2442 is connected to the input end of the first eight-bit stream decryptor 2441; the other input end of the first eight-bit stream decryptor 2441 is connected to the output end of the decryption level setter 242, and the output end of the first eight-bit stream decryptor 2441 is connected to the input end of the data target module 22.

[0034] In this embodiment, the decryption level setter 242 selects the stream decryptor to be activated according to the decryption level and selects the stream decryptor to which the encryption sequence is to be input according to the decryption level, thereby decrypting the encryption sequence in sequence, and when the stream decryptor at the front of the sequence is activated, the stream decryptor behind the stream decryptor must also be activated. For example, when the decryption level setting device 242 sets the second-order decryption level corresponding to the second-order encryption level, the decryption level setting device 242 will activate the second 8-bit stream decryptor 2442 and the first 8-bit stream decryptor 2441 at the same time. The decryption level setting device 242 will input the encrypted sequence into the second 8-bit stream decryptor 2442 according to the second-order decryption level. The encrypted sequence is decrypted by the second 8-bit stream decryptor 2442 and the first 8-bit stream decryptor 2441. The first 8-bit stream decryptor 2441 outputs the decrypted encrypted sequence, thereby performing the decryption of the second-order decryption level (equivalent to a 16-bit decryption device); the remaining unused 16-bit stream decryptor 2443, 32-bit stream decryptor 2444 and 64-bit stream decryptor 2445 are not activated. The decrypted encrypted sequence output by the fifth-order decryptor 244 is defined as the restored data packet. When the first-order decryption level (corresponding to the first-order encryption level) activates only the first eight-bit stream decryptor 1441, the decryption system can constitute an eight-bit decryption device; when the second-order decryption level (corresponding to the second-order encryption level) activates only the first eight-bit stream decryptor 2441 and the second eight-bit stream decryptor 2442, the decryption system can constitute a sixteen-bit decryption device; when the third-order decryption level (corresponding to the third-order encryption level) activates the first eight-bit stream decryptor 2441, the second eight-bit stream decryptor 2442 and the sixteen-bit stream decryptor When the first eight-bit stream decryptor 2441, the second eight-bit stream decryptor 2442, the sixteen-bit stream decryptor 2443 and the thirty-two-bit stream decryptor 2444 are activated at the fourth decryption level (corresponding to the fourth encryption level), the decryption system can constitute a thirty-two-bit decryption device; when the fifth decryption level (corresponding to the fifth encryption level) activates all the stream decryptors, the decryption system can constitute a one hundred and twenty-eight-bit decryption device. Specifically, at any decryption level, only one encryption sequence corresponding to the decryption level will be received.

[0035] The output of the first 8-bit stream decryptor 2441 is defined as the first data packet PK1; the output of the second 8-bit stream decryptor 2442 is defined as the second data packet PK2; the output of the 16-bit stream decryptor 2443 is defined as the third data packet PK3; the output of the 32-bit stream decryptor 2444 is defined as the fourth data packet PK4; and the output of the 64-bit stream decryptor 2445 is defined as the fifth data packet PK5. Specifically, the restored data packet output by the fifth-order decryptor 244 is the first data packet PK1, which is also described here.

[0036] In one embodiment, the first 8-bit stream decryptor 2441, the second 8-bit stream decryptor 2442, the 16-bit stream decryptor 2443, the 32-bit stream decryptor 2444 and the 64-bit stream decryptor 2445 of the aforementioned five-stage decryptor 244 respectively include a decryption linear feedback shift register (LFSR) and one or more decryption logic gates. The decryption linear feedback shift register has a decryption key, which corresponds to the encryption key and can be input into the decryption linear feedback shift register by other devices as a preset decryption key. The devices are not limited to the content of this application and are explained in advance. The decryption linear feedback shift register performs a logic operation on a plurality of decryption bit taps of the decryption key to obtain a decryption operand, and the decryption operand and the received encryption sequence are operated via the decryption logic gate to obtain a decryption sequence, wherein the encryption sequence is fed back to the first bit of the decryption linear feedback shift register as an update of the decryption key, and the update means that the encryption sequence is input to the first bit of the decryption key of the decryption linear feedback shift register, so that the original first bit of the decryption key is moved to the second bit, the original second bit of the decryption key is moved to the third bit, and so on, and the original last bit of the decryption key is covered by the previous bit, thereby updating the decryption key.

[0037] Specifically, see Figure 6, is a logical operation diagram of the five-stage decryptor of the present application, as shown in the figure: the first eight-bit stream decryptor 2441 includes a decryption linear feedback shift register 2441L (stores a first decryption key identical to the first encryption key a[1] to a[8], and is labeled the same as the first encryption key) and a decryption logic gate 2441G; the second eight-bit stream decryptor 2442 includes a decryption linear feedback shift register 2442L (stores a second decryption key identical to the second encryption key b[1] to b[8], and is labeled the same as the second encryption key) and a decryption logic gate 2442G; the sixteen-bit stream decryptor 2443 includes a decryption linear feedback shift register 2443L (stores The 32-bit stream decryptor 2444 includes a decryption linear feedback shift register 2444L (which stores a fourth decryption key which is the same as the fourth encryption key d[1] to d

[32] and is labeled the same as the fourth encryption key) and a decryption logic gate 2444G; the 64-bit stream decryptor 2445 includes a decryption linear feedback shift register 2445L (which stores a fifth decryption key which is the same as the fifth encryption key e[1] to e

[64] and is labeled the same as the fifth encryption key) and a decryption logic gate 2445G. In principle, the logic gate AND logic operation in the fifth-order decryptor 244 must perform the inverse logic operation with the fifth-order encryptor 144 (for example, if the fifth-order encryptor 144 is AND, the fifth-order decryptor 244 is NAND).

[0038] In other embodiments, the aforementioned fifth-order decryptor 244 may also be provided with a multiplexer (MUX) at the front end to determine to which stream decryptor the encryption sequence is input, or a control module (Control Module) may be provided at the front end of the fifth-order decryptor 244 to replace the decryption level setter 242 to determine the activated stream decryptor and part of the functions of the logic gate. Such variations in implementation are not within the scope of the present application.

[0039] In other embodiments, when an advanced encryptor is provided between the aforementioned data generation module 12 and the data encryption module 14 (not shown), an advanced decryptor (not shown) corresponding to the advanced encryptor is provided between the data target module 22 and the data decryption module 24. The advanced encryptor encrypts the data packet PK of the data generation module 12 and outputs it to the data encryption module 14; the advanced decryptor restores the data packet PK to the data target module 22 by decryption processing corresponding to the advanced encryptor. The aforementioned encryption processing is, for example, Advanced Encryption Standard (AES), which is not limited in the present application.

[0040] The above is a description of a specific embodiment of the hardware architecture of the present application. The working procedure of the present application will be further described below. Please refer to Figure 7 , is a flowchart of the adjustable five-stage encryption method of this application:

[0041] Before data transmission, the encryption level setter 142 and the decryption level setter 242 will set the same encryption / decryption level according to the user setting / automatic configuration (for example, when the encryption level setter 142 selects the fifth-level encryption level of the fifth-level encryptor 144, the decryption level setter 242 will select the fifth-level decryptor 244 as the fifth-level decryption level), which is explained here in advance.

[0042] First, in the transmitting device 10, the data packet PK is output from the data generating module 12 to the data encrypting module 14 (step S201).

[0043] The data packet PK is received by the fifth-order encryptor 144 of the data encryption module 14 and is encrypted according to the encryption level set by the encryption level setter 142 (step S202 ).

[0044] The encrypted data packet PK is outputted as an encrypted sequence by the fifth-order encryptor 144 to the receiving device 20 (step S203).

[0045] The encrypted sequence is decrypted by the five-stage decryptor 244 in the data decryption module 24 according to the decryption level corresponding to the encryption level set by the decryption level setter 242 (step S204).

[0046] The decrypted encrypted sequence is outputted by the fifth-order decryptor 244 as a restored data packet to the data target module 22 for storage (step S205).

[0047] In one embodiment, the fifth-order encryptor 144 includes a first eight-bit stream decryptor 2441, a second eight-bit stream decryptor 2442, a sixteen-bit stream decryptor 2443, a thirty-two-bit stream decryptor 2444, and a sixty-four-bit stream decryptor 2445 for encryption; in the case where the fifth-order decryptor 244 includes a first eight-bit stream decryptor 2441, a second eight-bit stream decryptor 2442, a sixteen-bit stream decryptor 2443, a thirty-two-bit stream decryptor 2444, and a sixty-four-bit stream decryptor 2445, please refer to Figure 8 , Fig. 9, which is a schematic diagram of the encryption process of the fifth-order encryptor 144 and the decryption process of the fifth-order decryptor 244 of the present application. The aforementioned step S202 can be replaced by one or more steps among steps S2021-S2025 according to the encryption level, and the multiple steps must exist in sequence (for example: in the case of the fourth-level encryption level, step S202 needs to be replaced by the corresponding step S2024, and steps S2021-S2023 must also be included at this time, so step S202 can be replaced by steps S2021-S2024 in the case of the fourth-level encryption level); step S204 can be replaced by one or more steps among steps S2041-S2045 according to the decryption level, and the multiple steps must exist in reverse sequence (for example: in the case of the fourth-level decryption level, step S204 needs to be replaced by the corresponding step S2042, and steps S2043-S2045 must also be included at this time, so step S204 can be replaced by steps S2042-S2045). The contents of the steps described previously will not be repeated here, but will be explained first. In this embodiment, the logical operations described in the fifth-order encryptor 144 are all XOR; the logical operations described in the fifth-order decryptor 244 are all OR (corresponding to the logical operations of the fifth-order encryptor). In other embodiments, the aforementioned logical operations can be other logical operations such as AND, NAND, which are not limited in this application; in this embodiment, the multiple encryption tap bits selected by the encryption linear feedback shift register and the multiple decryption tap bits and quantities selected by the decryption feedback shift register are only one embodiment, and the encryption / decryption tap bits can be selected and changed in quantity according to actual needs (for example: select the first and seventh bits as encryption / decryption tap bits; select the fourth, fifth, sixth, and eighth bits as encryption / decryption tap bits; select the second and thirty-seventh bits when there are more bits), and the selection of the encryption / decryption tap bits is not within the scope of the application. The aforementioned decryption tap bits will be selected corresponding to the encryption tap bits to match the decryption. In this embodiment, the number of encryption bit taps of the first 8-bit stream encryptor 1441, the 16-bit stream encryptor 1443, and the 32-bit stream encryptor 1444 is two; the number of encryption bit taps of the second 8-bit stream encryptor 1442 and the 64-bit stream encryptor 1445 is four; the number of decryption bit taps of the first 8-bit stream decryptor 2441, the 16-bit stream decryptor 2443, and the 32-bit stream decryptor 2444 is two; the number of decryption bit taps of the second 8-bit stream decryptor 2442 and the 64-bit stream decryptor 2445 is four, which are described here first. In one embodiment, the number of bits of the aforementioned encryption bit taps and decryption bit taps is an even number.

[0048] The following describes steps S2021-S2025. Please refer to Figure 4 , Figure 8 , which is a logical operation diagram and encryption flow diagram of the fifth-order encryptor of the present application. The data packet PK is received by the first eight-bit stream encryptor 1441 of the fifth-order encryptor 144, and the data packet PK is encrypted and output by the first eight-bit stream encryptor 1441 (step S2021).

[0049] In one embodiment, the encryption linear feedback shift register 1441L in the first eight-bit stream encryptor 1441 extracts the second bit a[2] and the seventh bit a[7] for logical operation to obtain the first encryption operand, and the data packet PK and the first encryption operand are encrypted in sequence through the encryption logic gate 1441G for logical operation and output by the first eight-bit stream encryptor 1441; when the encryption level setter 142 is set to first-order encryption, the first eight-bit stream encryptor 1441 outputs the first encryption sequence ES1.

[0050] The data packet PK encrypted and output by the first 8-bit stream encryptor 1441 is received by the second 8-bit stream encryptor 1442, and the second 8-bit stream encryptor 1442 encrypts and outputs the received data packet PK (step S2022).

[0051] In one embodiment, the encryption linear feedback shift register 1442L in the second eight-bit stream encryptor 1442 extracts the second bit b[2], the fifth bit b[5], the sixth bit b[6], and the seventh bit b[7] for logical operation to obtain a second encryption operand, and the data packet PK and the second encryption operand are encrypted in sequence through the encryption logic gate 1442G for logical operation and output by the second eight-bit stream encryptor 1442; when the encryption level setter 142 is set to second-order encryption, the second eight-bit stream encryptor 1442 outputs the second encryption sequence ES2.

[0052] The data packet PK encrypted and outputted by the second 8-bit stream encryptor 1442 is received by the 16-bit stream encryptor 1443, and the 16-bit stream encryptor 1443 encrypts and outputs the received data packet PK (step S2023).

[0053] In one embodiment, the encryption linear feedback shift register 1443L in the sixteen-bit stream encryptor 1443 extracts the fourteenth bit c

[14] and the sixteenth bit c

[16] for logical operation to obtain a third encryption operand, and the data packet PK and the third encryption operand are encrypted in sequence through the encryption logic gate 1443G for logical operation and output by the sixteen-bit stream encryptor 1443; when the encryption level setter 142 is set to third-order encryption, the sixteen-bit stream encryptor 1443 outputs the third encryption sequence ES3.

[0054] The data packet PK encrypted and outputted by the 16-bit stream encryptor 1443 is received by the 32-bit stream encryptor 1444, and the 32-bit stream encryptor 1444 encrypts and outputs the received data packet PK (step S2024).

[0055] In one embodiment, the encryption linear feedback shift register 1444L in the thirty-two-bit stream encryptor 1444 extracts the thirtieth bit d

[30] and the thirty-second bit d

[32] for logical operation to obtain a fourth encryption operand, and the data packet PK and the fourth encryption operand are encrypted and output in sequence through a logical operation via an encryption logic gate 1444G; when the encryption level setter 142 is set to fourth-order encryption, the thirty-two-bit stream encryptor 1444 outputs the fourth encryption sequence ES4.

[0056] The data packet PK encrypted and outputted by the 32-bit stream encryptor 1444 is received by the 64-bit stream encryptor 1445, and the 64-bit stream encryptor 1445 encrypts and outputs the received data packet PK (step S2025).

[0057] In one embodiment, when the encryption level setter 142 is set to fifth-order encryption, the encryption linear feedback shift register 1445L in the sixty-four-bit stream encryptor 1445 extracts the second bit e[2], the sixty-first bit e

[61] , the sixty-second bit e

[62] and the sixty-fourth bit e

[64] for logical operation to obtain the fifth encryption operand, and the data packet PK and the fifth encryption operand are encrypted and output in sequence through the encryption logic gate 1445G for logical operation. At this time, the sixty-four-bit stream encryptor 1445 outputs the fifth encryption sequence ES5.

[0058] The following describes steps S2041-S2045. Please refer to Figure 6 , Fig. 9 , which is a logical operation diagram and a decryption process diagram of the fifth-order decryptor of the present application. The fifth encrypted sequence ES5 is received by the sixty-four-bit stream decryptor 2445 of the fifth-order decryptor 244, and the sixty-four-bit stream decryptor 2445 decrypts the fifth encrypted sequence ES5 and outputs a fifth data packet PK5 (step S2041).

[0059] In one embodiment, when the decryption level is five, the decryption linear feedback shift register 2445L in the sixty-four-bit stream decryptor 2445 extracts the second bit e[2], the sixty-first bit e

[61] , the sixty-second bit e

[62] and the sixty-fourth bit e

[64] for logical operation to obtain the fifth decryption operand, and the fifth encryption sequence ES5 and the fifth decryption operand are logically operated through the decryption logic gate 2445G to be sequentially converted into a fifth data packet PK5 and output to the thirty-two-bit stream decryptor 2444.

[0060] The fifth data packet PK5 is received by the 32-bit stream decryptor 2444 of the fifth-order decryptor 244. The 32-bit stream decryptor 2444 decrypts the fifth data packet PK5 and outputs a fourth data packet PK4 (step S2042).

[0061] In one embodiment, when the decryption level is five, the decryption linear feedback shift register 2444L in the thirty-two-bit stream decryptor 2444 extracts the thirtieth bit d

[30] and the thirty-second bit d

[32] for logical operation to obtain the fourth decryption operand, and the fifth data packet PK5 and the fourth decryption operand are logically operated through the decryption logic gate 2444G to be converted into the fourth data packet PK4 in sequence and output to the sixteen-bit stream decryptor 2443; when the decryption level is four, ... fourth data packet PK4 is output to the sixteen-bit stream decryptor 2443; The decryptor 2444 receives the fourth encrypted sequence ES4 output by the transmitting device 10. At this time, the decryption linear feedback shift register 2444L in the thirty-two-bit stream decryptor 2444 extracts the thirtieth bit d

[30] and the thirty-second bit d

[32] for logical operation to obtain the fourth decryption operand. The fourth encrypted sequence ES4 and the fourth decryption operand are logically operated through the decryption logic gate 2444G and converted into a fourth data packet PK4 in sequence and output to the sixteen-bit stream decryptor 2443.

[0062] The fourth data packet PK4 is received by the 16-bit stream decryptor 2443 of the fifth-order decryptor 244. The 16-bit stream decryptor 2443 decrypts the fourth data packet PK4 and outputs a third data packet PK3 (step S2043).

[0063] In one embodiment, when the decryption level is five or four, the decryption linear feedback shift register 2443L in the sixteen-bit stream decryptor 2443 extracts the fourteenth bit c

[14] and the sixteenth bit c

[16] to perform a logic operation to obtain a third decryption operand, and the fourth data packet PK4 and the third decryption operand are converted into a third data packet PK3 in sequence through the decryption logic gate 2443G and output to the second eight-bit stream decryptor 2442; when the decryption level is three, the sixteen-bit stream decryptor 2443 extracts the fourteenth bit c

[14] and the sixteenth bit c

[16] to perform a logic operation to obtain a third decryption operand, and the fourth data packet PK4 and the third decryption operand are converted into a third data packet PK3 in sequence through the decryption logic gate 2443G and output to the second eight-bit stream decryptor 2442; The decryptor 2443 receives the third encrypted sequence ES3 output by the transmitting device 10. At this time, the decryption linear feedback shift register 2443L in the sixteen-bit stream decryptor 2443 extracts the fourteenth bit c

[14] and the sixteenth bit c

[16] to obtain the third decryption operand after performing a logical operation. The third encrypted sequence ES3 and the third decryption operand are converted into a third data packet PK3 in sequence through a decryption logic gate 2443G for logical operation and output to the second eight-bit stream decryptor 2442.

[0064] The third data packet PK3 is received by the second 8-bit stream decryptor 2442 of the fifth-order decryptor 244. The second 8-bit stream decryptor 2442 decrypts the third data packet PK3 and outputs a second data packet PK2 (step S2044).

[0065] In one embodiment, when the decryption level is five-order, four-order or three-order, the decryption linear feedback shift register 2442L in the second eight-bit stream decryptor 2442 extracts the second bit b[2], the thirteenth bit b

[13] , the fourteenth bit b

[14] and the sixteenth bit b

[16] to obtain the second decryption operand after performing a logic operation, and the third data packet PK3 and the second decryption operand are converted into the second data packet PK2 in sequence through the decryption logic gate 2442G for logic operation and output to the first eight-bit stream decryptor 2441; when the decryption level is two-order, ... second data packet PK3 and the second decryption operand are converted into the second data packet PK2 in sequence through the decryption logic gate 2442G for logic operation and output to the first eight-bit stream decryptor 2441; The bit stream decryptor 2442 receives the second encrypted sequence ES2 output by the transmitting device 10. At this time, the decryption linear feedback shift register 2442L in the second eight-bit stream decryptor 2442 extracts the second bit b[2], the thirteenth bit b

[13] , the fourteenth bit b

[14] and the sixteenth bit b

[16] for logical operation to obtain the second decryption operand. The second encrypted sequence ES2 and the second decryption operand are logically operated through the decryption logic gate 2442G and converted into a second data packet PK2 in sequence and output to the first eight-bit stream decryptor 2441.

[0066] The second data packet PK2 is received by the first eight-bit stream decryptor 2441 of the five-level decryptor 244. The first eight-bit stream decryptor 2441 decrypts the second data packet PK2 and outputs the first data packet PK1 (step S2045). Specifically, when the decryption level is five-level, four-level, three-level or two-level, the decryption linear feedback shift register 2441L in the first eight-bit stream decryptor 2441 extracts the second bit a[2] and the seventh bit a[7] to obtain the first decryption operand after performing a logic operation. The second data packet PK2 and the first decryption operand are converted into the first data packet PK1 in sequence through the decryption logic gate 2441G for logic operation and output to the data target module 22. At this time, the first data packet PK1 is defined as the restored data packet output by the five-level decryptor 244. When the decryption level is one-level, the first eight-bit stream decryptor 2441 extracts the second bit a[2] and the seventh bit a[7] to obtain the first decryption operand. The second data packet PK2 and the first decryption operand are converted into the first data packet PK1 in sequence through the decryption logic gate 2441G for logic operation and output to the data target module 22. At this time, the first data packet PK1 is defined as the restored data packet output by the five-level decryptor 244. The decryptor 2441 receives the first encrypted sequence ES1 output by the transmitting device 10. At this time, the decryption linear feedback shift register 2441L in the first eight-bit stream decryptor 2441 extracts the second bit a[2] and the seventh bit a[7] to obtain the first decryption operand after performing a logical operation. The first encrypted sequence ES1 and the first decryption operand are converted into a first data packet PK1 in sequence through a decryption logic gate 2441G for logical operation and output to the data target module 22. At this time, the first data packet PK1 is defined as the restored data packet output by the five-stage decryptor 244.

[0067] In summary, compared to the prior art, the present application can switch encryption levels according to the required encryption level, and can implement different encryption level protections through a set of hardware.

[0068] The present application has been described in detail above. However, what is described above is only a preferred embodiment of the present application and should not be used to limit the scope of implementation of the present application. That is, all equivalent changes and modifications made according to the claims of the present application should still fall within the scope of the patent coverage of the present application.

Claims

1. An adjustable five-order encryption system, characterized in that: include: A transmitting end device, comprising a data generating module and a data encryption module, wherein the data encryption module comprises an encryption level setting device and a five-stage encryptor, wherein the encryption level setting device is used to set the encryption level of the five-stage encryptor, and the data encryption module obtains at least one data packet from the data generating module, encrypts the data packet via the encryption level selected by the five-stage encryptor, and then outputs an encrypted sequence; as well as The receiving end device comprises a data target module and a data decryption module, wherein the data decryption module comprises a decryption level setting device and a five-stage decryptor, wherein the decryption level setting device is used to set the decryption level of the five-stage decryptor according to the encryption level, and the data decryption module obtains the encryption sequence from the sending end device, decrypts the encryption sequence by decrypting the decryption level selected by the five-stage decryptor, and then outputs the restored data packet to the data target module; The five-stage encryptor includes a first eight-bit stream encryptor, a second eight-bit stream encryptor, a sixteen-bit stream encryptor, a thirty-two-bit stream encryptor and a sixty-four-bit stream encryptor connected in sequence; the five-stage decryptor includes a first eight-bit stream decryptor, a second eight-bit stream decryptor, a sixteen-bit stream decryptor, a thirty-two-bit stream decryptor and a sixty-four-bit stream decryptor connected in sequence; an input end of the first eight-bit stream encryptor is connected to an output end of the encryption level setter, and another input end is connected to a data generation module for receiving a data packet; An input terminal of the second 8-bit stream encryptor is connected to the output terminal of the encryption level setter, and another input terminal is connected to the output terminal of the first 8-bit stream encryptor; The input end of the 16-bit stream encryptor is connected to the output end of the encryption level setter, and the other input end is connected to the output end of the second 8-bit stream encryptor; the input end of the 32-bit stream encryptor is connected to the output end of the encryption level setter, and the other input end is connected to the output end of the 16-bit stream encryptor; the input end of the 64-bit stream encryptor is connected to the output end of the encryption level setter, and the other input end is connected to the output end of the 32-bit stream encryptor; The encryption level setter selects which of the first 8-bit stream encryptor, the second 8-bit stream encryptor, the 16-bit stream encryptor, the 32-bit stream encryptor, and the 64-bit stream encryptor to activate and which one to output the encrypted data packet according to the encryption level, and when the stream encryptor at the rear of the sequence is activated, the stream encryptor in front of the stream encryptor must also be activated.

2. The adjustable five-stage encryption system as claimed in claim 1, characterized in that: The first 8-bit stream encryptor, the second 8-bit stream encryptor, the 16-bit stream encryptor, the 32-bit stream encryptor and the 64-bit stream encryptor respectively include an encryption linear feedback shift register and one or more encryption logic gates, the encryption linear feedback shift register has an encryption key, the encryption linear feedback shift register performs a logic operation on multiple encryption bit taps of the encryption key to obtain an encryption operand, the encryption operand and the data packet are operated through the encryption logic gate to obtain the encryption sequence of the corresponding layer; the first 8-bit stream decryptor, the second 8-bit stream decryptor, the 16-bit stream decryptor, the 32-bit stream decryptor and the 64-bit stream decryptor respectively include a decryption linear feedback shift register and one or more decryption logic gates, the decryption linear feedback shift register has a decryption key, the decryption linear feedback shift register performs a logic operation on multiple decryption bit taps of the decryption key to obtain a decryption operand, the decryption operand and the encryption sequence are operated through the decryption logic gate to restore the data packet of the corresponding layer.

3. The adjustable five-stage encryption system as claimed in claim 2, characterized in that: The number of bits of the encryption bit tap and the decryption bit tap is an even number.

4. The adjustable five-stage encryption system as claimed in claim 3, characterized in that: The number of encryption bit taps of the first eight-bit stream encryptor, the sixteen-bit stream encryptor, and the thirty-two-bit stream encryptor is two; the number of encryption bit taps of the second eight-bit stream encryptor and the sixty-four-bit stream encryptor is four; the number of decryption bit taps of the first eight-bit stream decryptor, the sixteen-bit stream decryptor, and the thirty-two-bit stream decryptor is two; the number of decryption bit taps of the second eight-bit stream decryptor and the sixty-four-bit stream decryptor is four.

5. A transmitting end device, characterized in that: include: Data generation module; as well as a data encryption module, the data encryption module comprising an encryption level setter and a five-stage encryptor, the encryption level setter being used to set the encryption level of the five-stage encryptor, the data encryption module obtaining at least one data packet from the data generation module, encrypting the data packet via the encryption level selected by the five-stage encryptor, and then outputting an encrypted sequence; The five-stage encryptor includes a first 8-bit stream encryptor, a second 8-bit stream encryptor, a 16-bit stream encryptor, a 32-bit stream encryptor and a 64-bit stream encryptor connected in sequence; an input end of the first 8-bit stream encryptor is connected to an output end of the encryption level setter, and another input end is connected to the data generation module for receiving a data packet; An input terminal of the second 8-bit stream encryptor is connected to the output terminal of the encryption level setter, and another input terminal is connected to the output terminal of the first 8-bit stream encryptor; The input end of the 16-bit stream encryptor is connected to the output end of the encryption level setter, and the other input end is connected to the output end of the second 8-bit stream encryptor; the input end of the 32-bit stream encryptor is connected to the output end of the encryption level setter, and the other input end is connected to the output end of the 16-bit stream encryptor; the input end of the 64-bit stream encryptor is connected to the output end of the encryption level setter, and the other input end is connected to the output end of the 32-bit stream encryptor; The encryption level setter selects which of the first 8-bit stream encryptor, the second 8-bit stream encryptor, the 16-bit stream encryptor, the 32-bit stream encryptor, and the 64-bit stream encryptor to activate and which one to output the encrypted data packet according to the encryption level, and when the stream encryptor at the rear of the sequence is activated, the stream encryptor in front of the stream encryptor must also be activated.

6. The transmitting end device according to claim 5, characterized in that: The first 8-bit stream encryptor, the second 8-bit stream encryptor, the 16-bit stream encryptor, the 32-bit stream encryptor and the 64-bit stream encryptor respectively include an encryption linear feedback shift register and one or more encryption logic gates. The encryption linear feedback shift register has an encryption key. The encryption linear feedback shift register performs a logic operation on multiple encryption bit taps of the encryption key to obtain an encryption operand. The encryption operand and the data packet are operated through the encryption logic gate to obtain the encryption sequence corresponding to the encryption level.

7. The transmitting end device according to claim 6, characterized in that: The number of bits of the encryption bit tap is an even number.

8. The transmitting end device according to claim 7, characterized in that: The number of encryption bit taps of the first eight-bit stream encryptor, the sixteen-bit stream encryptor, and the thirty-two-bit stream encryptor is two; the number of encryption bit taps of the second eight-bit stream encryptor and the sixty-four-bit stream encryptor is four.

9. A receiving end device, characterized in that: include Data object module; and a data decryption module, the data decryption module comprising a decryption level setter and a five-stage decryptor, the decryption level setter being used to set the decryption level of the five-stage decryptor according to the encryption level, the data decryption module obtaining an encrypted sequence from a transmitting end device, decrypting the encrypted sequence by decrypting the decryption level selected by the five-stage decryptor, and then outputting a restored data packet to the data target module; The five-stage decryptor includes a first eight-bit stream decryptor, a second eight-bit stream decryptor, a sixteen-bit stream decryptor, a thirty-two-bit stream decryptor, and a sixty-four-bit stream decryptor connected in sequence; The decryption level setting device selects a stream decryptor to be activated according to the decryption level and selects a stream decryptor to which an encrypted sequence is to be input according to the decryption level, thereby decrypting the encrypted sequence in sequence, and when a stream decryptor located at the front of the sequence is activated, a stream decryptor behind the stream decryptor must also be activated; When the decryption level setter sets the second-order decryption level corresponding to the second-order encryption level, the decryption level setter starts the second eight-bit stream decryptor and starts the first eight-bit stream decryptor. After the decryption level setter inputs the encryption sequence into the second eight-bit stream decryptor according to the second-order decryption level, the encryption sequence is decrypted by the second eight-bit stream decryptor and the first eight-bit stream decryptor, and the first eight-bit stream decryptor outputs the decrypted encryption sequence, thereby performing decryption of the second-order decryption level; the remaining unused sixteen-bit stream decryptor, the thirty-two-bit stream decryptor, and the sixty-four-bit stream decryptor are not started.

10. The receiving end device according to claim 9, characterized in that: The first 8-bit stream decryptor, the second 8-bit stream decryptor, the 16-bit stream decryptor, the 32-bit stream decryptor and the 64-bit stream decryptor respectively include a decryption linear feedback shift register and one or more decryption logic gates. The decryption linear feedback shift register has a decryption key. The decryption linear feedback shift register performs a logical operation on multiple decryption bit taps of the decryption key to obtain a decryption operand. The decryption operand and the encryption sequence are operated through the decryption logic gate to restore the data packet corresponding to the encryption level.

11. The receiving end device according to claim 10, characterized in that: The number of bits of the decryption bit tap is an even number.

12. The receiving device according to claim 11, characterized in that: The number of decryption bit taps of the first 8-bit stream decryptor, the 16-bit stream decryptor, and the 32-bit stream decryptor is two; the number of decryption bit taps of the second 8-bit stream decryptor and the 64-bit stream decryptor is four.

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