Heat recovery for data center cooling systems

Abstract

Systems and methods for cooling a data center are disclosed. In at least one embodiment, an absorption chiller includes a generator vessel to enable removal of heat from a fluid returned from at least one computing component of the data center.

Description

TECHNICAL FIELD

[0001] At least one embodiment relates to cooling systems, including systems and methods for operating those cooling systems. In at least one embodiment, such cooling systems can be used in data centers containing one or more racks or computing servers. BACKGROUND

[0002] Data center cooling systems use fans to circulate air through server components. Certain supercomputers or other high-capacity computers can use water or other cooling systems in addition to air cooling systems to draw heat away from server components or racks of a data center to an area outside of the data center. The cooling system can include chillers within the data center area (including areas outside of the data center itself). Further, the area outside of the data center can include an area of a cooling tower or other external heat exchanger that receives heated coolant from the data center and dissipates heat to the environment (or an external cooling medium) through forced air or other means. The cooled coolant is recirculated back to the data center. The chillers and cooling tower collectively make up a cooling plant. SUMMARY

[0003] In one embodiment, a heat recovery system for a data center cooling system is disclosed, including: an absorption chiller including a generator vessel coupled to one or more computing components of a data center through a primary cooling loop to receive heat from fluid returned from the one or more computing components; an auxiliary cooling loop associated with and operable as an auxiliary coolant for the fluid; and one or more flow control valves associated with the auxiliary cooling loop for enabling the auxiliary coolant to be shunted from the auxiliary cooling loop to the heat recovery system and for returning the fluid to a cooling distribution unit (CDU) or to the one or more computing components.

[0004] In one embodiment, a data center cooling system is disclosed, including: a generator vessel coupled to one or more computing components of a data center through a primary cooling loop to receive heat from fluid returned from the one or more computing components, the generator vessel included in an absorption chiller within the data center cooling system; an auxiliary cooling loop associated with and operable as an auxiliary coolant for the fluid; and one or more flow control valves associated with the auxiliary cooling loop for enabling the auxiliary coolant to be shunted from the auxiliary cooling loop to the generator vessel and for returning the fluid to a cooling distribution unit (CDU) or to the one or more computing components.

[0005] In one embodiment, a method for a data center liquid cooling system is disclosed, comprising: providing a heat recovery system including an absorption chiller having a generator vessel; coupling the generator vessel through a primary cooling loop to one or more computing components of a data center to receive heat from fluid returned from the one or more computing components; determining that the fluid returned from the one or more computing components has heat that can be addressed by the absorption chiller; enabling the generator vessel to remove at least a portion of the heat from the fluid; providing an auxiliary coolant associated with an auxiliary cooling loop to be operable as the fluid; shunting the auxiliary coolant from the auxiliary cooling loop to the heat recovery system; and enabling the fluid to be returned to a cooling distribution unit (CDU) or to the one or more computing components. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 An exemplary data center cooling system subject to improvements described in at least one embodiment is shown;

[0007] Figure 2 Server-level features associated with a heat recovery system for a data center cooling system according to at least one embodiment are shown;

[0008] Figure 3 Rack-level features associated with a heat recovery system for a data center cooling system according to at least one embodiment are shown;

[0009] Figure 4 Data center-level features associated with a heat recovery system for a data center cooling system according to at least one embodiment are shown;

[0010] Figure 5 A method associated with a data center cooling system of Figures 2-4 according to at least one embodiment is shown;

[0011] Figure 6 A distributed system according to at least one embodiment is shown;

[0012] Figure 7 An exemplary data center according to at least one embodiment is shown;

[0013] Figure 8 A client-server network according to at least one embodiment is shown;

[0014] Figure 9 A computer network according to at least one embodiment is shown;

[0015] Figure 10A A networked computer system according to at least one embodiment is shown;

[0016] Figure 10B A networked computer system is shown in accordance with at least one embodiment;

[0017] Figure 10C A networked computer system is shown in accordance with at least one embodiment;

[0018] Figure 11 One or more components of a system environment in which services can be provided as third party network services are shown in accordance with at least one embodiment;

[0019] Figure 12 A cloud computing environment is shown in accordance with at least one embodiment;

[0020] Figure 13 A set of functional abstraction layers provided by a cloud computing environment is shown in accordance with at least one embodiment;

[0021] Figure 14 A supercomputer at the chip level is shown in accordance with at least one embodiment;

[0022] Figure 15 A supercomputer at the rack module level is shown in accordance with at least one embodiment;

[0023] Figure 16 A supercomputer at the rack level is shown in accordance with at least one embodiment;

[0024] Figure 17 A supercomputer at the entire system level is shown in accordance with at least one embodiment;

[0025] Figure 18A Inference and / or training logic is shown in accordance with at least one embodiment;

[0026] Figure 18B Inference and / or training logic is shown in accordance with at least one embodiment;

[0027] Figure 19 Training and deployment of a neural network is shown in accordance with at least one embodiment;

[0028] Figure 20 An architecture of a network system is shown in accordance with at least one embodiment;

[0029] Figure 21 An architecture of a network system is shown in accordance with at least one embodiment;

[0030] Figure 22 A control plane protocol stack is shown in accordance with at least one embodiment;

[0031] Figure 23A user plane protocol stack is shown in accordance with at least one embodiment;

[0032] Figure 24 Components of a core network are shown in accordance with at least one embodiment;

[0033] Figure 25 Components of a system that supports network function virtualization (NFV) are shown in accordance with at least one embodiment;

[0034] Figure 26 A processing system is shown in accordance with at least one embodiment;

[0035] Figure 27 A computer system is shown in accordance with at least one embodiment;

[0036] Figure 28 A system is shown in accordance with at least one embodiment;

[0037] Figure 29 An exemplary integrated circuit is shown in accordance with at least one embodiment;

[0038] Figure 30 A computing system is shown in accordance with at least one embodiment;

[0039] Figure 31 An APU is shown in accordance with at least one embodiment;

[0040] Figure 32 A CPU is shown in accordance with at least one embodiment;

[0041] Figure 33 An exemplary accelerator integration slice is shown in accordance with at least one embodiment;

[0042] Figures 34A-34B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0043] Figure 35A A graphics core is shown in accordance with at least one embodiment;

[0044] Figure 35B A GPGPU is shown in accordance with at least one embodiment;

[0045] Figure 36A A parallel processor is shown in accordance with at least one embodiment;

[0046] Figure 36B A processing cluster is shown in accordance with at least one embodiment;

[0047] Figure 36C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0048] Figure 37 a software stack of a programming platform is shown in accordance with at least one embodiment;

[0049] Figure 38 a software stack of a programming platform is shown in accordance with at least one embodiment; Figure 37 a CUDA implementation of the software stack of

[0050] Figure 39 a ROCm implementation of the software stack of Figure 37

[0051] Figure 40 an OpenCL implementation of the software stack of Figure 37

[0052] Figure 41 software supported by a programming platform is shown in accordance with at least one embodiment; and

[0053] Figure 42 compiled code for execution on a programming platform of Figures 37-40 is shown in accordance with at least one embodiment. DETAILED DESCRIPTION

[0054] In the following description, numerous specific details are set forth to provide a more thorough understanding of the embodiments. However, it will be apparent to one of skill in the art that the present inventive concept can be practiced without one or more of these specific details.

[0055] In at least one embodiment, air cooling of high density servers can not be effective or can be ineffective in view of sudden high heat demand caused by varying computational loads in today’s computing components. In at least one embodiment, as the demand goes through a range between a minimum to a maximum of different cooling demands, appropriate cooling systems must be used to meet these demands in an economical way. In at least one embodiment, for medium to high cooling demands, liquid cooling systems can be used. In at least one embodiment, different cooling demands also reflect different thermal signatures of data centers. In at least one embodiment, heat generated from components, servers, and racks is cumulatively referred to as a thermal signature or cooling demand, as the cooling demand must fully address the thermal signature.

[0056] ​​In at least one embodiment, a data center liquid cooling system is disclosed. In at least one embodiment, the data center cooling system addresses thermal signatures in associated computing or data center devices or components, such as a graphics processing unit (GPU), a switch, a dual in-line memory module (DIMM), or a central processing unit (CPU). Further, in at least one embodiment, the associated computing or data center device can be a processing card with one or more GPUs, switches, or CPUs thereon. In at least one embodiment, each of the GPUs, switches, and CPUs can be a heat-generating feature of a computing device. In at least one embodiment, the GPUs, CPUs, or switches can have one or more cores, and each core can be a heat-generating feature.

[0057] In at least one embodiment, data center components can be designed for high computing demands of artificial intelligence / machine learning (AI / ML) and other high performance computing (HPC) applications. In at least one embodiment, these data center components can be high heat density components that require reliable and economical heat dissipation. In at least one embodiment, because these data center components can generate a large amount of heat, waste heat utilization, such as in a heat recovery system, is suitable for a data center cooling system. In at least one embodiment, when using the heat recovery system herein in a liquid cooling system for high heat density components, data center efficiency can be improved and free cooling within the data center can be facilitated. In at least one embodiment, such waste heat utilization reduces the environmental impact of data center cooling and reduces the carbon footprint of the data center.

[0058] In at least one embodiment, an absorption chiller can be positioned and calibrated to receive heat from fluid returning from a data center. In at least one embodiment, the fluid can be a coolant. In at least one embodiment, the absorption chiller has a working fluid that is different from the fluid returning from and being sent to the data center. In at least one embodiment, the working fluid is a mixed solution with lithium bromide as an absorbent material and water as a carrier material. In at least one embodiment, the fluid returning from the data center can be a secondary coolant of a secondary cooling loop. In at least one embodiment, the fluid can return from cold plates or immersion liquid-cooled servers of the data center. In at least one embodiment, the fluid can be introduced directly or indirectly (e.g., through a heat exchanger or burner stage) into a generator vessel of a single-stage or multi-stage absorption chiller.

[0059] In at least one embodiment, the absorption chiller functions to cool the fluid by enabling the generator vessel to transfer heat from the fluid to its contents to remove at least a portion of the heat from the fluid. In at least one embodiment, a portion of the heat is transferred to the generator vessel, which in turn transfers heat to the contents of the generator vessel, such as a working fluid. In at least one embodiment, a portion of the heat supplements the combustor of the combustor stage used with the generator vessel to reach a temperature that enables separation of the absorption material from the working fluid in the absorption chiller. In at least one embodiment, the fluid of the data center can be returned to the data center to cool the cold plates or data center components immersed in the liquid-cooled servers. In at least one embodiment, the fluid can be removed from the fluid of the heat removed by a chiller distribution unit (CDU) interfacing the fluid with a primary coolant of a primary cooling loop having an external cooling facility.

[0060] In at least one embodiment, cooling the fluid by the absorption chiller enables cooling of at least a portion of the working fluid in an evaporation region that houses the evaporating coils in the absorption chiller. In at least one embodiment, the fluid can be further cooled in the evaporation region after the CDU. In at least one embodiment, a separate cooling loop can include a separate fluid (compared to the data center fluid or working fluid) for other cooling functions of the data center, including cooling of personnel spaces in or near the data center, heating, ventilation, and air conditioning (HVAC) units. In at least one embodiment, the absorption chiller can be beneficial in its own capacity or as a supplemental cooling feature to the data center cooling system. In at least one embodiment, the absorption chiller can remove more than 1 kW of heat from the fluid returned from the data center components.

[0061] In at least one embodiment, as Figure 1An exemplary data center 100 is shown, having a cooling system subject to improvements described herein. In at least one embodiment, the data center 100 can be one or more spaces 102 having racks 110 and ancillary equipment for housing one or more servers on one or more server trays. In at least one embodiment, the data center 100 is supported by a cooling tower 104 located outside of the data center 100. In at least one embodiment, the cooling tower 104 dissipates heat from within the data center 100 by acting on a primary cooling loop 106. In at least one embodiment, a cooling distribution unit (CDU) 112 is used between the primary cooling loop 106 and a secondary or auxiliary cooling loop 108 to enable heat to be extracted from the secondary or auxiliary cooling loop 108 to the primary cooling loop 106. In at least one embodiment, the auxiliary cooling loop 108 can access different pipes into the server trays as needed throughout, in one aspect. In at least one embodiment, the loops 106, 108 are shown as line diagrams, but one of ordinary skill will recognize that one or more pipe features can be used. In at least one embodiment, flexible polyvinyl chloride (PVC) tubing can be used with associated piping to move fluid along each of the loops 106, 108. In at least one embodiment, one or more coolant pumps can be used to maintain a pressure differential within the loops 106, 108 to enable the coolant to move according to temperature sensors in different locations, including in the room, in one or more racks 110, and / or in server cabinets or server trays within the racks 110.

[0062] In at least one embodiment, the coolant in the primary cooling loop 106 and the auxiliary cooling loop 108 can be at least water and an additive, such as ethylene glycol or propylene glycol. In operation, in at least one embodiment, each of the primary cooling loop and the auxiliary cooling loop has its own coolant. In at least one embodiment, the coolant in the auxiliary cooling loop can be dedicated to the requirements of the components in the server trays or racks 110. In at least one embodiment, the CDU 112 is capable of complex control of the coolant in the loops 106, 108 independently or simultaneously. In at least one embodiment, the CDU can be adapted to control flow rates so that the coolant is properly distributed to draw heat generated within the racks 110. In at least one embodiment, more flexible tubing 114 is provided from the auxiliary cooling loop 108 to enter each server tray and provide coolant to electrical and / or computing components.

[0063] In at least one embodiment, electrical and / or computing components are used interchangeably to refer to heat-generating components that benefit from the present data center cooling system. In at least one embodiment, tubing 118 forming part of secondary cooling loop 108 can be referred to as a room manifold. Separately, in at least one embodiment, tubing 116 extending from tubing 118 can also be part of secondary cooling loop 108, but can be referred to as a row manifold. In at least one embodiment, tubing 114 enters a rack as part of secondary cooling loop 108, but can be referred to as a rack cooling manifold. In at least one embodiment, row manifold 116 extends along a row in data center 100 to all racks. In at least one embodiment, ductwork of secondary cooling loop 108 including manifolds 118, 116, and 114 can be improved by at least one embodiment of the present disclosure. In at least one embodiment, chillers 120 can be provided in a primary cooling loop within data center 102 to support cooling prior to a cooling tower. In at least one embodiment, to the extent that additional loops exist in a primary control loop, one of ordinary skill in the art, upon reading the present disclosure, will recognize that these additional loops provide cooling outside of a rack and outside of a secondary cooling loop; and can be incorporated with a primary cooling loop for the present invention.

[0064] In at least one embodiment, in operation, heat generated within server trays of rack 110 can be transferred via flexible tubing of row manifold 114 of secondary cooling loop 108 to coolant exiting rack 110. In at least one embodiment, second coolant from CDU 112 for cooling rack 110 (in secondary cooling loop 108) moves toward rack 110. In at least one embodiment, second coolant from CDU 112 is transferred from one side of room manifold having tubing 118 via row manifold 116 to one side of rack 110 and via tubing 114 through one side of server trays. In at least one embodiment, used or returned second coolant (or exiting second coolant taking heat away from computing components) exits from another side of server trays (such as entering a left side of a rack for server trays after circulating through server trays or through components on server trays and exiting a right side of the rack). In at least one embodiment, used second coolant exiting server trays or rack 110 comes out from a different side (such as an exit side) of tubing 114 and moves to a parallel also exit side of row manifold 116. In at least one embodiment, used second coolant moves from row manifold 116 in a parallel section to room manifold 118, travels in an opposite direction from incoming second coolant (which can also be newer second coolant), and toward CDU 112.

[0065] In at least one embodiment, the spent secondary coolant exchanges its heat with the primary coolant in the primary cooling loop 106 via the CDU 112. In at least one embodiment, the spent secondary coolant may be refreshed (such as relatively cooler when compared to the temperature of the spent secondary coolant stage) and ready to be circulated back through the auxiliary cooling loop 108 to the computing components. In at least one embodiment, various flow and temperature control features in the CDU 112 enable control of the exchange of heat from the spent secondary coolant or the flow of secondary coolant into and out of the CDU 112. The CDU 112 may also be capable of controlling the flow of the primary coolant in the primary cooling loop 106.

[0066] In at least one embodiment, Figure 2 The illustrated server-level feature 200 can be associated with a heat recovery system for a data center cooling system. In at least one embodiment, the server-level feature 200 includes a server tray or box 202, which can be directly or indirectly connected to a heat recovery system 250. In at least one embodiment, the server tray 202 includes a server manifold 204 connected directly or intermediately between the cold plates 210A-D of the server tray or box 202 and the heat recovery system 250. In at least one embodiment, other intermediate components, such as a rack manifold, can exist between the server tray or box 202 and the heat recovery system 250. In at least one embodiment, the server tray or box 202 includes one or more cold plates 210A-D associated with one or more computing or data center components or devices 220A-D. In at least one embodiment, one or more server-level cooling circuits 214A, B are provided between the server manifold 204 and the cold plates 210A-D. In at least one embodiment, each server-level cooling circuit 214A, B includes an inlet line 210 and an outlet line 212. In at least one embodiment, when there are cold plates 210A, B configured in series, an intermediate line 216 may be provided to couple between the cold plates 210A, B to provide a return path for the auxiliary coolant.

[0067] In at least one embodiment, the cold plates 210A-D can be directly associated with the heat recovery system 250 via server-level cooling loops 214A, B. In at least one embodiment, the server trays or boxes 202 can be immersion-cooled server trays or boxes. In at least one embodiment, the immersion-cooled server trays or boxes can be connected to the heat recovery system 250 directly or through a manifold. In at least one embodiment, when a server manifold 204 is used between the cold plates 210A-D and the heat recovery system, inlet and outlet lines 206A, B; 208B, B can connect the server manifold 204 to the rack manifold, e.g., Figure 3rack manifold shown in FIG. 2. In at least one embodiment, use of the rack manifold allows for indirect association of the cold plates 210A-D and the heat recovery system 250.

[0068] In at least one embodiment, the heat recovery system 250 for a data center cooling system can be an absorption chiller 250. In at least one embodiment, the absorption chiller 250 includes a generator vessel 252, an absorber vessel 254, a condenser 256, and an evaporation region 258. In at least one embodiment, the evaporation region 258 can be separate or a region within the generator vessel of the absorption chiller. In at least one embodiment, the generator vessel 252 can be adapted to remove heat from a fluid returning within a data center. In at least one embodiment, the fluid enters the absorption chiller via an inlet line 260. In at least one embodiment, the fluid can be associated with at least one computing component 210A;B;C;D of a data center and can be returned from the at least one computing component having extracted heat from the at least one computing component.

[0069] In at least one embodiment, the absorption chiller 250 can have two modes of operation. In at least one embodiment, a first mode of operation of the absorption chiller uses a mixed solution or working fluid different from the fluid to cool the fluid. In at least one embodiment, after a first cooling in the heat recovery system 250, the fluid can be circulated to a CDU for further cooling. In at least one embodiment, after the CDU, the fluid can additionally be circulated in an evaporation region for further cooling.

[0070] In at least one embodiment, a second mode of operation of the absorption chiller cools the fluid completely to a temperature that allows the fluid to be circulated back to the at least one computing device for further extraction of heat from the at least one computing device. In at least one embodiment, contents of the generator vessel are heated by heat returned in the fluid after circulation through a cold plate associated with the at least one computing component in a data center. In at least one embodiment, the mixed solution of the absorption chiller enables a cooling cycle of the absorption chiller 250. In at least one embodiment, if the mixed solution (and portions thereof) is depleted during the cooling cycle, the mixed solution (and portions thereof) can be replenished.

[0071] In at least one embodiment, in either mode of operation, the working fluid can be a mixed solution of different parts. In at least one embodiment, the mixed solution includes parts of lithium bromide and industrial water. In at least one embodiment, the combination provides beneficial thermal properties relative to using one or the other alone. In at least one embodiment, the ratio is determined from the thermal properties and data of the heat recovery system and the heat generated in the data center. In at least one embodiment, the return fluid can be at about 65-73°C (150-165°F), which is below the 100°C (212°F) boiling point of water at normal atmospheric pressure, e.g., 1 atmosphere (atm) pressure. In at least one embodiment, the return fluid can be used to evaporate the contents of the generator vessel by its own heat, or can supplement or can indirectly heat a burner, which then provides heat to the generator vessel (or contents therein). In at least one embodiment, the heat can be used to evaporate the contents in the generator vessel. In at least one embodiment, the contents must be able to evaporate at least at the temperature of the return fluid. In at least one embodiment, at least one material of the contents must be able to evaporate and can use a pressure lower than atmospheric pressure (e.g., vacuum) in the generator vessel to achieve evaporation. In at least one embodiment, the contents are a mixed solution of at least two materials. In at least one embodiment, the working pressure of the evaporation region and absorber vessel can be about 0.01 atmospheres (ATM), and the working pressure associated with the generator vessel and condenser can be about 0.1 ATM.

[0072] In at least one embodiment, the ratio of the mixed solution can be selected so that the mixed solution has thermal properties that enable separation (e.g., by evaporation) of at least one material of the mixed solution. In at least one embodiment, the separation can be performed at or below the temperature of the return fluid, independent of the pressure applied on the mixed solution. In at least one embodiment, the ratio of the mixed solution can be selected to produce a mixed solution with thermal properties that enable separation of at least one material of the mixed solution at a temperature below the return fluid temperature at low pressure (e.g., in a vacuum). In at least one embodiment, in the second mode of operation, the ratio of the working fluid can be selected so that the temperature required to separate at least one material is effective to remove heat from the return fluid that allows the return of the fluid back into the secondary cooling loop.

[0073] In at least one embodiment, in the second mode of operation, the temperature of the return fluid reflects a temperature that can be above the boiling point of the working fluid, which is not simply industrial water, and when it is at a lower pressure than atmospheric pressure, such as in a vacuum within the generator vessel 252. In at least one embodiment, in the first mode of operation, the temperature of the return fluid reflects a temperature that can be above the boiling point of the mixed solution within the generator vessel 252. In at least one embodiment, the mixed solution can include more absorbent material with a lower boiling point to lower the boiling point of the mixed solution such that the lower pressure in the generator vessel 252 is able to separate at the lower boiling point of the mixed solution. In at least one embodiment, the requirement in either mode of operation can be to enable at least one material in the generator vessel 252 to evaporate or otherwise separate. In at least one embodiment, when the working fluid or mixed solution is above the boiling point, the vapor pressure of the working fluid or mixed solution can be sufficient to cause vaporization of at least one material of the working fluid or mixed solution. In at least one embodiment, the at least one material can be used elsewhere in the absorption chiller 250, such as in the evaporative coil 268, to enable cooling of a different coolant or other fluid in the features 278, 280. In at least one embodiment, the different coolant or other fluid in the features 278, 280 can be circulated in a personnel space, a heating, ventilation, and air conditioning (HVAC) unit of a data center, or in a vicinity of a data center to cool these areas by blowing air over the features 278 (e.g., conduction ducts) or through a heat exchanger associated with the features 278.

[0074] In at least one embodiment, the generator vessel 252 can be held at a pressure that is lower than atmospheric pressure. In at least one embodiment, the lower pressure within the generator vessel ensures that the working fluid, even when heated to a temperature that is below the boiling point of industrial water, has a sufficient effect on the working fluid or mixed solution to cause separation of the absorbent material from a carrier material that can initially be present in the working fluid or mixed solution within the generator vessel. In at least one embodiment, the low pressure can be varied to enable separation of the working fluid at the temperature of the return fluid or other temperature. In at least one embodiment, the heat in the return fluid can be sufficient to vaporize the absorbent material at the pressure that has been set for the generator vessel, thereby separating it from the carrier material in the first mode of operation, but can include removal of residual heat at the CDU and / or evaporation zone (after the CDU).

[0075] In at least one embodiment, a jacket or coil 272 disposed around or within the generator vessel 252 forms a portion of the generator vessel 252 to enable the return secondary fluid to flow around the generator vessel 252. In at least one embodiment, this flow can be external or internal to the generator vessel 252, such as in a jacket or coil 272 forming a heat exchange tube for the generator vessel 252. In at least one embodiment, the jacket or coil 272 is capable of radiative heat exchange between the return fluid and the working fluid. In at least one embodiment, the secondary fluid returning from the data center (e.g., from at least one computing component, server, or rack of a data center) carries heat transferred to it from the at least one computing component, server, or rack.

[0076] In at least one embodiment, in the first mode of operation, a portion of the heat from the return fluid can be transferred to the contents of the generator vessel 252 without a physical connection between the return fluid and the contents. In at least one embodiment, the heat transferred from the fluid to the contents causes the fluid to lose the portion transferred, but the fluid can have residual heat. In at least one embodiment, the heat transferred from the fluid to the contents causes the contents to gain the portion transferred. In at least one embodiment, the action of thermodynamics can be understood to have losses, and thus can not be a perfect transfer of heat. In at least one embodiment, the heat transferred can have a slight variation acceptable to thermodynamics.

[0077] In at least one embodiment, the generator vessel is capable of removing heat from the fluid (e.g., secondary coolant or other return fluid from at least one component, server, or rack of a data center), such as by maintaining a low pressure within the generator vessel and / or in association with a burner that is heated or supplemented by the heat. In at least one embodiment, the fluid continues to have residual heat in the first mode of operation. In at least one embodiment, the CDU can be used to remove all or a portion of the residual heat by interfacing the fluid with the primary coolant of the primary cooling loop. In at least one embodiment, the fluid can be passed to an evaporation region for further cooling after the CDU. In at least one embodiment, when the contents of the generator vessel 252 are an absorption material and a carrier material in a mixed solution, the transfer of heat to the contents of the generator vessel 252 (or the contents gained from the portion of the heat transferred from the fluid) causes the absorption material to separate from the carrier material in the generator vessel 252. In at least one embodiment, the absorption material evaporates from the mixed solution of the generator vessel 252.

[0078] In at least one embodiment, the return fluid has waste heat for the heat recovery system 250. In at least one embodiment, instead of having the main cooling loop (and thus the cooling facility) consume energy to cool the fluid returning from the data center, the energy already present in the fluid can be used to directly or indirectly cause its own cooling. In at least one embodiment, in the second mode of operation, the heat in the return fluid can be cycled through a heat exchanger in the generator vessel (or to a combustor) such that a majority of the heat in the fluid is removed and the temperature is low enough to allow the fluid to re-enter the at least one computing component without further cooling in the CDU. In at least one embodiment, in the first mode of operation, a portion of the heat that can be present in the return fluid can be removed in the CDU via a split flow path 274 to the CDU and a portion of the heat can be simultaneously removed in the heat recovery system 250 through path 260. In at least one embodiment, in the second mode of operation, the low pressure in the generator vessel 252 is able to remove a portion of the heat in the return fluid, which can be referred to as a first portion of heat, and the CDU can be for removing residual heat, referred to as a second portion of heat. In at least one embodiment, further cooling in the evaporation region can also remove residual heat, or can provide further cooling if no more heat remains in the return fluid. In at least one embodiment, the first heat, the second heat, the residual heat, and the further cooling can be related to a temperature of the fluid first entering the at least one computing component.

[0079] In at least one embodiment, the transition in the working fluid by the low pressure of the generator vessel has included the transfer of heat to the contents of the generator vessel. In at least one embodiment, this can be the vaporization of at least a portion of the material in the mixed solution forming the contents of the generator vessel. In at least one embodiment, this enables the generator vessel to remove the first heat from the fluid (and transfer the contents of the generator vessel). In at least one embodiment, since the working fluid can be composed of material portions, including an absorbent material (such as lithium bromide) and a carrier material (such as industrial water), removing the first heat from the return fluid can be thermodynamically achieved by the separation of the absorbent material from the carrier material in the generator vessel 252.

[0080] In at least one embodiment, the working fluid can remain in its mixed solution state at the temperature at which it is delivered without a lower pressure in the generator vessel. In at least one embodiment, the temperature of the fluid returning from the data center can be sufficient to separate the absorbent material from the carrier material under appropriate thermodynamic conditions (e.g., using a pressure-temperature chart for one or more fluid materials to provide an appropriate lower pressure for the temperature). In at least one embodiment, the generator vessel 252 can thus be maintained at a pressure lower than atmospheric pressure and use heat from the returning fluid to separate the absorbent material from the carrier material. In at least one embodiment, the condenser 256 is capable of condensing a vapor of the absorbent material delivered from the generator vessel 252 to the condenser 256 via a vapor line. The condensed absorbent material is delivered to the evaporation coil 268 through an expansion valve 266.

[0081] In at least one embodiment, the evaporation coil 268 in the evaporation region 258 can be adapted to enable the evaporation of the absorbent material to change the phase of the absorbent material. In at least one embodiment, in a first mode of operation, the fluid returning from at least one computing component, server, or rack in the data center continues to retain some heat after the first heat has been removed in the generator vessel 252. In at least one embodiment, the fluid flows from the generator vessel 252 to the CDU via line 262. In at least one embodiment, the line 272 is a zigzag line (or any suitable heat transfer line or plate) adapted to indirectly contact the fluid in the line with the absorbent material being re-mixed in the absorber vessel 254 and delivered to the generator vessel 252 as part of the absorption cycle. In at least one embodiment, the evaporation coil receives the absorbent material via a pressure valve 266 that maintains a pressure at which the condensed absorbent material can enter the evaporation coil 268. In at least one embodiment, the evaporation coil 268 sprays the condensed absorbent material over a line 278 that has a cooling fluid for other data center personnel cooling needs. In at least one embodiment, the spraying can be performed using perforations in the evaporation coil 268. In at least one embodiment, a second heat in the fluid can remain or be residual in the fluid after the generator vessel 252 and can be cooled by the CDU.

[0082] In at least one embodiment, the vapor of the at least one material from the generator vessel is condensed into a liquid in condenser 256. In at least one embodiment, the condensation results in removal 270 of heat from the absorption material, where the removed heat can be at least some of the first heat absorbed by the fluid that was transferred to the contents of the generator vessel 252 in the first mode of operation of the absorption chiller 250. In at least one embodiment, the removed heat 270 can be blown away or exhausted using an appropriate air cooling system or cooling facility that can be different from the main cooling loop. In at least one embodiment, the absorption material in the form of condensate is transferred via expansion valve 266 to the evaporator region 258 such that the pressure of the absorption material condensate is reduced and such that evaporation of the absorption material condensate can occur. In at least one embodiment, the evaporation of the absorption material in the evaporator region 258 is capable of cooling a different coolant or fluid (other than the data center fluid or working fluid) that can be circulated via fluid line 278 for cooling of personnel areas.

[0083] In at least one embodiment, the evaporation of the absorption material results in movement of the vapor of the absorption material from the evaporator region 258 to the absorber vessel 254. In at least one embodiment, the absorber vessel 254 combines or enables the combination of the phase change absorption material in vapor state (from condensate state) with the recirculated carrier material from the generator vessel 252. In at least one embodiment, the thermodynamic characteristics of the absorber vessel 254 enable the vapor state to be absorbed (or mixed) into the carrier material, such as industrial water that was previously separated in the generator vessel 252. In at least one embodiment, the combination of the absorption material and the carrier material in the absorber vessel 254 results in a mixed solution in concentrated form in the absorber vessel 254.

[0084] In at least one embodiment, the combination of the absorption material and the carrier material in the absorber vessel 254 can result in an exothermic combination and can result in the release of the absorbed heat (from the cooling fluid in line 278) into the environment of the absorber vessel 254. In at least one embodiment, this heat can be removed by air cooling, as in the case where air cooling is applied to remove the heat in the hot air 270 from the condenser 256. In at least one embodiment, the heat can be removed by cooling using a liquid cooling from a cooling facility that is different from the main cooling loop.

[0085] In at least one embodiment, a concentrated form of the mixed solution can be pumped into the generator vessel 252 by pump 264. In at least one embodiment, this represents a cooling cycle that can repeat multiple times for the working fluid to maintain a steady temperature, reduce the temperature of the return fluid, or address any particular temperature requirements in the first mode or second operating mode of the absorption chiller 250. In at least one embodiment, the return fluid leaving the heat recovery system 250 can return to a server tray or cabinet to cool components 220A-D or to a CDU for further cooling, and can be referred to as a recovered fluid.

[0086] In at least one embodiment, in the first operating mode, fluid returning from at least one computing component, server, or rack in a data center can be split into two portions. In at least one embodiment, a first portion passes through the heat recovery system 250, but continues to retain residual heat after a portion of the heat has been removed by the generator vessel 252. In at least one embodiment, a second portion of the fluid bypasses the generator vessel 252 for the CDU. In at least one embodiment, the generator vessel 252 can be adapted to use a portion of the heat from the first portion of the fluid to effect a phase change of an absorption material that was previously part of the fluid in the generator vessel 252. In at least one embodiment, after the portion of the heat from the first portion is removed in the generator vessel 252, the second portion of the fluid is mixed with the first portion of the fluid. In at least one embodiment, this enables the fluid to enter the CDU as part of an auxiliary cooling loop with less total heat than when the fluid first exited (returned) from the at least one computing device, server tray, or rack. In at least one embodiment, the less total heat in the fluid is able to enable a smaller cooling load for the CDU, and thus a smaller cooling load for the primary coolant, primary cooling loop, and chiller facility.

[0087] In at least one embodiment, the second portion of the fluid or the fluid that did not work in the generator vessel 252 flows via a provided line 274 to mix with the first portion of the fluid that was cooled by transferring its heat to the contents of the generator vessel 252. In at least one embodiment, the mixing occurs prior to the combined fluid entering the CDU to at least remove residual heat. In at least one embodiment, the line 276 from the heat recovery system 250 and the line 274 that bypasses the heat recovery system 250 converge at a mixing feature provided by the bifurcated line 274 after the bypass. In at least one embodiment, all of the fluid returning from a computing device, server, or rack is passed to the heat recovery system 250 via the provided line 260 so that the heat exchanger line 272 within the generator vessel 252 is able to transfer heat from the fluid to the contents in the generator vessel 252 at a lower pressure and cause a transition of the absorption material.

[0088] In at least one embodiment, generator vessel 252 can be located proximate to a first split of an auxiliary cooling loop, such as from a server tray or cabinet 202 or from a cooling manifold as shown in Figure 3 In one embodiment, the first split can be a return (or at least a portion thereof) of fluid from at least one computing component 220A;B;C;D to heat recovery system 250. In at least one embodiment, a second split of the auxiliary cooling loop enables a return of fluid (or at least a portion thereof) to a CDU. In at least one embodiment, the first and second splits are associated with a server manifold 204 of a server tray or cabinet 202 or with a cooling manifold of a rack.

[0089] In at least one embodiment, a carrier material and an absorption material can be in a mixed solution in generator vessel 252. In at least one embodiment, the absorption material can be adapted to evaporate, condense, and remix into the mixed solution. In at least one embodiment, the absorption material can be adjusted in this manner based in part on one or more of a temperature of the return fluid, a temperature of the recovered fluid, a temperature at which the absorbent material is at least evaporated, a temperature of components 252-258 of the heat recovery system, a pressure available in the heat recovery system 250, and a carrier material used with the absorption material. In at least one embodiment, the carrier material can be adapted to carry the absorption material between generator vessel 252 and absorber vessel 254.

[0090] In at least one embodiment, the first and second operational modes can be supported by one or more of a plurality of paths as shown in Figure 2 In at least one embodiment, a first path can enable a transfer of fluid to generator vessel 252 to heat contents of the generator vessel at a high pressure. In at least one embodiment, the first path can be enabled at least by lines 260, 272 provided between a computing device, server, or rack and heat recovery system 250. In at least one embodiment, a second path can be capable of transferring a first portion of fluid from the generator vessel to a CDU. In at least one embodiment, the second path can be enabled at least by a line 276 provided between generator vessel 252 and the CDU. In at least one embodiment, a third path can be enabled to transfer a second portion of fluid from the generator vessel to at least one computing component through line 262.

[0091] In at least one embodiment, a rack-level feature 300 as shown in Figure 3 In at least one embodiment, rack-level feature 300 includes a rack 302 with brackets 304, 306 to suspend cooling rack manifolds 314A,B. In at least one embodiment, cooling rack manifolds 314A,B are in fluid communication with a heat recovery system 250 as shown in Figure 3fluid is passed between the server tray or tank 308 and the heat recovery system 324. In at least one embodiment, the inlet and outlet lines 316, 318 are provided on one or either side of the server tray or tank 308 to connect the respective cooling rack manifolds 314A, B to the inlet or outlet side of the server tray or tank 308. In at least one embodiment, different cooling rack manifold 314A, B cooling systems are provided for the inlet and outlet sides of the data center. In at least one embodiment, a single manifold on a single rack 304; 306 can be used with passages therein for both the inlet and outlet sides of the server tray or tank 308 to receive and flow out fluid for cooling the data center or computing components or equipment 320 for the server tray or tank 308. In one embodiment, the data center or computing components or equipment 320 are associated with a cold plate 322 through which the fluid passes.

[0092] In at least one embodiment, fluid enters the rack 302 through the manifold inlet 310, through the inlet cooling rack manifold 314A, through the inlet line 316, through the cold plate 322, through the outlet line 318, through the outlet cooling rack manifold 314B, and through the manifold outlet 312. In at least one embodiment, the cooling rack manifolds 314A, B are associated with a row manifold 358. In at least one embodiment, the row manifold 358 feeds and receives fluid from the top, side, or bottom of the rack manifold 314A, B. In at least one embodiment, a splitter system of one or more flow controllers 310C, 312C can be provided to enable cooling by the heat recovery system 324 or entirely without the aid of the CDU 320; partially with the aid of the CDU 320; or to isolate the heat recovery system 324 and use only the CDU 320 for cooling. In at least one embodiment, the data center cooling system can rely entirely on a loop between the rack 302 and the heat recovery system 324. In at least one embodiment, this can represent a second mode of operation of the heat recovery system 324.

[0093] In at least one embodiment, the data center cooling system can rely entirely on a loop between the rack 302, the heat recovery system 324, and a primary cooling loop 346 supported by an external chiller facility 344. In at least one embodiment, chiller facility, chiller unit, cooling tower, and cooling facility are used to refer to one or more features that can make up part of the primary cooling loop infrastructure. In at least one embodiment, this can represent a first mode of operation. In at least one embodiment, the primary cooling loop can be supplemented by the heat recovery system 324 such that only the residual heat in the fluid is removed by the primary coolant. In at least one embodiment, the primary cooling loop can be supplemented by the heat recovery system 324 such that the residual heat in part of the fluid is removed by the primary coolant along with heat extracted from another part of the fluid, both of which are split from the returning secondary fluid.

[0094] In at least one embodiment, a primary cooling loop (through its associated cooling facility 342) can be used to cool components (e.g., absorber vessel 254 and condenser 256) or cool heat from components of heat recovery system 324. In at least one embodiment, cooling facility 342 for absorber cooler components 254, 256 can be different than cooling facility 344 for primary cooling loop. In at least one embodiment, this can be such that cooling facility 344 of primary cooling loop is not loaded with cooling requirements of secondary coolant from computing components, servers, and racks. In at least one embodiment, a flow splitter system can be supported by branch manifold inlets 310A, B and branch manifold outlets 312A, B that draw fluid out and introduce it into heat recovery system 324, or draw and introduce it into a secondary cooling loop that interfaces with primary cooling loop for supplemental or economizing cooling.

[0095] In at least one embodiment, an inlet path of fluid from heat recovery system 324 to at least one computing component 320 or to a cooling distribution unit (CDU) 326 (CDU 406 in Figure 4 In at least one embodiment, CDU 326 and heat recovery system 324 are located at different locations within a data center than other locations shown in Figure 3 In at least one embodiment, CDU 326 can exchange residual heat in fluid that can be recovered from heat recovery system 324 with primary coolant of primary cooling loop 346 associated with chiller unit 344C, cooling tower 344B, and pump 344B (of cooling facility 344) located outside of a data center. In at least one embodiment, CDU 326 is capable of exchanging residual heat (after heat recovery system 324) and retained heat (not cooled in heat recovery system 324) from a portion of fluid.

[0096] In at least one embodiment, a secondary coolant can be associated with a secondary cooling loop and operable as a fluid. In at least one embodiment, a flow controller 310C, 312C of a flow splitter system that can be associated with a secondary cooling loop can be used to enable secondary coolant to be split from a secondary cooling loop to heat recovery system 324 and enable fluid to be returned to a cooling distribution unit (CDU) 326 or at least one computing component.

[0097] In at least one embodiment, heat recovery system 324 and CDU 326 have (or are associated with) the components shown in the right side 302 exploded view on the right. In at least one embodiment, fluid from at least one component 320 (via an associated cold plate 322), server 308, or rack 302 returns to a row manifold 358 (which is illustrated as one structure with respective channels, but can be multiple manifolds for inlet and outlet of fluid). In at least one embodiment, the fluid has transferred heat. In at least one embodiment, the fluid flows from row manifold 358 to a generator vessel 332 of absorption chiller 324 through a provided line 360. In at least one embodiment, the fluid flows to a burner 340 and can exchange heat with the burner 340 enabling the burner 340 to heat the generator vessel to achieve the reference Figure 2 absorption cycle discussed. In at least one embodiment, the fluid flows from the burner to a CDU 362 instead of the generator vessel 332.

[0098] In at least one embodiment, the burner 340 is used in a supplemental manner, fluid goes directly to the generator vessel 332 and bypasses the burner 340. In at least one embodiment, this enables sufficient heat needed for the absorption chiller cycle to start at the generator vessel 332. In at least one embodiment, the generator vessel 332 receives heat from the fluid. In at least one embodiment, fluid with less heat is transferred to the CDU 326 via a provided line 352. In at least one embodiment, the CDU 326 can include a heat exchanger 330A and at least one associated flow controller 330B. In at least one embodiment, the at least one flow controller 330B can be a pump.

[0099] In at least one embodiment, a primary coolant from a cooling facility 344 can flow through a primary cooling loop 346 to further cool the fluid after the generator vessel 332. In at least one embodiment, residual heat in the fluid after the generator vessel 332 can be removed in the CDU 326. In at least one embodiment, the cooling facility 344 of the primary cooling loop can include a chiller unit 334C, a cooling tower 344B, and at least one associated flow controller 344B. In at least one embodiment, the at least one flow controller 344B can be a pump. In at least one embodiment, the fluid after the CDU 326 flows to the row manifold 358 via a line 348 and back to the rack 302, or to the evaporative area 336 for further cooling via a provided line 348, 368. In at least one embodiment, the fluid after the evaporative area 336 returns to the row manifold 358 through a provided line 350 so that it can be used again with at least one computing component, server, or rack (recycled in the data center).

[0100] In at least one embodiment, the cooling facility 342 associated with the absorption chiller 324 can use liquid cooling to cool the absorber vessel 338 and condenser 334 via different cooling circuits 362. In at least one embodiment, the main cooling circuit 346 can alternatively or simultaneously be used to cool the features or components 334, 338 of the absorption chiller 324. In at least one embodiment, the fluid after the CDU 326 flows to the row manifold 358 via provided lines 348, 366 for recirculation within the data center. In at least one embodiment, when the fluid is coupled to the row manifold 358 via provided lines 348, 366, the cooling achieved in the evaporative area 336 using heat from the fluid can be used to cool the personnel area 356 (or other areas within the data center) via different cooling circuits 364, 368. In at least one embodiment, different refrigerants can be used in the different cooling circuits 364, 368.

[0101] In at least one embodiment, Figure 4 The data center level features 400 shown can be associated with a heat recovery system for a data center cooling system. In at least one embodiment, the data center level features 400 include a heat recovery system 420 within the data center 402. In at least one embodiment, the heat recovery system 420 supports one or more racks 404. In at least one embodiment, the CDU 406 provides for removing excess heat from the fluid and provides further cooling of the recovered fluid. In at least one embodiment, the recovered fluid flows to the inlet of the CDU 406 via a provided line 426, which is shown as being located at the outlet of the heat recovery system 420. In at least one embodiment, the CDU 406 communicates auxiliary coolant between the CDU 406 and the row manifolds or via lines 412, 414 and the row cooling manifolds 410.

[0102] In at least one embodiment, flow controller 424 can be used to remove CDU 406 from the data center cooling system and rely solely on heat recovery system 420. In at least one embodiment, flow controller 424 shuts off CDU 406 from the data center cooling system, CDU 406 can still be operable to cool the recovery fluid received through line 426. In at least one embodiment, CDU 406 can return the cooled fluid through line 428 to heat recovery system 420, which can use its return lines associated with individual racks 404 to provide an alternate secondary cooling loop. In at least one embodiment, the cooled fluid from CDU 406 flows to manifold 410 and is recirculated in the data center. In at least one embodiment, manifold 410 serves racks 404 through lines 416, 418 with secondary coolant that is used as fluid and received in line 426 as recovery fluid and further cooled in CDU 406 to remove residual heat.

[0103] In at least one embodiment, the primary coolant of primary cooling loop 422 travels between CDU 406 and cooling facility 408, which can be external to data center 402 (or data center room). In at least one embodiment, the heat recovery system is adapted to optimize the cooling characteristics of the data center cooling system. In at least one embodiment, when fluid (which can be secondary coolant) leaves the data center or goes to the CDU to exchange heat with the primary cooling loop, it can be at a temperature of approximately 150-168°F. In at least one embodiment, the work required to cool the fluid from this temperature to circulate back to data center 402 is high. In at least one embodiment, external cooler 408 can be at a disadvantage due to this cooling load it is required to perform. In at least one embodiment, the heat recovery system assists the cooling facility or reduces the work required by the cooling fluid. In at least one embodiment, an absorption chiller is located in the secondary cooling loop to reduce the load performed by cooler 408 or to completely replace the primary cooling loop and cooler. In at least one embodiment, a separate cooling facility 430 (with associated features, such as cooling tower and chiller units) can be used differently from cooling facility 408 to cool components of absorption chiller 420 by providing liquid cooling via provided line 432.

[0104] In at least one embodiment, a generator vessel of an absorption chiller receives a return coolant, which can be an auxiliary coolant of an auxiliary cooling loop and can be associated with a cold plate or an immersion cooling server. In at least one embodiment, the generator vessel uses heat from the return coolant to directly or indirectly (through a heat exchanger) heat a combination of an absorption material and a carrier material, separating the absorption material from the carrier material. In at least one embodiment, the absorption material in a vapor phase is passed through a condenser to be cooled to a liquid phase before being evaporated in an evaporator coil to cause cooling in an evaporator coil region. In at least one embodiment, the return coolant passes from the generator vessel, back to the auxiliary cooling loop, and to a CDU for additional cooling. In at least one embodiment, the auxiliary coolant is circulated back to a computing component to extract heat from the computing component. In at least one embodiment, the auxiliary coolant is further cooled in an evaporation region of the absorption chiller before being recirculated to a data center. In at least one embodiment, the absorption material is circulated back to an absorber vessel to mix with a recirculated portion of the carrier material. A strong solution can be formed in the absorber vessel and pumped to remix with the mixed solution in the generator vessel.

[0105] In at least one embodiment, the at least one processor can interface with respective flow controllers discussed in connection with each of Figures 2-4 In at least one embodiment, respective flow controllers can be provided at connections of one or more of the provided lines 348, 350, 366, 364, 368. In at least one embodiment, respective flow controllers can be selected for the provided lines based in part on heat in fluid entering an absorption chiller, leaving a generator vessel, leaving a CDU, or leaving an evaporation region. In at least one embodiment, electronic components of the flow controllers can receive signals from the at least one processor and can cause mechanical reactions to throttle or increase fluid flow through various loops, from and to a CDU, from and to a heat recovery system, through diverging lines for fluid, and at least for the auxiliary cooling loop(s).

[0106] In at least one embodiment, each of the at least one processor has inference and / or training logic 1815, which can include, without limitation, code and / or data storage 1801 to store forward and / or output weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network being trained and / or used for inferencing, in aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1801 to store graph code or other software to control timing and / or sequence of loading weight and / or other parameter information to configure logic, including integer and / or floating point units (collectively, arithmetic logic unit(s) (ALUs)). In at least one embodiment, code such as graph code loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of a neural network that is trained in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or use of aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1801 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache memory or system memory.

[0107] In at least one embodiment, inference and / or training logic 1815 of the at least one processor can be part of a building management system (BMS) to control flow controllers at one or more of a server level, a rack level, and a row level. In at least one embodiment, a determination is made to engage supplemental or economized cooling (or both); or to engage a heat recovery system 420, CDU 406, evaporative coils, or all of these components can provide one or more neural networks of inference and / or training logic 1815 to cause one or more neural networks to infer which flow controller to gracefully engage or disengage. In at least one embodiment, a balance of temperatures and pressures in various zones or vessels of an absorption chiller 420 can be enabled by flow controllers (for gas and liquid phases, as well as expansion valves) controlled by inference and / or training logic 1815.

[0108] In at least one embodiment, one or more neural networks can be trained to reason about previously associated thermal characteristics or cooling requirements from computing devices, servers, or racks and the cooling capacity or performance indicated by heat recovery system 420. In at least one embodiment, previous cooling requirements met by heat recovery system 420 can cause one or more neural networks to make similar inferences about how to meet similar future cooling requirements (taking into account minor variations thereof) by adjusting flow controllers to engage heat recovery system 420 alone or in conjunction with CDUs (and additionally with evaporative zones). In at least one embodiment, similarly, previous cooling requirements met by heat recovery system 420 can cause one or more neural networks to make similar inferences about how to meet similar future cooling requirements (taking into account minor variations thereof) by adjusting flow controllers to engage heat recovery system 420 alone or in conjunction with CDUs (and additionally with evaporative zones). In at least one embodiment, one or more neural networks can determine and send a selection to a flow controller (e.g., to an electronic component associated with the flow controller) to cause the appropriate heat exchanger to be engaged or disengaged.

[0109] Figure 5 According to at least one embodiment, Figures 2-4 Method 500 associated with a data center cooling system. In at least one embodiment, step 502 of method 500 can be providing an absorption chiller having a generator vessel. In at least one embodiment, step 504 of method 500 can be determining that fluid returning from the data center has a heat amount that can be handled by the absorption chiller. In at least one embodiment, the returned heat amount can be within the limits that the absorption chiller can effectively cool. In at least one embodiment, this can be a threshold that at least exceeds a maximum heat amount that enables the generator vessel to convert its contents and have minimal excess heat in the recovered fluid (or not enough heat to require further cooling). In at least one embodiment, the maximum heat amount that can be used for the generator vessel can be based in part on the evaporation temperature of the absorbent material used for the fluid or in the generator vessel at a determined pressure. In at least one embodiment, the excess heat amount can be a temperature value that can be reflected not by reference to the boiling point of water but by reference to the thermal characteristics or cooling requirements of at least one computing device, server tray, or rack.

[0110] In at least one embodiment, step 506 verifies that the heat is also at least sufficient to enable the generator vessel to effectively remove the first heat from the fluid, as described with respect to Figures 2-4discussed. In at least one embodiment, because a heat recovery system can rely on heat from the fluid itself to operate, heat in the fluid must also be high enough for the heat recovery system to work against a determined pressure in the generator vessel, but must also be lower than a maximum heat enabled for the generator vessel.

[0111] In at least one embodiment, step 508 can be performed when all heat (and thus temperature) requirements of the fluid are met. In at least one embodiment, step 508 enables the generator vessel to remove heat from the fluid. In at least one embodiment, the heat removed can not be all of the heat in the fluid. In at least one embodiment, there can be residual heat in the fluid. In at least one embodiment, step 506 can be repeated until heat removal requirements of the heat recovery system are met. In at least one embodiment, further steps can include using a CDU to remove residual heat from the fluid. In at least one embodiment, an evaporative region of an absorption chiller can be used to further cool the fluid after the CDU.

[0112] In at least one embodiment, another sub-step or step of method 500 can be enabling the fluid to be further cooled (e.g., further cooled than at least a portion of heat removed from the generator vessel) in an evaporative region of an absorption chiller. In at least one embodiment, further cooling can be after a CDU. In at least one embodiment, further cooling can be reducing a temperature of the fluid to a lower temperature than when the fluid is first cooled at least one computing component (e.g., via an associated cooling plate). In at least one embodiment, a sub-step of the above-described steps or a step of method 500 includes maintaining the generator vessel at a pressure that can be lower than atmospheric pressure. In at least one embodiment, another sub-step or step of the method can be using heat to enable separation of an absorption material from a carrier material. In at least one embodiment, a further sub-step or step can be enabling a condenser to condense the absorption material. In at least one embodiment, yet another sub-step or step of the method can be enabling an evaporative region to cause a phase change of the absorption material. In at least one embodiment, a further sub-step or step can be combining the phase changed absorption material with recycled carrier material from the generator vessel in an absorber vessel.

[0113] In at least one embodiment, another sub-step or step of method 500 can be to provide a jacket or coil around or inside the generator vessel to enable a fluid to flow around the generator vessel to remove heat from the fluid and use the heat to separate the absorbent material from the carrier material in the generator vessel. In at least one embodiment, the heat can supplement heat provided from a burner used for the generator vessel. In at least one embodiment, a further sub-step or step can be to enable the fluid to be enabled to flow from a heat recovery system to at least one computing component or to an inlet path of a cooling distribution unit (CDU). In at least one embodiment, the CDU can exchange waste heat in the fluid with a primary coolant of a primary cooling loop associated with a chiller located outside of the data center.

[0114] In at least one embodiment, another sub-step or step of method 500 can be to provide a secondary coolant associated with a secondary cooling loop to be operable to be used as the fluid. In at least one embodiment, a further sub-step or step can be to enable the secondary coolant to be shunted from the secondary cooling loop to the heat recovery system. In at least one embodiment, a further sub-step or step can be to enable the fluid to be returned to a cooling distribution unit (CDU) or to at least one computing component. In at least one embodiment, this represents a first and second mode of operation of the heat recovery system.

[0115] In at least one embodiment, another sub-step or step of method 500 can be to position the generator vessel proximate a first shunt of the secondary cooling loop to return the fluid from at least one computing component to the heat recovery system. In at least one embodiment, a further sub-step or step can be to position a second shunt of the secondary cooling loop to enable the fluid to be passed to at least one computing component. In at least one embodiment, a further sub-step or step can be to enable the carrier material and the absorbent material to be in a mixed solution in the generator vessel. In at least one embodiment, a further sub-step or step can be to enable the absorbent material to be evaporated, condensed, and ultimately mixed (or re-mixed) into the mixed solution. In at least one embodiment, a further sub-step or step can enable the carrier material to carry the absorbent material between the generator vessel and the absorber vessel.

[0116] In at least one embodiment, another sub-step or step of method 500 may include providing a mixed solution of carrier material and absorbent material in the generator vessel. In at least one embodiment, a further sub-step or step may include heating the contents of the generator vessel at low pressure using at least heat from the returning auxiliary fluid. In at least one embodiment, a further sub-step or step may include vaporizing the absorbent material in the generator vessel. In at least one embodiment, a further sub-step or step may include condensing the absorbent material in a condenser. In at least one embodiment, a further sub-step or step may include mixing or remixing the absorbent material with the carrier material in the absorber vessel.

[0117] In at least one embodiment, another sub-step or step of the method includes using a first path to transfer fluid to a generator vessel to heat the contents of the generator vessel at low pressure. In at least one embodiment, a further sub-step or step may be using a second path to transfer a first portion of the fluid from the generator vessel to the CDU. In at least one embodiment, a further sub-step or step may be using a third path to transfer a second portion of the fluid from the generator vessel to at least one computing component. In at least one embodiment, the recovered coolant may be sufficiently cooled to remove some more heat from the high-density computing components, but may benefit from further temperature reduction. In at least one embodiment, using two paths to return a portion of the recovered fluid and being able to further cool another portion of the recovered fluid can achieve an overall cooling effect by also reducing the load on the CDU (and therefore, the main cooling loop and cooling facility).

[0118] In at least one embodiment, a further sub-step or step may be determining a first temperature of the fluid returning from the data center and determining a second temperature associated with separation of the absorbent material. In at least one embodiment, a further sub-step or step may be activating an absorption chiller for the fluid when the first temperature is within a threshold of the second temperature, such that the returning fluid may contribute to the efficient operation of the absorption chiller. In at least one embodiment, this information may be used to activate a burner to provide additional heating to the generator vessel. In at least one embodiment, this information may be used to adjust the pressure in the generator vessel to a lower pressure to increase the effectiveness of the heat provided to the contents.

[0119] Servers and Data Centers

[0120] The following figures illustrate, but are not limited to, exemplary network server and data center based systems that may be used to implement at least one embodiment.

[0121] Figure 6A distributed system 600 is shown in accordance with at least one embodiment. In at least one embodiment, the distributed system 600 includes one or more client computing devices 602, 604, 606, and 608 that are configured to execute and operate a client application such as a web browser, a proprietary client, and / or variants thereof. In at least one embodiment, server 612 can be communicatively coupled with remote client computing devices 602, 604, 606, and 608 via network 610.

[0122] In at least one embodiment, server 612 can be adapted to execute one or more software applications or services such as services and applications that can manage session activity for single sign-on (SSO) access across multiple data centers. In at least one embodiment, server 612 can also provide other services or software applications, which can include non-virtual and virtual environments. In at least one embodiment, these services can be provided as web-based services or cloud services or under a software as a service (SaaS) model to users of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, users operating client computing devices 602, 604, 606, and / or 608 can in turn utilize one or more client applications to interact with server 612 to utilize services provided by these components.

[0123] In at least one embodiment, software components 618, 620, and 622 of system 600 are implemented on server 612. In at least one embodiment, one or more components of system 600 and / or services provided by these components can also be implemented by one or more of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, users operating the client computing devices can then utilize one or more client applications to use the services provided by these components. In at least one embodiment, these components can be implemented in hardware, firmware, software, or combinations thereof. It should be appreciated that various Figure 6 The illustrated embodiment is at least one embodiment of a distributed system for implementing an embodiment system and is not intended to be limiting.

[0124] In at least one embodiment, client computing devices 602, 604, 606, and / or 608 can include different types of computing systems. In at least one embodiment, client computing devices can include portable handheld devices (e.g., an iPhone®, cellular smart phone cellular phone, computing tablet, a personal digital assistant (PDA), or a wearable device (e.g., a Google head-mounted displays), running software such as Microsoft Windows ) and / or various mobile operating systems such as iOS, Windows Phone, Android, BlackBerry 10, Palm OS, and / or variations of the foregoing. In at least one embodiment, a device can support different applications such as different Internet-related applications, email, a short message service (SMS) application, and can use various other communications protocols. In at least one embodiment, client computing devices can also include general purpose personal computers including, by way of example, personal computers and / or laptops running various versions of Microsoft Windows, Apple MacOS, and / or Linux operating systems. A client computing device can be equipped with memory hardware such as Apple and / or Linux operating system.

[0125] In at least one embodiment, a client computing device can be a workstation computer running any of a variety of Unix operating systems, including without limitation the varieties of GNU / Linux operating systems such as Google Chrome OS. In at least one embodiment, client computing devices can also include devices that have embedded thereon functionality such as Internet-enabled gaming systems (e.g., Microsoft Xbox with or without Kinect® gesture input device), Internet-enabled cellular telephones (e.g., Apple iPhone, Samsung Galaxy), some embodiments of which do not have many traditional aspects of a computing device (e.g., no keyboard, no mouse), and / or personal messaging devices. Although distributed system 600 in Figure 6 is shown with four client computing devices, any number of client computing devices can be supported. Other devices (e.g., devices with sensors, etc.) can interact with server 612.

[0126] In at least one embodiment, network 610 in distributed system 600 can be any type of network that is capable of supporting data communications using any of a variety of available protocols, including without limitation TCP / IP (transmission control protocol / Internet protocol), SNA (systems network architecture), IPX (Internet packet exchange), AppleTalk, and / or variations thereof. In at least one embodiment, network 610 can be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network, the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a public switched telephone network (PSTN), an infrared network, a wireless network, e.g., a network operating under any of the Institute of Electrical and Electronics (IEEE) 802.11 suite of protocols, Bluetooth®, and / or any other wireless protocol(s), and / or any combination of these and / or other networks. ​

[0127] In at least one embodiment, server 612 can be comprised of one or more general purpose computers, specialized server computers (including, in at least one embodiment, PC (personal computer) servers, UNIX® servers, mid-range servers, mainframe computers, rack-mounted servers, etc.), server farms, server clusters, or any other appropriate arrangement and / or combination. In at least one embodiment, server 612 can include one or more virtual machines running virtual operating systems, or other computing architectures involving virtualization. In at least one embodiment, one or more pools of flexible logical storage devices can be virtualized for use by servers to maintain virtual storage devices. In at least one embodiment, virtual networks can be controlled by server 612 using software-defined networking. In at least one embodiment, server 612 can be adapted to run one or more services or software applications.

[0128] In at least one embodiment, server 612 can run any operating system, and any commercially available server operating system. In at least one embodiment, server 612 can also run any of a variety of additional server applications and / or mid-tier applications, including HTTP (HyperText Transfer Protocol) servers, FTP (File Transfer Protocol) servers, CGI (Common Gateway Interface) servers, JAVA® servers, database servers, and / or variations thereof. In at least one embodiment, example database servers include, but are not limited to, those available from Oracle, Microsoft, Sybase, IBM (International Business Machines) and / or variations thereof.

[0129] In at least one embodiment, server 612 can include one or more applications for analyzing and consolidating data feeds and / or event updates received from users of client computing devices 602, 604, 606, and 608. In at least one embodiment, data feeds and / or event updates can include, but are not limited to, data feeds and / or event updates received from one or more third party information sources and continuous data streams, which can include real-time events. In at least one embodiment, these sources include, but are not limited to, financial feeds, updates, or real-time updates that can include real-time events related to sensor data applications, financial quotes, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automobile traffic monitoring, and / or variations thereof. In at least one embodiment, server 612 can also include one or more applications for displaying the data feeds and / or real-time events via one or more display devices of client computing devices 602, 604, 606, and 608.

[0130] ​In at least one embodiment, distributed system 600 can also include one or more databases 614 and 616. In at least one embodiment, databases can provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 614 and 616 can reside in various locations. In at least one embodiment, one or more of databases 614 and 616 can reside on a non-transitory storage medium local to (and / or in) server 612. In at least one embodiment, databases 614 and 616 can be remote from server 612 and in communication with server 612 via a network-based or dedicated connection. In at least one embodiment, databases 614 and 616 can reside in a storage area network (SAN). In at least one embodiment, any necessary files for performing functions attributed to server 612 can be appropriately either locally stored on server 612 and / or remotely stored. In at least one embodiment, databases 614 and 616 can comprise a relational database such as one adapted to store, update, and retrieve data in response to SQL-formatted commands.

[0131] Figure 7 An example data center 700 is shown in accordance with at least one embodiment. In at least one embodiment, data center 700 includes, without limitation, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0132] In at least one embodiment, as shown Figure 7 In at least one embodiment, data center infrastructure layer 710 can include a resource orchestrator 712, grouped computing resources 714, and node computing resources (“node C.R.s”) 716(1)-716(N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s 716(1)-716(N) can include, without limitation, any number of central processing units (“CPUs” or “processors”) or other processors (including accelerators, field programmable gate arrays (“FPGAs”), graphics processors, etc.), memory devices (e.g., dynamic random access memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, cooling modules, etc. In at least one embodiment, one or more of node C.R.s 716(1)-716(N) can be a server having one or more of the above computing resources.

[0133] In at least one embodiment, grouped computing resources 714 can include individual groupings of node C.R.s housed within one or more racks (not shown), or housed within a number of racks (also not shown) within data centers at various geographic locations. Individual groupings of node C.R.s within grouped computing resources 714 can include grouped computing, network, memory, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors can be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches in any combination.

[0134] In at least one embodiment, resource orchestrator 712 can configure or otherwise control one or more node C.R.s 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource orchestrator 712 can include a software design infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource orchestrator 712 can include hardware, software, or some combination thereof.

[0135] In at least one embodiment, as Figure 7As shown, framework layer 720 includes, without limitation, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, framework layer 720 can include a framework that supports software 752 of software layer 730 and / or one or more applications 742 of application layer 740. In at least one embodiment, software 752 or applications 742 can include, respectively, web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 can be, without limitation, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that can utilize distributed file system 738 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 732 can include a Spark driver to facilitate scheduling workloads supported by various layers of data center 700. In at least one embodiment, configuration manager 734 can be capable of configuring different layers, such as software layer 730 and framework layer 720 including Spark and distributed file system 738 for supporting large-scale data processing. In at least one embodiment, resource manager 736 can be capable of managing clustered or grouped computing resources mapped to or allocated for supporting distributed file system 738 and job scheduler 732. In at least one embodiment, clustered or grouped computing resources can include grouped computing resources 714 on data center infrastructure layer 710. In at least one embodiment, resource manager 736 can coordinate with resource orchestrator 712 to manage these mapped or allocated computing resources.

[0136] In at least one embodiment, software 752 included in software layer 730 can include software used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of software can include, without limitation, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0137] In at least one embodiment, one or more applications 742 included in application layer 740 can include one or more types of applications used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of applications can include, without limitation, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variations thereof.

[0138] In at least one embodiment, any of configuration manager 734, resource manager 736, and resource orchestrator 712 can implement any number and type of self-modifying actions based on any number and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions can relieve data center operators of data center 700 from making possibly poor configuration decisions and can avoid underutilization and / or poor-performing portions of a data center.

[0139] Figure 8 A client-server network 804 formed of a plurality of network server computers 802 interconnected is shown, according to at least one embodiment. In at least one embodiment, each network server computer 802 stores data accessible by other network server computers 802 and client computers 806 and networks 808 linked to a wide area network 804. In at least one embodiment, a configuration of client-server network 804 can change over time as client computers 806 and one or more networks 808 connect and disconnect with network 804, and as one or more backbone server computers 802 are added to or removed from network 804. In at least one embodiment, a client-server network includes client computers 806 and networks 808 when they are connected with network server computers 802. In at least one embodiment, the term computer includes any device or machine that is capable of accepting data, applying prescribed processes to data, and providing results of processes.

[0140] In at least one embodiment, client-server network 804 stores information accessible to web server computers 802, remote network 808, and client computers 806. In at least one embodiment, web server computers 802 are formed from mainframe computers, minicomputers, and / or microcomputers each having one or more processors. In at least one embodiment, server computers 802 are linked together through wired and / or wireless transmission media, such as wire, fiber optic cable, and / or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media. In at least one embodiment, client computers 806 access web server computers 802 through similar wired or wireless transmission media. In at least one embodiment, client computers 806 can link into client-server network 804 using modems and standard telephone communication networks. In at least one embodiment, alternative carrier systems, such as cable and satellite communication systems, can also be used to link into client-server network 804. In at least one embodiment, other private or time-shared carrier systems can be used. In at least one embodiment, network 804 is a global information network, such as the Internet. In at least one embodiment, network is a private intranet using similar protocols as the Internet but with added security measures and restricted access controls. In at least one embodiment, network 804 is a private or semi-private network using proprietary communication protocols.

[0141] In at least one embodiment, client computers 806 are any end-user computers, and can also be mainframe computers, minicomputers, or microcomputers having one or more microprocessors. In at least one embodiment, server computers 802 can sometimes act as client computers accessing another server computer 802. In at least one embodiment, remote network 808 can be a local area network, a network added to a wide area network through an independent service provider (ISP) for the Internet, or another group of computers interconnected by wired or wireless transmission media having a fixed or changing configuration over time. In at least one embodiment, client computers 806 can link into and access network 804 independently or through remote network 808.

[0142] Figure 9A computer network 908 connecting one or more computer machines is shown in accordance with at least one embodiment. In at least one embodiment, network 908 can be any type of electrically connected computer group, including, for example, the following networks: the Internet, an intranet, a local area network (LAN), a wide area network (WAN), or an interconnected combination of these network types. In at least one embodiment, connections within network 908 can be a remote modem, Ethernet (IEEE 802.3), Token Ring (IEEE 802.5), Fiber Distributed Datalink Interface (FDDI), Asynchronous Transfer Mode (ATM), or any other communications protocol. In at least one embodiment, computing devices linked to network can be desktops, servers, portable, handheld, set-top, personal digital assistants (PDAs), terminals, or any other desired type or configuration. In at least one embodiment, network-connected devices can vary widely in processing power, internal memory, and other performance depending on their functionality.

[0143] In at least one embodiment, communications within network and to or from computing devices connected to network can be wired or wireless. In at least one embodiment, network 908 can include, at least in part, the world-wide public Internet, which typically connects multiple users according to a client-server model according to Transmission Control Protocol / Internet Protocol (TCP / IP) specifications. In at least one embodiment, a client-server network is a dominant model for communication between two computers. In at least one embodiment, a client computer (“client”) issues one or more commands to a server computer (“server”). In at least one embodiment, a server fulfills client commands by accessing available network resources and returning information to a client according to client commands. In at least one embodiment, client computer systems and network resources residing on network servers are assigned network addresses for identification during communications between elements of a network. In at least one embodiment, communications from other network-connected systems to a server will include a network address of a relevant server / network resource as part of a communication, so that an appropriate destination for data / requests is identified as a recipient. In at least one embodiment, when network 908 includes the global Internet, network addresses are IP addresses in TCP / IP format, which can route data, at least in part, to an email account, website, or other Internet tool residing on a server. In at least one embodiment, information and services residing on network servers can be available to web browsers of client computers through a domain name (e.g., www.site.com), which maps to an IP address of a network server.

[0144] In at least one embodiment, multiple clients 902, 904, and 906 connect to network 908 via corresponding communication links. In at least one embodiment, each of these clients can access network 908 via any desired form of communication, such as via a dial-up modem connection, cable link, digital subscriber line (DSL), wireless or satellite link, or any other form of communication. In at least one embodiment, each client can communicate using any machine compatible with network 908 (e.g., a personal computer (PC), a workstation, a dedicated terminal, a personal data assistant (PDA), or other similar device). In at least one embodiment, clients 902, 904, and 906 can or can not be located in the same geographic region.

[0145] In at least one embodiment, multiple servers 910, 912, and 914 are connected to network 918 to serve clients in communication with network 918. In at least one embodiment, each server is typically a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, servers include computer-readable data storage media, such as hard drive and RAM memory, that store program instructions and data. In at least one embodiment, servers 910, 912, 914 run application programs in response to client commands. In at least one embodiment, server 910 can run a web server application for responding to client requests for HTML pages, and can also run a mail server application for receiving and routing electronic mail. In at least one embodiment, other application programs can also run on server 910, such as an FTP server or media server for streaming audio / video data to clients. In at least one embodiment, different servers can be dedicated to performing different tasks. In at least one embodiment, server 910 can be a dedicated web server that manages resources related to a website for different users, while server 912 can be dedicated to providing electronic mail (email) management. In at least one embodiment, other servers can be dedicated to media (audio, video, etc.), file transfer protocol (FTP), or a combination of any two or more services typically available or provided over a network. In at least one embodiment, each server can be in the same or different location as other servers. In at least one embodiment, there can be multiple servers performing mirror tasks for users, thereby relieving congestion or minimizing traffic directed to and from a single server. In at least one embodiment, servers 910, 912, 914 are under the control of a web hosting provider that maintains and delivers third-party content over network 918.

[0146] In at least one embodiment, a web hosting provider delivers services to two different types of clients. In at least one embodiment, one type, which may be referred to as a browser, requests content from servers 910, 912, 914, such as web pages, email messages, video clips, etc. In at least one embodiment, a second type, which may be referred to as a user, hires the web hosting provider to maintain network resources (such as a website) and make them available to the browser. In at least one embodiment, the user contracts with the web hosting provider to make available the memory space, processor capacity, and communication bandwidth required for the network resources they desire, depending on the amount of server resources they desire to utilize.

[0147] In at least one embodiment, in order for the web hosting provider to serve both clients, an application that manages the network resources hosted by the server must be appropriately configured. In at least one embodiment, the program configuration process involves defining a set of parameters that at least partially control the application's responses to browser requests and also at least partially define the server resources available to a particular user.

[0148] In one embodiment, intranet server 916 communicates with network 908 via a communication link. In at least one embodiment, intranet server 916 communicates with server manager 918. In at least one embodiment, server manager 918 includes a database of application configuration parameters used in servers 910, 912, 914. In at least one embodiment, a user modifies database 920 via intranet 916, and server manager 918 interacts with servers 910, 912, 914 to modify application parameters so that they match the contents of the database. In at least one embodiment, a user logs into intranet 916 by connecting to intranet 916 via computer 902 and entering authentication information such as a username and password.

[0149] In at least one embodiment, when a user wishes to log in to a new service or modify an existing service, the intranet server 916 authenticates the user and provides the user with an interactive screen display / control panel that allows the user to access configuration parameters for a particular application. In at least one embodiment, the user is presented with a number of modifiable text boxes that describe aspects of the user's website or other network resource's configuration. In at least one embodiment, if the user desires to increase the amount of memory space reserved on the server for their website, the user is provided with a field in which the user specifies the desired amount of memory space. In at least one embodiment, in response to receiving this information, the intranet server 916 updates the database 920. In at least one embodiment, the server manager 918 forwards this information to the appropriate server, and the new parameters are used during operation of the application. In at least one embodiment, the intranet server 916 is configured to provide the user with access to configuration parameters for a hosted network resource (e.g., web page, email, FTP site, media site, etc.) that the user has contracted with a web hosting service provider.

[0150] Figure 10A A networked computer system 1000A is shown, in accordance with at least one embodiment. In at least one embodiment, the networked computer system 1000A includes a plurality of nodes or personal computers ("PCs") 1002, 1018, 1020. In at least one embodiment, the personal computers or nodes 1002 include a processor 1014, a memory 1016, a video camera 1004, a microphone 1006, a mouse 1008, a speaker 1010, and a monitor 1012. In at least one embodiment, the PCs 1002, 1018, 1020 can each run one or more desktop servers for an internal network within a given company, or can be servers for a general-purpose network that is not limited to a particular environment. In at least one embodiment, there is one server per PC node of the network, such that each PC node of the network represents a particular network server with a particular network URL address. In at least one embodiment, each server has a default web page for the user of that server by default, which default web page can itself contain embedded URLs pointing to further sub-pages of that user on that server, or to other servers on the network or pages on other servers.

[0151] In at least one embodiment, nodes 1002, 1018, 1020, and other nodes of network are interconnected by a medium 1022. In at least one embodiment, medium 1022 can be a communication channel such as an Integrated Services Digital Network (“ISDN”). In at least one embodiment, various nodes of a networked computer system can be connected by various communication media, including a Local Area Network (“LAN”), a Plain Old Telephone Line (“POTS”) (sometimes referred to as a Public Switched Telephone Network (“PSTN”)), and / or variations thereof. In at least one embodiment, various nodes of a network can also constitute computer system users interconnected via a network such as the Internet. In at least one embodiment, each server on a network (running from a particular node of a network at a given instance) has a unique address or identification within a network, which can be specified according to a URL.

[0152] In at least one embodiment, multiple Multipoint Conference Units (“MCUs”) can thus be used to transmit data to and from various nodes or “endpoints” of a conferencing system. In at least one embodiment, nodes and / or MCUs can be interconnected via ISDN links or through a Local Area Network (“LAN”), in addition to various other communication media, such as nodes connected through the Internet. In at least one embodiment, nodes of a conferencing system can typically be connected either directly to a communication medium such as a LAN or through an MCU, and a conferencing system can include other nodes or elements such as routers, servers, and / or variations thereof.

[0153] In at least one embodiment, processor 1014 is a general-purpose programmable processor. In at least one embodiment, a processor of a node of networked computer system 1000A can also be a special-purpose video processor. In at least one embodiment, different peripheral devices and components of a node, such as those of node 1002, can differ from those of other nodes. In at least one embodiment, node 1018 and node 1020 can be configured the same as or differently from node 1002. In at least one embodiment, in addition to a PC system, a node can be implemented on any suitable computer system.

[0154] Figure 10BA networked computer system 1000B is shown in accordance with at least one embodiment. In at least one embodiment, system 1000B shows a network, such as LAN 1024, which can be used to interconnect various nodes that can communicate with each other. In at least one embodiment, attached to LAN 1024 are a number of nodes, such as PC nodes 1026, 1028, 1030. In at least one embodiment, nodes can also connect to the LAN via a web server or other device. In at least one embodiment, system 1000B includes other types of nodes or elements, including routers, servers, and nodes for at least one embodiment.

[0155] Figure 10C A networked computer system 1000C is shown in accordance with at least one embodiment. In at least one embodiment, system 1000C shows a WWW system with communication across a backbone communication network, such as Internet 1032, which can be used to interconnect various nodes of a network. In at least one embodiment, the WWW is a set of protocols that operate on top of the Internet, and allows graphical interface systems to operate on it in order to access information over the Internet. In at least one embodiment, attached to Internet 1032 in the WWW are a number of nodes, such as PCs 1040, 1042, 1044. In at least one embodiment, nodes interface with other nodes of the WWW through WWW HTTP servers, such as servers 1034, 1036. In at least one embodiment, PC 1044 can be a PC that forms a node of network 1032, and PC 1044 itself runs its server 1036, although PC 1044 and server 1036 are shown separately in Figure 10C for purposes of illustration.

[0156] In at least one embodiment, the WWW is a distributed type of application, characterized by WWW HTTP, the protocol of the WWW, which operates on top of the Internet's Transmission Control Protocol / Internet Protocol ("TCP / IP"). In at least one embodiment, the WWW can thus be characterized by a set of protocols (i.e., HTTP) that operate on the Internet as its "backbone."

[0157] In at least one embodiment, a web browser is an application running on a node of a network in a network system of the WWW type that allows a user of a particular server or node to view such information and thus allows the user to search through graphical and text-based files linked together using hypertext links embedded in documents or files available from servers on a network that understand HTTP. In at least one embodiment, when a user uses another server on a network such as the Internet to retrieve a given web page of a first server associated with a first node, the retrieved document can have different hypertext links embedded in it, and a local copy of the page is created locally at the retrieval user's machine. In at least one embodiment, when the user clicks on a hypertext link, the locally stored information related to the selected hypertext link is typically sufficient to allow the user's machine to open a connection through the Internet to the server indicated by the hypertext link.

[0158] In at least one embodiment, more than one user can be coupled to each HTTP server through a LAN such as LAN 1038, such as shown with respect to WWW HTTP server 1034. In at least one embodiment, system 1000C can also include other types of nodes or elements. In at least one embodiment, a WWW HTTP server is an application running on a machine such as a PC. In at least one embodiment, each user can be considered to have a unique "server" as shown with respect to PC 1044. In at least one embodiment, a server can be considered to be a server such as WWW HTTP server 1034 that provides access to a network for a LAN or multiple nodes or multiple LANs. In at least one embodiment, there are multiple users, each with a desktop PC or node of a network, each desktop PC potentially setting up a server for its user. In at least one embodiment, each server is associated with a particular network address or URL that, when accessed, provides a default web page for that user. In at least one embodiment, the web page can contain further links (embedded URLs) that point to further sub-pages of that user on that server, or to other servers on the network or to pages on other servers on the network.

[0159] Cloud computing and services

[0160] The following figures set forth, but are not limited to, exemplary cloud-based systems that can be used to implement at least one embodiment.

[0161] In at least one embodiment, cloud computing is a style of computing in which dynamically scalable and often virtualized resources are provided as a service over the Internet. In at least one embodiment, users do not need to have knowledge, understanding or control over the technology infrastructure in the “cloud” that supports them, the specialized knowledge of the technology infrastructure, or control over the technology infrastructure, which can be referred to as “in the cloud.” In at least one embodiment, cloud computing converges infrastructure, platform and software as a service offering common themes that depend on the internet to meet the computing needs of users. In at least one embodiment, a typical cloud deployment, such as in a private cloud (e.g., enterprise network) or data center (DC) in a public cloud (e.g., the Internet) can consist of thousands of servers (or alternatively, VMs), hundreds of Ethernet, Fibre Channel or Fibre Channel over Ethernet (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, a cloud can also consist of network services infrastructure, such as IPsec VPN hubs, firewalls, load balancers, Wide Area Network (WAN) optimizers, etc. In at least one embodiment, remote subscribers can securely access cloud applications and services by connecting via a VPN tunnel, such as an IPsec VPN tunnel.

[0162] In at least one embodiment, cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction.

[0163] In at least one embodiment, cloud computing is characterized by on-demand self-service, wherein consumers can unilaterally provision computing capabilities, such as server time and network storage, as needed automatically (without requiring human interaction with each service provider). In at least one embodiment, cloud computing is characterized by broad network access, wherein capabilities are available over the network and accessed through standard mechanisms that promote the use of heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by resource pooling, wherein the provider’s computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to consumer demand. In at least one embodiment, there is a sense of location independence, as consumers generally do not have control or knowledge of the exact location of the provided resources, but can be able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0164] In at least one embodiment, resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by rapid elasticity, in which capability can be rapidly and elastically provisioned (in some cases automatically), in some cases with little or no management effort or interaction with provider. In at least one embodiment, cloud computing is characterized by pay-per-use billing in which users are only billed for the capacity that they actually use — contributing to what is often a substantial cost savings for users. In at least one embodiment, cloud computing is characterized by measured service, in which cloud systems automatically control and optimize resource use by leveraging a metering capability at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). In at least one embodiment, resource usage can be monitored, controlled, and reported providing transparency for both the provider and consumer of the service.

[0165] In at least one embodiment, cloud computing can be associated with various services. In at least one embodiment, cloud Software as a Service (SaaS) can refer to a paradigm in which the providing of an application is delivered to a consumer on a cloud infrastructure. In at least one embodiment, the application is accessible from various client devices through a thin client interface such as a web browser (e.g., web-based e-mail). In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0166] In at least one embodiment, cloud Platform as a Service (PaaS) can refer to a paradigm in which the providing of a platform is delivered by the provider. The platform can be comprised of tools, libraries and infrastructure that support the development and execution of applications. In at least one embodiment, consumer developers can develop, test, deploy, and / or serve their created applications using programming languages and tools supported by the provider. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly application hosting environment configurations.

[0167] In at least one embodiment, cloud Infrastructure as a Service (IaaS) can refer to a paradigm in which the providing of infrastructure is delivered by the provider. The infrastructure can be comprised of computer servers that a consumer can program or control. In at least one embodiment, the consumer does not manage or control or does not have direct control over the underlying cloud infrastructure including networks, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited, well-defined customer-specific application configurations.

[0168] In at least one embodiment, cloud computing provides a convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and client data, etc.) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service. In at least one embodiment, this cloud resource can include tools delivered as a service to users that allow for the creation of a custom operating system, applications, or specific

[0169] Figure 11 One or more components of a system environment 1100, in accordance with one or more embodiments, are shown in which services can be provided as third party network services. In at least one embodiment, a third party network can be referred to as a cloud, a cloud network, a cloud computing network, and / or variations thereof. In at least one embodiment, system environment 1100 includes one or more client computing devices 1104, 1106, and 1108, which can be used by users to interact with a third party network infrastructure system 1102 that provides third party network services, which can be referred to as cloud computing services. In at least one embodiment, third party network infrastructure system 1102 can include one or more computers and / or servers.

[0170] It is to be appreciated that the third party network infrastructure system 1102 depicted in Figure 11 In at least one embodiment, the third party network infrastructure system 1102 depicted in Figure 11 In at least one embodiment, an embodiment of a third party network infrastructure system is depicted. In at least one embodiment, third party network infrastructure system 1102 can have more or fewer components than those depicted in Figure 11 In at least one embodiment, the third party network infrastructure system 1102 depicted in

[0171] In at least one embodiment, client computing devices 1104, 1106, and 1108 can be configured to operate a client application such as a web browser that can be used by users of client computing devices to interact with third party network infrastructure system 1102 to use services provided by third party network infrastructure system 1102. Although example system environment 1100 is illustrated as having three client computing devices, any number of client computing devices can be supported. In at least one embodiment, other devices such as devices with sensors, etc. can interact with third party network infrastructure system 1102. In at least one embodiment, one or more networks 1110 can facilitate communications and exchange of data between client computing devices 1104, 1106, and 1108 and third party network infrastructure system 1102.

[0172] In at least one embodiment, services provided by third party network infrastructure system 1102 can include hosting of services available on demand to users of third party network infrastructure system. In at least one embodiment, various services can also be provided including, but not limited to, online data storage and backup solutions, Web-based electronic mail services, managed office suites and document collaboration services, database management and processing, managed technical support services, and / or variations thereof. In at least one embodiment, services provided by a third party network infrastructure system can dynamically scale to meet the needs of its users.

[0173] In at least one embodiment, a particular instantiation of a service provided by third party network infrastructure system 1102 can be referred to as a “service instance.” In at least one embodiment, generally, any service available to a user from a third party network service provider system via a communications network, such as the Internet, is referred to as a “third party network service.” In at least one embodiment, in a public third party network environment, servers and systems that make up the third party network service provider system are distinct from a customer’s on-premise servers and systems. In at least one embodiment, a third party network service provider system can host an application and users can order and utilize the application on-demand via a communications network, such as the Internet.

[0174] In at least one embodiment, a service in a computer network third party network infrastructure can include protected computer network access to storage, hosted databases, hosted network servers, software applications, or other services provided to a user by a third party network vendor. In at least one embodiment, a service can include password protected access to remote storage on a third party network over the Internet. In at least one embodiment, a service can include a network service based hosted relational database and scripting language middleware engine for private use by a networked developer. In at least one embodiment, a service can include access to an email software application hosted on a website of a third party network vendor.

[0175] In at least one embodiment, third party network infrastructure system 1102 can include a suite of applications, middleware, and database service offerings that are delivered to customers in a self-service, subscription-based, elastically scalable, reliable, highly available, and secure manner. In at least one embodiment, third party network infrastructure system 1102 can also provide “big data” related computing and analytics services. In at least one embodiment, the term “big data” is commonly used to refer to extremely large data sets that can be stored and manipulated by analysts and researchers to visualize large amounts of data, detect trends, and / or otherwise interact with the data. In at least one embodiment, big data and related applications can be hosted and / or manipulated by infrastructure system at many levels and at different scales. In at least one embodiment, tens, hundreds, or thousands of processors linked in parallel can act on such data to present the data or simulate an outside force on the data or what it represents. In at least one embodiment, these data sets can involve structured data (such as structured data in a database or otherwise organized according to a structured model) and / or unstructured data (e.g., emails, images, data blobs (binary large objects), web pages, complex event processing). In at least one embodiment, by leveraging capabilities of embodiments to relatively quickly focus more (or less) computing resources on a target, third party network infrastructure system can be better used to perform tasks on big data sets based on demand from businesses, government agencies, research organizations, private individuals, groups of like-minded individuals or organizations, or other entities.

[0176] In at least one embodiment, third party network infrastructure system 1102 can be adapted to automatically provide, manage and track customer subscriptions for services provided by third party network infrastructure system 1102. In at least one embodiment, third party network infrastructure system 1102 can provide third party network services via different deployment models. In at least one embodiment, services can be provided under a public third party network model in which third party network infrastructure system 1102 is owned by an organization that sells third party network services and makes services available to the general public or different industry enterprises. In at least one embodiment, services can be provided under a private third party network model in which third party network infrastructure system 1102 operates for a single organization and can provide services for one or more entities within the organization. In at least one embodiment, third party network services can also be provided under a community third party network model in which third party network infrastructure system 1102 and the services provided by third party network infrastructure system 1102 are shared by several organizations in a related community. In at least one embodiment, third party network services can also be provided under a hybrid third party network model, which is a combination of two or more different models.

[0177] In at least one embodiment, services provided by third party network infrastructure system 1102 can include one or more services provided under a Software as a Service (SaaS) category, a Platform as a Service (PaaS) category, an Infrastructure as a Service (IaaS) category, or other categories of services including hybrid services. In at least one embodiment, a customer can order one or more services provided by third party network infrastructure system 1102 via a subscription order. In at least one embodiment, third party network infrastructure system 1102 then performs processing to provide services in customer’s subscription order.

[0178] In at least one embodiment, services provided by third party network infrastructure systems 1102 can include, without limitation, application services, platform services, and infrastructure services. In at least one embodiment, application services can be provided by third party network infrastructure systems via a SaaS platform. In at least one embodiment, a SaaS platform can be configured to provide third party network services that fall into the SaaS category. In at least one embodiment, a SaaS platform can provide the capability for customers to use applications, running on third party network infrastructure systems, that are built using an integrated development and deployment platform. In at least one embodiment, a SaaS platform can manage and control underlying software and infrastructure for providing the SaaS services. In at least one embodiment, by utilizing the services provided by a SaaS platform, customers can no longer have to worry about acquiring and managing the underlying hardware and software. In at least one embodiment, customers can obtain an application service without the need for customers to purchase, install, and manage software or hardware. In at least one embodiment, various different SaaS services can be provided. In at least one embodiment, this can include, without limitation, services for sales performance management, enterprise integration, and business flexibility that provide solutions for managing sales, aligning sales with customers, and improving business responsiveness, respectively.

[0179] In at least one embodiment, platform services can be provided by third party network infrastructure systems 1102 via a PaaS platform. In at least one embodiment, a PaaS platform can be configured to provide third party network services that fall into the PaaS category. In at least one embodiment, platform services can include, without limitation, services enabling organizations to combine existing applications with new applications built using the shared services provided by the platform, as well as the ability to establish new applications that leverage the shared services provided by the platform. In at least one embodiment, a PaaS platform can manage and control the underlying software and infrastructure for providing the PaaS services. In at least one embodiment, customers can obtain PaaS services provided by third party network infrastructure systems 1102 without the need for customers to purchase, install, and manage the underlying hardware and software.

[0180] In at least one embodiment, by utilizing the services provided by a PaaS platform, customers can use programming languages and tools supported by the third party network infrastructure system and also control deployed services. In at least one embodiment, platform services provided by a third party network infrastructure system can include database third party network services, middleware third party network services, and third party network services. In at least one embodiment, database third party network services can support a shared services deployment model that enables organizations to pool database resources and offer customers database as a service in the form of a database third party network. In at least one embodiment, middleware third party network services can provide customers with a platform for developing and deploying various business applications, and third party network services can provide customers with a platform to deploy applications in a third party network infrastructure system.

[0181] In at least one embodiment, various different infrastructure services can be provided by an IaaS platform in third party network infrastructure system. In at least one embodiment, infrastructure services facilitate the management and control of underlying computing resources, such as storage, networks, and other fundamental computing resources for customers utilizing services provided by SaaS and PaaS platforms.

[0182] In at least one embodiment, third party network infrastructure system 1102 can also include infrastructure resources 1130 for providing resources used to provide various services to customers of third party network infrastructure system. In at least one embodiment, infrastructure resources 1130 can include pre-integrated and optimized combinations of hardware, such as, for example, servers, storage, and networking resources, for

[0183] In at least one embodiment, resources in third party network infrastructure system 1102 can be shared by multiple users and dynamically re-allocated per demand. In at least one embodiment, resources can be allocated to users in different time zones. In at least one embodiment, third party network infrastructure system 1102 can enable a first set of users in a first time zone to utilize resources of third party network infrastructure system for a specified number of hours and subsequently enable reallocation of same resources to another set of users located in a different time zone, thereby maximizing resource utilization.

[0184] In at least one embodiment, a number of internal shared services 1132 can be provided that are shared by different components or modules of third party network infrastructure system 1102 for enabling services provided by third party network infrastructure system 1102. In at least one embodiment, these internal shared services can include, but are not limited to, security and identity services, integration services, enterprise repository services, enterprise manager services, virus scanning and white list services, high availability, backup and recovery services, services for enabling third party network support, email services, notification services, file transfer services, and / or variations thereof.

[0185] In at least one embodiment, third party network infrastructure system 1102 can provide comprehensive management of third party network services (e.g., SaaS, PaaS, and IaaS services) in third party network infrastructure system. In at least one embodiment, third party network management functionality can include the ability to provision, manage and track subscriptions of customers received by third party network infrastructure system 1102, and / or variations thereof.

[0186] In at least one embodiment, as Figure 11As shown, the third party network management functionality can be provided by one or more modules, such as an order management module 1120, an order coordination module 1122, an order provisioning module 1124, an order management and monitoring module 1126, and an identity management module 1128. In at least one embodiment, these modules can include or use one or more computers and / or servers, which can be general purpose computers, special purpose server computers, server farms, server clusters, or any other appropriate arrangement and / or combination.

[0187] In at least one embodiment, at step 1134, a customer using a client device, such as client computing device 1104, 1106, or 1108, can interact with the third party network infrastructure system 1102 by requesting and placing an order for one or more services provided by the third party network infrastructure system 1102 and a subscription to one or more services provided by the third party network infrastructure system 1102. In at least one embodiment, the customer can access a third party network user interface (UI), such as third party network UI 1112, third party network UI 1114, and / or third party network UI 1116, and place the order for subscription via these UIs. In at least one embodiment, order information received by the third party network infrastructure system 1102 in response to the customer placing the order can include information identifying the customer and one or more services provided by the third party network infrastructure system 1102 that the customer wants to subscribe to.

[0188] In at least one embodiment, at step 1136, the order information received from the customer can be stored in an order database 1118. In at least one embodiment, if this is a new order, a new record can be created for the order. In at least one embodiment, the order database 1118 can be one of several databases operated by the third party network infrastructure system 1118 and in conjunction with other system elements.

[0189] In at least one embodiment, at step 1138, the order information can be forwarded to an order management module 1120, which can be configured to perform billing and accounting functions related to the order, such as validating the order, and, upon validation, provisioning an order.

[0190] In at least one embodiment, at step 1140, information about the order can be transmitted to an order coordination module 1122, which is configured to coordinate the provisioning of services and resources for orders placed by customers. In at least one embodiment, the order coordination module 1122 can use the services of an order provisioning module 1124 for provisioning. In at least one embodiment, the order coordination module 1122 enables management of business processes associated with each order and applies business logic to determine whether an order should continue to be provisioned.

[0191] In at least one embodiment, at step 1142, upon receiving a new subscribed order, the order coordination module 1122 sends a request to the order provisioning module 1124 to allocate resources and configure resources needed to fulfill the subscribed order. In at least one embodiment, the order provisioning module 1124 implements resource allocation for services ordered by customers. In at least one embodiment, the order provisioning module 1124 provides a level of abstraction between third-party network services offered by the third-party network infrastructure system 1100 and physical implementation layers for resources to be applied to provision the requested services. In at least one embodiment, this enables the order coordination module 1122 to be isolated from implementation details, such as whether services and resources are provisioned in real-time or pre-provisioned and only allocated / assigned upon request.

[0192] In at least one embodiment, at step 1144, once services and resources are provisioned, a notification can be sent to the subscribing customer indicating that the requested services are now ready for use. In at least one embodiment, information (e.g., a link) can be sent to the customer that enables the customer to begin using the requested services.

[0193] In at least one embodiment, at step 1146, orders for which customers subscribe can be managed and tracked by an order management and monitoring module 1126. In at least one embodiment, the order management and monitoring module 1126 can be configured to collect usage statistics about customer usage of subscribed services. In at least one embodiment, statistics can be collected for amounts of storage used, amounts of data transferred, numbers of users, and amounts and / or changes in system up times and system down times.

[0194] In at least one embodiment, third party network infrastructure system 1100 can include an identity management module 1128 configured to provide identity services such as access management and authorization services in third party network infrastructure system 1100. In at least one embodiment, identity management module 1128 can control information about customers who wish to utilize services provided by third party network infrastructure system 1102. In at least one embodiment, such information can include information that authenticates the identities of such customers and information that describes what actions those customers are authorized to perform with respect to various resources (e.g., files, directories, applications, communication ports, memory segments, etc.). In at least one embodiment, identity management module 1128 can also include managing descriptive information about each customer and about who is authorized to access and modify such descriptive information and by whom.

[0195] Figure 12 A cloud computing environment 1202 is shown in accordance with at least one embodiment. In at least one embodiment, cloud computing environment 1202 includes one or more computer systems / server 1204 that are in communication with one or more computing devices, such as personal digital assistant (PDA) or cellular telephone 1206A, desktop computer 1206B, laptop computer 1206C, and / or automobile computer system 1206N, that are in communication with one or more computer systems / server 1204. In at least one embodiment, this allows infrastructure, platforms, and / or software to be offered as services available from cloud computing environment 1202 and thus does not require individual clients to have their own Figure 12 The types of computing devices 1206A-N shown in FIG. 12 are intended to be illustrative only and that cloud computing environment 1202 can communicate with any type of computerized device over any type of network and / or network / addressable connection (e.g., using a web browser).

[0196] In at least one embodiment, computer system / server 1204 can be operational with numerous other general purpose or special purpose computing system environments or configurations. In at least one embodiment, computing systems, environments, and / or configurations that can be suitable for use with computer system / server 1204 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and / or variants thereof.

[0197] In at least one embodiment, computer system / server 1204 can be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, and / or the like that perform particular tasks or implement particular abstract data types. In at least one embodiment, exemplary computer system / server 1204 can be practiced in distributed cloud computing environments with remote processing devices that are linked through a communications network. In at least one embodiment, in a distributed cloud computing environment, program modules can be located in both local and remote computer system storage media including memory storage devices.

[0198] Figure 13 A set of functional abstraction layers provided by cloud computing environment 1202 (FIG. 13) is shown. It should be understood that Figure 12 Figure 13 components, layers, and functions shown in FIG. 13 are intended to be illustrative only and that components, layers, and functions can be changed, combined, and / or eliminated.

[0199] In at least one embodiment, hardware and software layer 1302 includes hardware and software components. In at least one embodiment, hardware components include mainframes, various RISC (Reduced Instruction Set Computer) architecture-based servers, various computing systems, supercomputers, storage devices, networks, networking components, and / or the like. In at least one embodiment, software components include network application server software, various application server software, various database software, and / or the like.

[0200] In at least one embodiment, virtualization layer 1304 provides an abstraction layer from which the following exemplary virtual entities can be provided: virtual servers; virtual storage; virtual networks, including virtual private networks; virtual applications and / or the like.

[0201] ​In at least one embodiment, management layer 1306 provides various functions. In at least one embodiment, resource provisioning provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. In at least one embodiment, metering provides usage tracking of resources in use, for example, the usage of application software licenses. In at least one embodiment, provisioning provides a single point of management functionality that enables ubiquitous underwriting and rapid deployment of resources by orchestrating different layers of the cloud computing environment. In at least one embodiment, security provides identity verification for users and tasks, as well as protection for data and other resources. In at least one embodiment, user interface provides access to the cloud computing environment for both users and system administrators. In at least one embodiment, service level management provides cloud computing resource allocation and management such that required service levels are met. In at least one embodiment, service level agreement (SLA) planning and fulfillment provides pre-arrangement for, and fulfillment of, cloud computing resources to provide desired level of service to a user.

[0202] In at least one embodiment, workload layer 1308 provides functionality for which the cloud computing environment can be utilized. In at least one embodiment, workloads and functions that can be provided from this layer include: mapping and navigation; software development and management; education services; data analysis and processing; transaction processing; and services delivery.

[0203] Supercomputing

[0204] The following figures illustrate, but are not limited to, exemplary supercomputer-based systems that can be used to implement at least one embodiment.

[0205] In at least one embodiment, a supercomputer can refer to a hardware system that exhibits significant parallelism and includes at least one chip, where the chips in the system are interconnected by a network and are placed in a hierarchically organized enclosure. In at least one embodiment, a large hardware system that fills a machine room with several racks, each containing several board / rack modules, each containing several chips all interconnected by a scalable network, is at least one embodiment of a supercomputer. In at least one embodiment, a single rack of such a large hardware system is at least one other embodiment of a supercomputer. In at least one embodiment, a single chip that exhibits significant parallelism and contains several hardware components can also be considered a supercomputer, as the amount of hardware that can be incorporated in a single chip can increase as feature sizes can decrease.

[0206] Figure 14A supercomputer at the chip level is shown, according to at least one embodiment. In at least one embodiment, within an FPGA or ASIC chip, primary computation is performed within finite state machines (1404) called thread units. In at least one embodiment, a task and synchronization network (1402) connects finite state machines and is used to dispatch threads and perform operations in correct order. In at least one embodiment, a memory network (1406, 1410) is used to access a multi-level partitioned on-chip cache hierarchy (1408, 1412). In at least one embodiment, a memory controller (1416) and off-chip memory network (1414) is used to access off-chip memory. In at least one embodiment, an I / O controller (1418) is used for cross-chip communication when a design does not fit on a single logic chip.

[0207] Figure 15 A supercomputer at the rack module level is shown, according to at least one embodiment. In at least one embodiment, within a rack module, there are multiple FPGA or ASIC chips (1502) connected to one or more DRAM units (1504) that make up a main accelerator memory. In at least one embodiment, each FPGA / ASIC chip is connected to its neighboring FPGA / ASIC chip using a wide bus on board with differential high speed signaling (1506). In at least one embodiment, each FPGA / ASIC chip is also connected to at least one high speed serial communication cable.

[0208] Figure 16 A supercomputer at the rack level is shown, according to at least one embodiment. Figure 17 A supercomputer at the entire system level is shown, according to at least one embodiment. In at least one embodiment, see Figure 16 and Figure 17Between and across racks of rack modules, a scalable, possibly incomplete hypercube network is implemented using high-speed serial optical or copper cables (1602, 1702). In at least one embodiment, one of the FPGA / ASIC chips of an accelerator is connected to a host system (1704) through a PCI-Express connection. In at least one embodiment, a host system includes a host microprocessor (1708) on which software portions of an application run, and a memory consisting of one or more host memory DRAM units (1706) that are kept coherent with memory on an accelerator. In at least one embodiment, a host system can be a separate module on one of the racks, or can be integrated with one of the modules of a supercomputer. In at least one embodiment, a cyclic topology of cube connections provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, a small group of FPGA / ASIC chips on a rack module can act as a single hypercube node, such that the total number of external links per group is increased compared to a single chip. In at least one embodiment, a group contains chips A, B, C, and D on a rack module, which has an internal wide differential bus connecting A, B, C, and D in a ring organization. In at least one embodiment, there are 12 serial communication cables that connect the rack module to the outside world. In at least one embodiment, chip A on a rack module is connected to serial communication cables 0, 1, 2. In at least one embodiment, chip B is connected to cables 3, 4, 5. In at least one embodiment, chip C is connected to 6, 7, 8. In at least one embodiment, chip D is connected to 9, 10, 11. In at least one embodiment, the entire group {A, B, C, D} making up a rack module can form a hypercube node within a supercomputer system, with up to 2i2= 4096 rack modules (16384 FPGA / ASIC chips). In at least one embodiment, in order for chip A to send a message out on link 4 of the group {A, B, C, D}, the message must first be routed to chip B with an on-board differential wide bus connection. In at least one embodiment, a message arriving on link 4 destined for the group {A, B, C, D} of chips (i.e., to B) must also first be routed to the correct destination chip (A) inside the group {A, B, C, D}. In at least one embodiment, other sizes of parallel supercomputer systems can also be implemented.

[0209] Artificial intelligence

[0210] The following figures illustrate, but are not limited to, example artificial intelligence-based systems that can be used to implement at least one embodiment.

[0211] Figure 18AInference and / or training logic 1815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1815 are provided below in conjunction with FIGS. 1 A, 1 B, and 8. Figure 18A and / or Figure 18B Details regarding inference and / or training logic 1815 are provided below in conjunction with FIGS. 1 A, 1 B, and 8.

[0212] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, code and / or data storage 1801 for storing forward and / or output weight and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1801 for storing graph code or other software to control timing and / or order where weight and / or other parameter information will be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic unit(s) (ALUs)). In at least one embodiment, code such as graph code loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of a neural network that is trained in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or use of aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1801 can be included with other on-chip or off-chip data storage, including processor L1, L2, or L3 cache memory, or system memory.

[0213] In at least one embodiment, any portion of code and / or data storage 1801 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 1801 can be cache memory, dynamic random addressable memory (“DRAM”), static random addressable memory (“SRAM”), nonvolatile memory (e.g., Flash), or other storage. In at least one embodiment, whether code and / or code and / or data storage 1801 is internal or external to a processor, and / or the choice of including DRAM, SRAM, Flash, or some other type of storage, can depend on available storage on-chip relative to off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0214] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, code and / or data storage 1805 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 1805 stores weight parameters and / or input / output data for each layer of a neural network that is trained in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1805 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information will be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0215] In at least one embodiment, code such as graph code causes weight or other parameter information to be loaded into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 1805 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1805 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1805 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, whether code and / or data storage 1805 is internal or external to a processor, or includes a choice of DRAM, SRAM, Flash, or some other storage type, can depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0216] In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be separate storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be combined storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be partially combined and partially separate. In at least one embodiment, any portion of code and / or data store 1801 and code and / or data store 1805 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0217] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, one or more arithmetic logic units (“ALUs”), including integer and / or floating-point units, for performing logical and / or mathematical operations based, at least in part, on training and / or inference code (e.g., graphics code) or instructions by training and / or inference code (e.g., graphics code), results of which can produce activations (e.g., output values from layers or neurons within a neural network) stored in activation storage 1820, which is a function of input / output and / or weight parameter data stored in code and / or data store 1801 and / or code and / or data store 1805. In at least one embodiment, activations stored in activation storage 1820 are generated from linear algebra and / or matrix-based mathematics performed by ALU 1810 in response to executing instructions or other code, where weight values stored in code and / or data store 1805 and / or data store 1801 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which can be stored in code and / or data store 1805 or code and / or data store 1801 or another storage on-chip or off-chip.

[0218] In at least one embodiment, one or more ALUs 1810 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 1810 may be external to the processor or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, ALUs 1810 may be included within an execution unit of a processor or otherwise within an ALU bank accessible by an execution unit of a processor, either within the same processor or distributed across different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1801, code and / or data storage 1805, and activation storage 1820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1820 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry and fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic circuitry.

[0219] In at least one embodiment, activation storage 1820 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage devices. In at least one embodiment, activation storage 1820 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 1820 is internal or external to the processor, or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0220] In at least one embodiment, Figure 18A The inference and / or training logic 1815 shown in FIG can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU), or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 18A The inference and / or training logic 1815 shown in FIG may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0221] Figure 18B Inference and / or training logic 1815 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 1815 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown in FIG can be combined with an application specific integrated circuit (ASIC) (such as the one from Google Processing unit from Graphcore TM Inference Processing Unit (IPU), or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown in FIG can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 1815 includes, but is not limited to, code and / or data storage 1801 and code and / or data storage 1805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 18B In at least one embodiment described in

[0065] , each of code and / or data storage 1801 and code and / or data storage 1805 is associated with dedicated computing resources, such as computing hardware 1802 and computing hardware 1806, respectively. In at least one embodiment, each of computing hardware 1802 and computing hardware 1806 includes one or more ALUs that perform mathematical functions (such as linear algebraic functions) solely on the information stored in code and / or data storage 1801 and code and / or data storage 1805, respectively, with the results being stored in activation storage 1820.

[0222] In at least one embodiment, each code and / or data store 1801 and 1805 and corresponding compute hardware 1802 and 1806, respectively, correspond to different layers of a neural network, such that resulting activations from one storage / compute pair 1801 / 1802 are provided as input to the next storage / compute pair 1805 / 1806 in code and / or data store 1805 and compute hardware 1806, mirroring a conceptual organization of a neural network. In at least one embodiment, each of storage / compute pairs 1801 / 1802 and 1805 / 1806 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) after or in parallel with storage / compute pairs 1801 / 1802 and 1805 / 1806 can be included in inference and / or training logic 1815.

[0223] Figure 19 Training and deployment of a deep neural network is shown, in accordance with at least one embodiment. In at least one embodiment, an untrained neural network 1906 is trained using a training dataset 1902. In at least one embodiment, training framework 1904 is a PyTorch framework, while in other embodiments, training framework 1904 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 1904 trains untrained neural network 1906 and enables it to train using processing resources described herein to generate a trained neural network 1908. In at least one embodiment, weights can be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0224] In at least one embodiment, an untrained neural network 1906 is trained using supervised learning, where a training dataset 1902 includes inputs paired with desired outputs for inputs, or where a training dataset 1902 includes inputs with known outputs and outputs of the neural network 1906 are manually graded. In at least one embodiment, an untrained neural network 1906 is trained in a supervised manner and inputs from a training dataset 1902 are processed and resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 1906. In at least one embodiment, a training framework 1904 adjusts weights that control the untrained neural network 1906. In at least one embodiment, a training framework 1904 includes tools to monitor how well an untrained neural network 1906 is converging towards a model, such as a trained neural network 1908, that is suitable to generate correct answers, such as results 1914, based on input data, such as a new dataset 1912. In at least one embodiment, a training framework 1904 trains an untrained neural network 1906 repeatedly while using a loss function and adjustment algorithm, such as stochastic gradient descent, to adjust weights to refine outputs of the untrained neural network 1906. In at least one embodiment, a training framework 1904 trains an untrained neural network 1906 until the untrained neural network 1906 achieves a desired accuracy. In at least one embodiment, a trained neural network 1908 can then be deployed to implement any number of machine learning operations.

[0225] In at least one embodiment, an untrained neural network 1906 is trained using unsupervised learning, where an untrained neural network 1906 attempts to train itself using unlabeled data. In at least one embodiment, an unsupervised learning training dataset 1902 will include input data without any associated output data or “ground truth” data. In at least one embodiment, an untrained neural network 1906 can learn groupings within a training dataset 1902 and can determine how individual inputs relate to the untrained dataset 1902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in a trained neural network 1908 that is capable of performing operations useful in reducing a dimensionality of a new dataset 1912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for identification of data points in a new dataset 1912 that deviate from a normal pattern of the new dataset 1912.

[0226] In at least one embodiment, semi-supervised learning can be used, which is a technique where a mix of labeled and unlabeled data is included in a training dataset 1902. In at least one embodiment, training framework 1904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables a trained neural network 1908 to adapt to new datasets 1912 without forgetting knowledge that was imprinted within trained neural network 1408 during initial training.

[0227] 5G network

[0228] The following figures set forth, without limitation, exemplary 5G network-based systems that can be used to implement at least one embodiment.

[0229] Figure 20 Architecture of a system 2000 of a network, in accordance with at least one embodiment, is shown. In at least one embodiment, system 2000 is shown to include a user equipment (UE) 2002 and UE 2004. In at least one embodiment, UEs 2002 and 2004 are shown as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but can also include any mobile or non-mobile computing device, such as personal data assistants (PDAs), pagers, laptop computers, desktop computers, wireless handsets or any computing device including a wireless communications interface.

[0230] In at least one embodiment, any of UEs 2002 and 2004 can comprise an Internet of Things (IoT) UE, which can comprise an network access layer designed for low-power IoT applications utilizing short-lived connections. In at least one embodiment, an IoT UE can utilize technologies such as machine-to-machine (M2M) or machine-type communications (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), a proximity-based service (ProSe) or device-to-device (D2D) communication, sensor networks, or IoT networks. In at least one embodiment, M2M or MTC data exchanges can be machine-initiated exchanges in which data is exchanged between members of a M2M or MTC network. In at least one embodiment, an IoT network describes interconnecting IoT UEs, which can include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections.

[0231] In at least one embodiment, UEs 2002 and 2004 can be configured to connect with a radio access network (RAN) 2016 (e.g., communicatively coupled with the RAN 2016). In at least one embodiment, the RAN 2016 can be an evolved universal mobile telecommunication system (UMTS) terrestrial radio access network (E-UTRAN), a NextGen RAN (NG-RAN), or some other type of RAN. In at least one embodiment, UEs 2002 and 2004 utilize connections 2012 and 2014, respectively, each of which includes a physical

[0232] In at least one embodiment, UEs 2002 and 2004 can also directly exchange communication data via a ProSe interface 2006. In at least one embodiment, the ProSe interface 2006 can alternatively be referred to as a sidelink interface comprising one or more logical channels, including but not limited to a physical sidelink control channel (PSCCH), a physical sidelink shared channel (PSSCH), a physical sidelink discovery channel (PSDCH), and a physical sidelink broadcast channel (PSBCH).

[0233] In at least one embodiment, UE 2004 is illustrated as being configured to access an access point (AP) 2010 via connection 2008. In at least one embodiment, connection 2008 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein the AP 2010 would comprise a wireless fidelity router. In at least one embodiment, AP 2010 is illustrated as connected to the Internet without connecting to the core network, although this is not required in every embodiment. In at least one embodiment, AP 2010 can represent a plurality of APs connected in a mesh network, each AP communicating data to one another over respective mesh network connections.

[0234] In at least one embodiment, RAN 2016 can include one or more access nodes 2012 and 2014 that enable the connection 2012 and 2014. In at least one embodiment, these access nodes (ANs) can be referred to as base stations, NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNBs), RAN nodes, and / or the like, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage over a geographic area, such as a cell. In at least one embodiment, RAN 2016 can include one or more RAN nodes for providing macrocells (e.g., macro RAN node 2018) and one or more RAN nodes for providing femtocells or picocells (e.g., low power (LP) RAN node 2020).

[0235] In at least one embodiment, any of the RAN nodes 2018 and 2020 can terminate the air interface protocol and can be the first point of contact for the UEs 2002 and 2004. In at least one embodiment, any of the RAN nodes 2018 and 2020 can fulfill various logical functions for the RAN 2016 including, but not limited to, RNC functionssuch as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[0236] In at least one embodiment, UEs 2002 and 2004 can be configured to communicate using orthogonal frequency division multiplexing (OFDM) communication signals with each other or with any of the RAN nodes 2018 and 2020 over a multicarrier communication channel in accordance with various communication techniques, such as, but not limited to, an orthogonal frequency division multiple access (OFDMA) communication technique (e.g., for downlink communications) or a single carrier frequency division multiple access (SC-FDMA) communication technique (e.g., for uplink and ProSe or sidelink communications), and / or variants thereof. In at least one embodiment, OFDM signals can comprise orthogonal waveform signals, such as sinusoids with frequencies that are orthogonal with one another.

[0237] In at least one embodiment, a downlink resource grid can be used for downlink transmissions from any of the RAN node 2018 and 2020 to the UEs 2002 and 2004, while uplink transmissions can utilize a similar approach. In at least one embodiment, the grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. In at least one embodiment, such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. In at least one embodiment, each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to one slot, which depends on the downlink slot duration. In at least one embodiment, the minimum time-frequency unit in the resource grid is denoted as a resource element. In at least one embodiment, the resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block comprises a collection of resource elements in the time domain and frequency domain. In at least one embodiment, in the frequency domain, this can represent the smallest quantity of resources that can be allocated, in at least one embodiment, there are several different physical downlink channels that are conveyed using such resource blocks.

[0238] In at least one embodiment, a physical downlink shared channel (PDSCH) can carry user data and higher layer signaling to the UEs 2002 and 2004. In at least one embodiment, a physical downlink control channel (PDCCH) can carry information about the transport format and resource allocations for the PDSCH channels, etc. In at least one embodiment, it can also inform the UEs 2002 and 2004 about the transport format, resource allocation, and HARQ information for uplink shared channel. In at least one embodiment, generally, downlink scheduling (allocating control and shared channel resource blocks to the UEs 2002 within a cell) can be performed at any of the RAN nodes 2018 and 2020 based on channel quality information feedback from any of the UEs 2002 and 2004. In at least one embodiment, downlink resource allocation information can be sent on the PDCCH used for each of the UEs 2002 and 2004.

[0239] In at least one embodiment, a PDCCH can use control channel elements (CCEs) to convey control information. In at least one embodiment, PDCCH complex-valued symbols can first be organized into quadruplets, then permuted using a sub-block interleaver for rate matching, in at least one embodiment, one or more of these CCEs can be used to transmit each PDCCH, where each CCE can correspond to nine sets of four resource element groups (REGs), referred to as resource element groups (REGs). In at least one embodiment, four Quadrature Phase Shift Keying (QPSK) symbols can be mapped to each REG. In at least one embodiment, depending on the Downlink Control Information (DCI) size and the channel condition, one or more CCEs can be used to send a PDCCH. In at least one embodiment, there can be four or more different PDCCH formats (e.g., aggregation level, L=l, 2, 4, or 8) defined in LTE with different number of CCEs.

[0240] In at least one embodiment, an enhanced physical downlink control channel (EPDCCH) using PDSCH resources can be used for control information transmission. In at least one embodiment, one or more enhanced control channel elements (ECCEs) can be used to transmit EPDCCH. In at least one embodiment, each ECCE can correspond to nine sets of four physical resource elements called enhanced resource element groups (EREGs). In at least one embodiment, an ECCE can have other numbers of EREGs in some situations.

[0241] In at least one embodiment, RAN 2016 is shown to be communicatively coupled to core network (CN) 2038 via an S1 interface 2022. In at least one embodiment, CN 2038 can be an evolved packet core (EPC) network, a NextGen packet core (NPC) network, or some other type of CN. In at least one embodiment, S1 interface 2022 is split into two parts: the S1 -U interface 2026, which carries traffic data between RAN nodes 2018 and 2020 and serving gateway (S-GW) 2030, and the S1 -Mobility Management Entity (MME) interface 2024, which is a signaling interface between RAN nodes 2018 and 2020 and MME 2028.

[0242] In at least one embodiment, the CN 2038 includes a MME 2028, a S-GW 2030, a packet data network (PDN) gateway (P-GW) 2034, and a home subscriber server (HSS) 2032. In at least one embodiment, the MME 2028 can be similar in function to a control plane of legacy Serving General Packet Radio Service (GPRS) Support Nodes (SGSN). In at least one embodiment, the MME 2028 can manage mobility aspects in access such as gateway selection and tracking area list management. In at least one embodiment, the HSS 2032 can include a database for network users, including subscription-related information to support the network entities’ handling of communication sessions. In at least one embodiment, the CN 2038 can include one or more HSSs 2032 depending on the number of mobile subscribers, on the capacity of the equipment, on the organization of the network, etc. In at least one embodiment, the HSS 2032 can provide support for routing / roaming, authentication, authorization, naming / addressing resolution, location dependencies, etc.

[0243] In at least one embodiment, the S-GW 2030 can terminate the S1 interface 2022 towards RAN 2016, and route data packets between the RAN 2016 and the CN 2038. In at least one embodiment, the S-GW 2030 can be a local mobility anchor for inter-RAN node handovers and also for intra-RAN mobility including seamless handovers. In at least one embodiment, other responsibilities can include lawful intercept, charging, and some policy enforcement and steering functions.

[0244] In at least one embodiment, the P-GW 2034 can terminate an SGi interface towards a PDN. In at least one embodiment, the P-GW 2034 can route data packets between a EPC network 2038 and external networks such as the Internet 2042, and between the Internet 2042 and other UEs 2002, 2004. In at least one embodiment, the application server 2040 can be an element offering applications that use IP bearer resources to be provisioned by a core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.). In at least one embodiment, the P-GW 2034 is shown to be communicatively coupled to an application server 2040 via the IP communications interface 2042. In at least one embodiment, the application server 2040 can also be configured to support one or more communication services (e.g., Voice-over-Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UEs 2002, 2004 via the CN 2038.

[0245] In at least one embodiment, the P-GW 2034 can also be a node for policy enforcement and charging data collection. In at least one embodiment, a Policy and Charging Enforcement Function (PCRF) 2036 is a policy and charging control element of the CN 2038. In at least one embodiment, in a non-roaming scenario, there can be a single PCRF 2036 in a Home Public Land Mobile Network (HPLMN) associated with a UE’s Internet Protocol Connectivity Access Network (IP-CAN) session. In at least one embodiment, in a roaming scenario with local breakout of traffic, there can be two PCRFs associated with a UE’s IP-CAN session: a Home PCRF (H-PCRF) within a HPLMN and a Visited PCRF (V-PCRF) within a Visited Public Land Mobile Network (VPLMN). In at least one embodiment, the PCRF 2036 can be communicatively coupled to an application server 2040 via the P-GW 2034. In at least one embodiment, the application server 2040 can signal the PCRF 2036 to indicate a new service flow and select appropriate Quality of Service (QoS) and charging parameters. In at least one embodiment, the PCRF 2036 can provision this rule to a Policy and Charging Enforcement Function (PCEF) (not shown) with appropriate traffic flow template (TFT) and Quality of Class of Service (QCI) which commences the QoS and charging by the application server 2040.

[0246] Figure 21 An architecture of a system 2100 of a network is shown in accordance with some embodiments. In at least one embodiment, system 2100 is shown to include a UE 2102, a 5G access node or RAN node (shown as (R)AN node 2108), a user plane function (shown as UPF 2104), a data network (DN 2106), which in at least one embodiment can be operator services, Internet access, or third party services, and a 5G core network (5GC) (shown as CN 2110).

[0247] In at least one embodiment, the CN 2110 includes an Authentication Server Function (AUSF 2114); a Core Access and Mobility Management Function (AMF 2112); a Session Management Function (SMF 2118); a Network Exposure Function (NEF 2116); a Policy Control Function (PCF 2122); a Network Function (NF) Repository Function (NRF 2120); a Unified Data Management (UDM 2124); and an Application Function (AF 2126). In at least one embodiment, the CN 2110 can also include other elements not shown, such as a Structured Data Storage Network Function (SDSF), an Unstructured Data Storage Network Function (UDSF), and variations thereof.

[0248] In at least one embodiment, the UPF 2104 can serve as an anchor point for intra-RAT and inter-RAT mobility, an external PDU session point interconnected to the DN 2106, and a branch point supporting multi-homed PDU sessions. In at least one embodiment, the UPF 2104 can also perform packet routing and forwarding, packet inspection, user plane portion of policy rule enforcement, lawful interception of packets (UP collection), service usage reporting, QoS processing for the user plane (e.g., packet filtering, gating, UL / DL rate enforcement), uplink service validation (e.g., SDF to QoS flow mapping), transport-level packet marking in the uplink and downlink, downlink packet buffering, and downlink data notification triggering. In at least one embodiment, the UPF 2104 can include an uplink classifier to support routing of service flows to the data network. In at least one embodiment, the DN 2106 can represent various network operator services, internet access, or third-party services.

[0249] In at least one embodiment, the AUSF 2114 may store data used for authentication of the UE 2102 and handle authentication-related functions. In at least one embodiment, the AUSF 2114 may facilitate a common authentication framework for various access types.

[0250] In at least one embodiment, AMF2112 may be responsible for registration management (e.g., for registering UE2102, etc.), connection management, reachability management, mobility management, and legal interception of AMF-related events, as well as access authentication and authorization. In at least one embodiment, AMF2112 may provide transmission of SM messages for SMF2118 and act as a transparent proxy for routing SM messages. In at least one embodiment, AMF2112 may also provide UE2102 with SMS function (SMSF) ( Figure 21 In at least one embodiment, the AMF 2112 may comprise a security context management (SCM) function that receives from the SEA a key that it uses to derive an access network-specific key. In addition, in at least one embodiment, the AMF 2112 may comprise a security context management (SCM) function that receives from the SEA a key that it uses to derive an access network-specific key. In addition, in at least one embodiment, the AMF 2112 may comprise a security anchor function (SEA) that may comprise interaction with the AUSF 2114 and the UE 2102 and reception of an intermediate key established as a result of the UE 2102 authentication process. In at least one embodiment, the AMF 2112 may comprise a security context management (SCM) function that receives from the SEA a key that it uses to derive an access network-specific key. In addition, in at least one embodiment, the AMF 2112 may be a termination point for the RANCP interface (N2 reference point), a termination point for NAS (NI) signaling, and perform NAS encryption and integrity protection.

[0251] In at least one embodiment, the AMF 2112 can also support NAS signaling with the UE 2102 over an N3 interworking function (IWF) interface. In at least one embodiment, the N3IWF can be used to provide access to untrusted entities. In at least one embodiment, the N3IWF can be a termination point for N2 and N3 interfaces for control plane and user plane, respectively, and thus can handle N2 signaling from SMF and AMF for PDU session and QoS, encapsulate / decapsulate packets for IPSec and N3 tunneling, mark N3 user-plane packets in uplink, and enforce QoS corresponding to N3 packet marking taking into account QoS requirements associated with such marking received over N2. In at least one embodiment, the N3IWF can also relay uplink and downlink control-plane NAS (N I) signaling between the UE 2102 and AMF 2112, and relay uplink and downlink user-plane packets between the UE 2102 and UPF 2104. In at least one embodiment, the N3IWF also provides mechanisms for IPsec tunnel establishment with the UE 2102.

[0252] In at least one embodiment, the SMF 2118 can be responsible for session management (e.g., session establishment, modify, and release, including UPF and AN node selection); UE IP address allocation and management (including optional authorization); selection and control of UP function; configuration of traffic steering at UPF to route traffic to proper destination; interface termination towards policy control functions; control plane part of policy enforcement and QoS; lawful intercept (for SM events and interface to LI system); termination of SM parts of NAS messages; downlink data notification; initiator of AN specific SM information transmitted over N2 to AN via AMF; determining SSC mode of a session. In at least one embodiment, the SMF 2118 can include the following roaming functionality: handling local enforcement to apply QoS SLAs (VPLMN); charging data collection and charging interface (VPLMN); lawful intercept (in VPLMN for SM events and interface to LI system); support for interaction with external DN to transfer signaling for PDU session authorization / authentication by external DN.

[0253] In at least one embodiment, the NEF 2116 can provide means for securely exposing services and capabilities offered by 3 GPP network functions for third party, internal exposure / re exposure, application functions (e.g., AF 2126), edge computing or fog computing systems, etc. In at least one embodiment, the NEF 2116 can authenticate, authorize, and / or throttle AFs. In at least one embodiment, the NEF 2116 can also translate information exchanged with AFs 2126 and information exchanged with internal network functions. In at least one embodiment, the NEF 2116 can translate between AF service identifiers and internal 5GC information. In at least one embodiment, the NEF 2116 can also receive information from other network functions (NFs) based on exposed capabilities of other network functions. In at least one embodiment, this information can be stored at the NEF 2116 as structured data, or at a data storage NF using standardized interfaces. In at least one embodiment, the stored information can then be re-exposed by the NEF 2116 to other NFs and AFs, and / or used for other purposes such as analytics.

[0254] In at least one embodiment, the NRF 2120 can support service discovery functions, receive NF discovery requests from NF instances, and provide information of discovered NF instances to NF instances. In at least one embodiment, the NRF 2120 also maintains information of available NF instances and their supported services.

[0255] In at least one embodiment, the PCF 2122 can provide policy rules to control plane functions to enforce them, and can also support a unified policy framework to govern network behavior. In at least one embodiment, the PCF 2122 can also implement a front end (FE) to access subscription information related to policy decisions in a UDR of UDM 2124.

[0256] In at least one embodiment, the UDM 2124 can handle subscription-related information to support network entities handling communication sessions, and can store subscription data of UEs 2102. In at least one embodiment, the UDM 2124 can include two parts, an application FE and a user data repository (UDR). In at least one embodiment, the UDM can include a UDM FE that is responsible for processing credentials, location management, subscription management, etc. In at least one embodiment, several different front ends can service the same user in different transactions. In at least one embodiment, the UDM-FE accesses subscription information stored in the UDR and performs authentication credential processing; user identification processing; access authorization; registration / mobility management; and subscription management. In at least one embodiment, the UDR can interact with the PCF 2122. In at least one embodiment, the UDM 2124 can also support SMS management, where an SMS-FE implements similar application logic as previously discussed.

[0257] In at least one embodiment, AF 2126 can provide application influence on traffic routing, access to network capability exposure (NCE), and interaction with policy framework for policy control. In at least one embodiment, NCE can be a mechanism that allows 5GC and AF 2126 to provide information to each other via NEF 2116, which can be used for edge computing implementation. In at least one embodiment, network operators and third party services can be hosted close to the access point of attachment of a UE 2102 for efficient service delivery with reduced end-to-end latency and load on transport networks. In at least one embodiment, for edge computing implementation, 5GC can choose a UPF 2104 close to the UE 2102 and execute traffic steering from the UPF 2104 to DN 2106 via N6 interface. In at least one embodiment, this can be based on UE subscription data, UE location, and information provided by AF 2126. In at least one embodiment, AF 2126 can influence UPF (re)selection and traffic routing. In at least one embodiment, based on operator deployment, when AF 2126 is considered a trusted entity, network operator can allow AF 2126 to interact directly with relevant NFs.

[0258] In at least one embodiment, CN 2110 can include an SMSF, which can be responsible for SMS subscription checking and verification, and relaying SM messages to / from UEs 2102 to / from other entities, such as SMS-GMSC / IWMSC / SMS-router. In at least one embodiment, SMS can also interact with AMF 2112 and UDM 2124 for a notification procedure that the UE 2102 is available for SMS transfer (e.g., setting a UE-Not-Reachable flag, and notifying UDM 2124 when UE 2102 is available for SMS).

[0259] In at least one embodiment, system 2100 can include the following service-based interfaces: Namf: service-based interface exposed by AMF; Nsmf: service-based interface exposed by SMF; Nnef: service-based interface exposed by NEF; Npcf: service-based interface exposed by PCF; Nudm: service-based interface exposed by UDM; Naf: service-based interface exposed by AF; Nnrf: service-based interface exposed by NRF; and Nausf: service-based interface exposed by AUSF.

[0260] In at least one embodiment, system 2100 can include the following reference points: N1: Reference point between UE and AMF; N2: Reference point between (R)AN and AMF; N3: Reference point between (R)AN and UPF; N4: Reference point between SMF and UPF; and N6: Reference point between UPF and Data Network. In at least one embodiment, there can be more reference points and / or service-based interfaces between NFs, however, these interfaces and reference points have been omitted for clarity. In at least one embodiment, a NS reference point can be between a PCF and an AF; a N7 reference point can be between a PCF and a SMF; a N11 reference point between an AMF and a SMF; and / or the like. In at least one embodiment, CN 2110 can include an Nx interface, which is an inter-CN interface between MME and AMF 2112 in order to enable interworking between CN 2110 and CN 7221.

[0261] In at least one embodiment, system 2100 can include multiple RAN nodes, such as (R)AN nodes 2108, where the Xn interface is defined between two or more (R)AN nodes 2108 connected to 5GC 410, between a (R)AN node 2108 (e.g., gNB) and an eNB (e.g., macro RAN node) connected to CN 2110, and / or between two eNBs connected to CN 2110.

[0262] In at least one embodiment, Xn interface can include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, Xn-U can provide guaranteed delivery of user plane PDUs with some exceptions and support / provide data forwarding and flow control functionality. In at least one embodiment, Xn-C can provide management and error handling functionality, functionality to manage the Xn-C interface; mobility support for UEs 2102 in a connected mode (e.g., CM-CONNECTED) including functionality to manage connected mode UE mobility between one or more (R)AN nodes 2108. In at least one embodiment, mobility support can include context transfer from an old (source) serving (R)AN node 2108 to new (target) serving (R)AN node 2108; and control of user plane tunnels between old (source) serving (R)AN node 2108 to new (target) serving (R)AN node 2108.

[0263] In at least one embodiment, the Xn-U protocol stack can include a transport network layer built on top of an Internet Protocol (IP) transport layer and a GTP-U layer for carrying user plane PDUs on top of a UDP and / or one or more IP layers. In at least one embodiment, the Xn-C protocol stack can include an application layer signaling protocol, referred to as Xn Application Protocol (Xn-AP), and a transport network layer built on top of an SCTP layer. In at least one embodiment, the SCTP layer can be on top of an IP layer. In at least one embodiment, the SCTP layer provides a guaranteed delivery of application layer messages. In at least one embodiment, in the transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In at least one embodiment, the Xn-U protocol stack and / or the Xn-C protocol stack can be the same as or similar to user plane and / or control plane protocol stacks shown and described herein.

[0264] Figure 22 is an illustration of a control plane protocol stack in accordance with some embodiments. In at least one embodiment, control plane 2200 is illustrated as a communication protocol stack between UE 2002 (or, alternatively, UE 2004), RAN 2016, and MME 2028.

[0265] In at least one embodiment, PHY layer 2202 can transmit or receive information used by MAC layer 2204 over one or more air interfaces. In at least one embodiment, PHY layer 2202 can also perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers, such as RRC layer 2210. In at least one embodiment, PHY layer 2202 can further perform error detection on the transport channels, forward error correction (FEC) coding / decoding of the transport channels, modulation / demodulation of physical channels, interleaving, rate matching, mapping to physical channels, and Multiple Input Multiple Output (MIMO) antenna processing.

[0266] In at least one embodiment, MAC layer 2204 can perform mapping between logical channels and transport channels, multiplexing of MAC service data units (SDUs) from one or more logical channels into transport blocks (TB) to be delivered to PHY via transport channels, demultiplexing of MAC SDUs to one or more logical channels from TBs delivered via transport channels from PHY, multiplexing of MAC SDUs onto TBs, scheduling information reporting, error correction through hybrid automatic repeat request (HARQ), and logical channel prioritization.

[0267] In at least one embodiment, RLC layer 2206 can operate in multiple modes of operation, including: transparent mode (TM), unacknowledged mode (UM), and acknowledged mode (AM). In at least one embodiment, RLC layer 2206 can perform transfer of upper layer protocol data units (PDUs), error correction through automatic repeat request (ARQ) for AM data transfers, and concatenation, segmentation, and reassembly of RLC SDUs for UM and AM data transfers. In at least one embodiment, RLC layer 2206 can also perform re-segmentation of RLC data PDUs for AM data transfers, reordering of RLC data PDUs for UM and AM data transfers, detect duplicate data for UM and AM data transfers, discard RLC SDUs for UM and AM data transfers, detect protocol errors for AM data transfers, and perform RLC re-establishment.

[0268] In at least one embodiment, PDCP layer 2208 can perform header compression and decompression of IP data, maintain PDCP sequence numbers (SNs), perform in-sequence delivery of upper layer PDUs at re-establishment of lower layers, eliminate duplication of lower layer SDUs at re-establishment of lower layers for RLC AM mapped radio bearers, cipher and decipher control plane data, integrity protect and integrity verify control plane data, perform data

[0269] In at least one embodiment, main services and functions of RRC layer 2210 can include broadcast of system information (e.g., included in master information block (MIB) or system information blocks (SIBs) related to non-access stratum (NAS)), broadcast of system information related to access stratum (AS), paging of the UE by E-UTRAN for a paging message, establishment, configuration, maintenance and release of an RRC connection between the UE and E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), setup, configuration, maintenance and release of point-to-point Radio Bearers, security functions including key management, inter-RAT mobility, and measurement configuration for reporting by the UE. In at least one embodiment, MIB and SIBs can include one or more information elements (IEs), each of which can include individual data fields or data structures.

[0270] In at least one embodiment, UE 2002 and RAN 2016 can utilize a Uu interface (e.g., LTE-Uu interface) to exchange control plane data via a protocol stack including PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208, and RRC layer 2210.

[0271] In at least one embodiment, a non-access stratum (NAS) protocol (NAS protocol 2212) forms a highest stratum of the control plane between UE 2002 and MME 2028. In at least one embodiment, NAS protocol 2212 supports mobility of UE 2002 and session management procedures to establish and maintain IP connectivity between UE 2002 and P-GW 2034.

[0272] In at least one embodiment, an Si application protocol (Si-AP) layer (Si-AP layer 2222) can support functions of the Si interface and include elementary procedures (EPs). In at least one embodiment, an EP is a unit of interaction between RAN 2016 and CN 2028. In at least one embodiment, S1-AP layer services can include two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these services perform functions including, but not limited to: E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transfer, RAN Information Management (RIM), and configuration transfer.

[0273] In at least one embodiment, a stream control transmission protocol (SCTP) layer (alternatively referred to as a stream control transmission protocol / internet protocol (SCTP / IP) layer) (SCTP layer 2220) can ensure reliable delivery of signaling messages between RAN 2016 and MME 2028 based, in part, on IP protocols supported by IP layer 2218. In at least one embodiment, L2 layer 2216 and L1 layer 2214 can refer to communication links (e.g., wired or wireless) used by RAN nodes and MMEs to exchange information.

[0274] In at least one embodiment, RAN 2016 and one or more MMEs 2028 can utilize an S1-MME interface to exchange control plane data via a protocol stack including L1 layer 2214, L2 layer 2216, IP layer 2218, SCTP layer 2220, and Si-AP layer 2222.

[0275] Figure 23 is a diagram of a user plane protocol stack, in accordance with at least one embodiment. In at least one embodiment, user plane 2300 is shown as a communication protocol stack between UE 2002, RAN 2016, S-GW 2030, and P-GW 2034. In at least one embodiment, user plane 2300 can utilize the same protocol layers as control plane 2200. In at least one embodiment, UE 2002 and RAN 2016 can utilize a Uu interface (e.g., an LTE-Uu interface) to exchange user plane data via a protocol stack including PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208.

[0276] In at least one embodiment, a general packet radio service (GPRS) tunneling protocol (GTP-U) layer (GTP-U layer 2304) for user plane can be used to carry user data within a GPRS core network and between a radio access network and a core network. In at least one embodiment, user data transported can be packets of any size that the protocol stack is designed to handle, including IPv4, IPv6, or PPP encapsulated data. In at least one embodiment, a UDP / IP layer (UDP / IP layer 2302) can provide checksums for data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication on selected data flows. In at least one embodiment, RAN 2016 and S-GW 2030 can utilize an S1-U interface to exchange user plane data via a protocol stack comprising L1 layer 2214, L2 layer 2216, UDP / IP layer 2302, and GTP-U layer 2304. In at least one embodiment, S-GW 2030 and P-GW 2034 can utilize a S5 / S8a interface to exchange user plane data via a protocol stack comprising L1 layer 2214, L2 layer 2216, UDP / IP layer 2302, and GTP-U layer 2304. In at least one embodiment, as discussed above with respect to FIG. 22, NAS protocols support mobility and session management procedures for UE 2002 to establish and maintain IP connectivity between UE 2002 and P-GW 2034. Figure 22

[0277] Figure 24 Components of a core network are shown in accordance with at least one embodiment 2400. In at least one embodiment, components of CN 2038 can be implemented in one physical node or in separate physical nodes including components to read and execute instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, network function virtualization (NFV) is used to virtualize any or all of the above-described network node functions via executable instructions stored in one or more computer-readable storage mediums (described in further detail below). In at least one embodiment, a logical instantiation of CN 2038 can be referred to as a network slice 2402 (e.g., network slice 2402 is shown to include HSS 2032, MME 2028, and S-GW 2030). In at least one embodiment, a logical instantiation of a portion of CN 2038 can be referred to as a network sub-slice 2404 (e.g., network sub-slice 2404 is shown to include P-GW 2034 and PCRF 2036).

[0278] ​In at least one embodiment, NFV architecture and infrastructure can be used to virtualize one or more network functions onto one or more physical servers that include a combination of industry-standard server hardware, storage hardware, or switches, which can alternatively be replaced by virtualized or reconfigurable hardware. In at least one embodiment, NFV systems can be used to perform virtual or reconfigurable implementations of one or more EPC components / functions.

[0279] Figure 25 FIG. 25 illustrates a block diagram of components of a system 2500 used to support network function virtualization (NFV), according to at least one embodiment. In at least one embodiment, system 2500 is shown to include a virtualization infrastructure manager (shown as VIM 2502), a network function virtualization infrastructure (shown as NFVI 2504), a VNF manager (shown as VNFM 2506), a virtualized network function (shown as VNF 2508), an element manager (shown as EM 2510), an NFV orchestrator (shown as NFVO 2512), and a network manager (shown as NM 2514).

[0280] In at least one embodiment, VIM 2502 manages resources of NFVI 2504. In at least one embodiment, NFVI 2504 can include physical or virtual resources and applications (including a hypervisor) used to execute system 2500. In at least one embodiment, VIM 2502 can utilize NFVI 2504 to manage life cycle of virtual resources (e.g., creation, maintenance, and tearing down of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, faults, and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

[0281] In at least one embodiment, VNFM 2506 can manage VNF 2508. In at least one embodiment, VNF 2508 can be used to execute EPC components / functions. In at least one embodiment, VNFM 2506 can manage life cycle of VNF 2508 and track performance, faults, and security of virtual aspects of VNF 2508. In at least one embodiment, EM 2510 can track performance, faults, and security of functional aspects of VNF 2508. In at least one embodiment, tracking data from VNFM 2506 and EM 2510 can include, in at least one embodiment, performance measurement (PM) data used by VIM 2502 or NFVI 2504. In at least one embodiment, both VNFM 2506 and EM 2510 can scale up / down the number of VNFs of system 2500.

[0282] In at least one embodiment, NFVO 2512 can coordinate, authorize, release, and occupy resources of NFVI 2504 in order to provide the requested service (e.g., to execute an EPC function, component, or slice). In at least one embodiment, NM 2514 can provide a package of end-user functions that are responsible for managing a network that can include network elements that are VNFs, non-virtualized network functions, or both (management of VNFs can occur via EM 2510).

[0283] Computer-based system

[0284] The following figures present, without limitation, exemplary computer-based systems that can be used to implement at least one embodiment.

[0285] Figure 26 A processing system 2600 according to at least one embodiment is shown. In at least one embodiment, system 2600 includes one or more processor(s) 2602 and one or more graphics processing unit(s) 2608, and can be a single processor desktop system, a multiprocessor workstation system, or a server system having many processors 2602 or processor cores 2607. In at least one embodiment, processing system 2600 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0286] In at least one embodiment, processing system 2600 can include, or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system 2600 is a mobile phone, a smart phone, a tablet device, or a mobile internet device. In at least one embodiment, processing system 2600 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0287] In at least one embodiment, one or more processors 2602 each include one or more processor cores 2607 to process instructions which, when executed, perform operations such as operations for systems and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a specific instruction set 2609. In at least one embodiment, instruction set 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via a very long instruction word (VLIW). In at least one embodiment, multiple processor cores 2607 can each process a different instruction set 2609, which can include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 2607 can also include other processing devices, such as a digital signal processor (DSP).

[0288] In at least one embodiment, processor 2602 includes cache memory 2604. In at least one embodiment, processor 2602 can have single-level or multi-level internal caches. In at least one embodiment, cache memory is shared among multiple components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a level three (L3) cache or last level cache (LLC)) (not shown), which can be shared among processor cores 2607 using known cache coherency techniques. In at least one embodiment, register file 2606 is additionally included in processor 2602, which can include different types of registers to store different kinds of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2606 can include a general register file or other registers.

[0289] In at least one embodiment, one or more processors 2602 are coupled with one or more interface buses 2610 for passing communication signals between processor 2602 and other components of system 2600. In at least one embodiment, one or more of interface buses 2610 can be versions of a Peripheral Component Interconnect (PCI) bus or PCI Express bus. In at least one embodiment, one or more of interface buses 2610 can be versions of an Industry Standard Architecture (ISA) bus, a MicroChannel Architecture (MCA) bus, an Intelll bus, a VESA local bus, an Accelerated Graphics Port (AGP) bus, a Video Electronics Standards Association (VESA) bus, or other suitable bus. In at least one embodiment, one or more of interface buses 2610 can be a bus using time-division multiplexing, a bus using Throttling, or another suitable bus structure at one or more embodiments. In at least one embodiment, one or more of interface buses 2610 can be a bus that is not standardized.

[0290] In at least one embodiment, memory device 2620 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, or a

[0291] In at least one embodiment, platform controller hub 2630 enables peripherals to connect to storage devices 2620 and processor 2602 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include, but are not limited to, audio controller 2646, network controller 2634, firmware interface 2628, wireless transceiver 2626, touch sensors 2625, data storage devices 2624 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage devices 2624 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, touch sensors 2625 can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2628 enables communication with system firmware, in at least one embodiment, and can be a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2634 can enable network connectivity to one or more wired networks. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2610. In at least one embodiment, audio controller 2646 is a multi-channel digital audio controller. In at least one embodiment, processing system 2600 includes an optional legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to processing system 2600. In at least one embodiment, platform controller hub 2630 can also connect to one or more Universal Serial Bus (USB) controllers 2642 that connect to input devices, such as keyboard and mouse combination 2643, camera 2644, or other USB input devices.

[0292] In at least one embodiment, memory controller 2616 and instances of platform controller hub 2630 can be integrated into a discrete external graphics processor, such as external graphics processor 2612. In at least one embodiment, platform controller hub 2630 and / or memory controller 2616 can be external to one or more processor(s) 2602. In at least one embodiment, processing system 2600 can include an external memory controller 2616 and platform controller hub 2630, which can be configured as a memory controller hub and a peripheral controller hub in a system-on-a-chip (SoC) that communicates with processor(s) 2602.

[0293] Figure 27A computer system 2700 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 2700 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 2700 is formed by a processor 2702, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 2700 can include, but is not limited to, components such as the processor 2702, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 2700 can include a processor such as the Intel® processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 2700 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux in at least one embodiment), embedded software, and / or graphical user interfaces may also be used.

[0294] In at least one embodiment, the computer system 2700 can be used in other devices, such as handheld devices and embedded applications. Some of at least one embodiment of a handheld device include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application can include a microcontroller, a digital signal processor ("DSP"), a SoC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0295] In at least one embodiment, computer system 2700 may include, but is not limited to, a processor 2702, which may include, but is not limited to, one or more execution units 2708, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( a CUDA program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 2700 is a single processor desktop or server system. In at least one embodiment, computer system 2700 can be a multiprocessor system. In at least one embodiment, processor 2702 can include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, in at least one embodiment. In at least one embodiment, processor 2702 can be coupled to a processor bus 2710 that can transmit data signals between processor 2702 and other components in computer system 2700.

[0296] In at least one embodiment, processor 2702 can include, without limitation, a level 1 (“Ll”) internal cache memory (“cache”) 2704. In at least one embodiment, processor 2702 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, cache memory can reside in the processor 2702’s external. In at least one embodiment, processor 2702 can include a combination of internal and external caches. In at least one embodiment, register file 2706 can store different types of data within various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer registers.

[0297] In at least one embodiment, execution unit 2708, including, without limitation, logic to perform integer and floating point operations, also resides in processor 2702. Processor 2702 can also include microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 2708 can include logic to handle a packed instruction set 2709. In at least one embodiment, by including the packed instruction set 2709 in the instruction set of a general-purpose processor 2702, along with associated circuitry to execute the instructions, the general-purpose processor 2702 can be used to perform the operations on packed data that many multimedia applications use. In at least one embodiment, by using the full width of the processor’s data bus when performing operations on packed data, many multimedia applications can be accelerated as compared to using load / store type architectures, which can require multiple Tens of load and store operations per application.

[0298] In at least one embodiment, execution unit 2708 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 2700 can include, but not limited to, memory 2720. In at least one embodiment, memory 2720 can be implemented as a DRAM device, SRAM device, flash memory device, or other memory device. Memory 2720 can store instructions 2719 and / or data 2721 that can be executed by processor 2702 as signaled by data signals.

[0299] In at least one embodiment, system logic chip can be coupled to processor bus 2710 and memory 2720. In at least one embodiment, system logic chip can include, without limitation, a memory controller hub (“MCH”) 2716, and processor 2702 can communicate with MCH 2716 via processor bus 2710. In at least one embodiment, MCH 2716 can provide a high bandwidth memory path 2718 to memory 2720 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 2716 can direct data signals between processor 2702, memory 2720, and other components in computer system 2700, and can

[0300] In at least one embodiment, computer system 2700 can use system I / O 2722 as a proprietary hub interface bus to couple MCH 2716 to I / O controller hub (“ICH”) 2730. In at least one embodiment, ICH 2730 can provide direct connections to some I / O devices and a high-speed I / O bus to connect to other I / O devices. In at least one embodiment, the high-speed I / O bus can include, without limitation, a PCI Express bus or a revved version thereof. Examples can include, without limitation, audio controller 2729, firmware hub (“Flash BIOS”) 2728, wireless transceiver 2726, data storage 2724, legacy I / O controller 2723 containing user input 2725 and keyboard interface, serial expansion port 2777 (e.g., USB), and network controller 2734. Data storage 2724 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0301] In at least one embodiment, Figure 27 A system including interconnected hardware devices or “chips” is shown. In at least one embodiment, Figure 27 An exemplary SoC can be shown. In at least one embodiment, Figure 27 Devices shown in FIG. 27 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 2700 are interconnected using Compute Express Link (CXL) interconnects.

[0302] Figure 28 System 2800 according to at least one embodiment is shown. In at least one embodiment, system 2800 is an electronic device that utilizes processor 2810. In at least one embodiment, system 2800 can be, without limitation, a laptop, a tower server, a rack server, a blade server, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0303] In at least one embodiment, system 2800 can include, without limitation, processor 2810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 2810 is coupled using a bus or interface, such as I 2a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 28 A system is shown that includes interconnected hardware devices or “chips.” In at least one embodiment, Figure 28 An exemplary SoC can be shown. In at least one embodiment, Figure 28 Devices shown in FIG. 26 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 28 One or more components of FIG. 26 are interconnected using Compute Express Link (CXL) interconnects.

[0304] In at least one embodiment, Figure 28 may include a display 2824, a touchscreen 2825, a touchpad 2830, a near field communication unit (“NFC”) 2845, a sensor hub 2840, a thermal sensor 2846, an Express Chipset (“EC”) 2835, a Trusted Platform Module (“TPM”) 2838, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 2822, a DSP 2860, a solid state disk (“SSD”) or hard disk drive (“HDD”) 2820, a wireless local area network unit (“WLAN”) 2850, a Bluetooth unit 2852, a wireless wide area network unit (“WWAN”) 2856, a Global Positioning System (GPS) 2855, a camera (“USB 3.0 camera”) 2854 (e.g., a USB 3.0 camera), or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 2815 implemented in at least one embodiment in LPDDR3 standard. These components can each be implemented in any suitable manner.

[0305] In at least one embodiment, other components can be communicatively coupled to processor 2810 by components discussed above. In at least one embodiment, an accelerometer 2841, an ambient light sensor (“ALS”) 2842, a compass 2843, and a gyroscope 2844 can be communicatively coupled to a sensor hub 2840. In at least one embodiment, a thermal sensor 2839, a fan 2837, a keyboard 2846, and a touchpad 2830 can be communicatively coupled to EC 2835. In at least one embodiment, a speaker 2863, a headphone 2864, and a microphone (“mic”) 2865 can be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 2864, which in turn can be communicatively coupled to a DSP 2860. In at least one embodiment, audio unit 2864 can include, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 2857 can be communicatively coupled to a WWAN unit 2856. In at least one embodiment, components such as WLAN unit 2850 and Bluetooth unit 2852, as well as WWAN unit 2856, can be implemented in a next-generation form factor (NGFF).

[0306] Figure 29 An exemplary integrated circuit 2900, in accordance with at least one embodiment, is shown. In at least one embodiment, exemplary integrated circuit 2900 is a SoC, which can be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and can additionally include an image processor 2915 and / or a video processor 2920, any of which can be a modular IP core. In at least one embodiment, integrated circuit 2900 includes peripheral or bus logic including a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an I 2 S / I 2 C controller 2940. In at least one embodiment, integrated circuit 2900 can include a display device 2945 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2950 and a mobile industry processor interface (MIPI) display interface 2955. In at least one embodiment, storage can be provided by flash memory subsystem 2960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via a memory controller 2965 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2970.

[0307] Figure 30A computing system 3000 is shown in accordance with at least one embodiment. In at least one embodiment, the computing system 3000 includes a processing subsystem 3001 having one or more processor(s) 3002 and system memory 3004, which communicate via an interconnection path 3005 that can include a memory hub 3005. In at least one embodiment, the memory hub 3005 can be a separate component coupled with one or more processors 3002 via individual communication links 3007A to 3007N. In at least one embodiment, memory hub 3005 can be integrated into one or more processors 3002.

[0308] In at least one embodiment, processing subsystem 3001 includes one or more parallel processor(s) 3012 coupled to memory hub 3005 via a bus or other communication link 3013. In at least one embodiment, communication link 3013 can be one of many such links which can be implemented as standard system buses

[0309] In at least one embodiment, system storage 3014 can connect to I / O hub 3007 to provide storage mechanisms for computing system 3000. In at least one embodiment, I / O switches 3016 can be used to provide interface mechanisms to enable connections between I / O hub 3007 and other components such as network adapter 3018 and / or wireless network adapter 3019 that can be integrated into a platform, as well as various other devices that can be added via one or more add-in devices 3020. In at least one embodiment, network adapter 3018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 3019 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices that include one or more radios.

[0310] In at least one embodiment, computing system 3000 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and / or variations of the same, which can also connect to I / O hub 3007. In at least one embodiment, communication paths interconnecting various components in Figure 30 Communication paths interconnecting various components in at least one embodiment can use any suitable protocols including, for example, PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Express) or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect, or inter-integrated circuit (I2C) protocols).

[0311] In at least one embodiment, parallel processor(s) 3012 include circuitry optimized for graphics and video processing, in at least one embodiment including video codec circuitry for a unified shader core mode, and in at least one embodiment including circuitry optimized for general purpose processing. In at least one embodiment, parallel processor(s) 3012 include circuitry optimized for general purpose processing. In at least one embodiment, computation system 3000 can include one or more other system elements on a single integrated circuit or within a single package. In at least one embodiment, parallel processor(s) 3012, memory hub 3005, processor(s) 3002, and I / O hub 3007 can be integrated on a common integrated circuit, in at least one embodiment a system on a chip (SoC). In at least one embodiment, computation system 3000 can include at least a portion of a memory hub 3005 that is integrated within processor(s) 3002, in at least one embodiment within a central processing unit of the processor(s) 3002. In at least one embodiment, computation system 3000 can include one or more other system elements on a single integrated circuit or within a single package. In at least one embodiment, computation system 3000 can be integrated into a system on a package (SoP) configuration.

[0312] Processing system

[0313] The following figures set forth, without limitation, example processing systems that can be used to implement at least one embodiment.

[0314] Figure 31 An accelerated processing unit (“APU”) 3100, in accordance with at least one embodiment, is shown. In at least one embodiment, APU 3100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, APU 3100 can be configured to execute application programs such as CUDA programs. In at least one embodiment, APU 3100 includes, without limitation, core complex 3110, graphics complex 3140, fabric 3160, I / O interface 3170, memory controllers 3180, display controllers 3192, and multimedia engines 3194. In at least one embodiment, APU 3100 can include, without limitation, any combination of any number of core complexes 3110, any number of graphics complexes 3140, any number of display controllers 3192, and any number of multimedia engines 3194. For purposes of illustration, multiple instances of similar objects are represented in this document by reference characters identifying the object, and a number in parentheses identifying the instance needed.

[0315] In at least one embodiment, core complex 3110 is a CPU, graphics complex 3140 is a GPU, and APU 3100 is a processing unit that integrates, without limitation, 3110 and 3140 onto a single chip. In at least one embodiment, some tasks can be assigned to core complex 3110, while other tasks can be assigned to graphics complex 3140. In at least one embodiment, core complex 3110 is configured to execute host software associated with APU 3100, for example an operating system. In at least one embodiment, core complex 3110 is a master processor of APU 3100 that controls and coordinates the operations of the other processors. In at least one embodiment, core complex 3110 issues commands that control the operations of graphics complex 3140. In at least one embodiment, core complex 3110 can be configured to execute host executable code derived from CUDA source code, and graphics complex 3140 can be configured to execute device executable code derived from CUDA source code.

[0316] In at least one embodiment, core complex 3110 includes, without limitation, cores 3120(1)-3120(4) and L3 cache 3130. In at least one embodiment, core complex 3110 can include, without limitation, any combination of any number of cores 3120 and any number and type of caches. In at least one embodiment, cores 3120 are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core 3120 is a CPU core.

[0317] In at least one embodiment, each core 3120 includes, without limitation, a fetch / decode unit 3122, an integer execution engine 3124, a floating point execution engine 3126, and an L2 cache 3128. In at least one embodiment, fetch / decode unit 3122 fetches instructions, decodes such instructions, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 3124 and floating point execution engine 3126. In at least one embodiment, fetch / decode unit 3122 can concurrently dispatch one micro-instruction to integer execution engine 3124 and another micro-instruction to floating point execution engine 3126. In at least one embodiment, integer execution engine 3124 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 3126 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 3122 dispatches micro-instructions to a single execution engine in place of both integer execution engine 3124 and floating point execution engine 3126.

[0318] In at least one embodiment, each core 3120(i) has access to an L2 cache 3128(i) included in core 3120(i), where i is an integer representing a particular instance of core 3120. In at least one embodiment, each core 3120 included in core complex 3110(j) is connected to other cores 3120 included in core complex 3110(j) via an L3 cache 3130(j) included in core complex 3110(j), where j is an integer representing a particular instance of core complex 3110. In at least one embodiment, cores 3120 included in core complex 3110(j) have access to all L3 caches 3130(j) included in core complex 3110(j), where j is an integer representing a particular instance of core complex 3110. In at least one embodiment, L3 cache 3130 can include, without limitation, any number of slices.

[0319] In at least one embodiment, graphics complex 3140 can be configured to perform compute operations in a highly parallel manner. In at least one embodiment, graphics complex 3140 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometric calculations, and other operations associated with rendering images to a display. In at least one embodiment, graphics complex 3140 is configured to perform operations that are not graphics related. In at least one embodiment, graphics complex 3140 is configured to perform graphics related operations and operations that are not graphics related.

[0320] In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of graphics processing clusters 3130 and shared L2 cache 3132. In at least one embodiment, graphics processing clusters 3130 share shared L2 cache 3132. In at least one embodiment, shared L2 cache 3132 is partitioned among graphics processing clusters 3130. In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of graphics processing clusters 3130 and any number (including zero) and type of cache. In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of specialized graphics hardware.

[0321] In at least one embodiment, each graphics processing cluster 3130 includes, without limitation, any number of SIMD units 3132 and shared memory 3134. In at least one embodiment, each SIMD unit 3132 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each graphics processing cluster 3130 can execute any number of thread blocks, but each thread block executes on a single graphics processing cluster 3130. In at least one embodiment, a thread block includes, without limitation, any number of threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 3132 executes a different thread warp. In at least one embodiment, a thread warp is a group of threads (e.g., 16 threads), where each thread in a thread warp belongs to a single thread block and is configured to process a different set of data based on a single instruction set. In at least one embodiment, one or more threads in a thread warp can be disabled using predication. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3134.

[0322] In at least one embodiment, fabric 3160 is a system interconnect that facilitates data and control transmissions across core complex 3110, graphics complex 3140, I / O interface 3170, memory controllers 3180, display controller 3192, and multimedia engine 3194. In at least one embodiment, APU 3100 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 3160 that facilitate data and control transmissions across any number and type of directly or indirectly linked components that can be internal or external to APU 3100. In at least one embodiment, I / O interface 3170 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3170. In at least one embodiment, peripheral devices coupled to I / O interface 3170 can include, without limitation, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0323] In at least one embodiment, display controller 3192 displays images on one or more display devices, such as liquid crystal display (“LCD”) devices. In at least one embodiment, multimedia engine 3194 includes, without limitation, any number and type of multimedia-related circuitry, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers 3180 facilitate data transfers between APU 3100 and unified system memory 3190. In at least one embodiment, core complex 3110 and graphics complex 3140 share unified system memory 3190.

[0324] In at least one embodiment, APU 3100 implements a memory subsystem that includes, without limitation, any number and type of memory controllers 3180 and memory devices (e.g., shared memory 3154) that can be dedicated to one component or shared among multiple components. In at least one embodiment, APU 3100 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 2728, L3 cache 3130, and L2 cache 3142), each of which can be private to a component or shared among any number of components (e.g., core 3120, core complex 3110, SIMD unit 3152, compute unit 3150, and graphics complex 3140).

[0325] Figure 32A CPU 3200 is shown, in accordance with at least one embodiment. In at least one embodiment, CPU 3200 is developed by AMD Corporation, of Santa Clara, California. In at least one embodiment, CPU 3200 can be configured to execute application programs. In at least one embodiment, CPU 3200 is configured to execute host executable code derived from CUDA source code, and an external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU 3200 includes, without limitation, any number of core complexes 3210, fabric 3260, I / O interfaces 3270, and memory controllers 3280.

[0326] In at least one embodiment, core complex 3210 includes, without limitation, cores 3220(1)-3220(4) and L3 cache 3230. In at least one embodiment, core complex 3210 can include, without limitation, any number of cores 3220 and any combination and type of caches. In at least one embodiment, cores 3220 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 3220 is a CPU core.

[0327] In at least one embodiment, each core 3220 includes, without limitation, a fetch / decode unit 3222, an integer execution engine 3224, a floating point execution engine 3226, and an L2 cache 3228. In at least one embodiment, fetch / decode unit 3222 fetches instructions, decodes them, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 3224 and floating point execution engine 3226. In at least one embodiment, fetch / decode unit 3222 can dispatch one micro-instruction to integer execution engine 3224 and another micro-instruction to floating point execution engine 3226 simultaneously. In at least one embodiment, integer execution engine 3224 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 3226 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 3222 dispatches micro-instructions to a single execution engine in place of both integer execution engine 3224 and floating point execution engine 3226.

[0328] In at least one embodiment, each core 3220(i) has access to an L2 cache 3228(i) included in the core 3220(i), where i is an integer representing a particular instance of a core 3220. In at least one embodiment, each core 3220 included in a core complex 3210(j) is connected to other cores 3220 in the core complex 3210(j) via an L3 cache 3230(j) included in the core complex 3210(j), where j is an integer representing a particular instance of a core complex 3210. In at least one embodiment, a core 3220 included in a core complex 3210(j) has access to all L3 caches 3230(j) included in the core complex 3210(j), where j is an integer representing a particular instance of a core complex 3210. In at least one embodiment, an L3 cache 3230 can include, without limitation, any number of slices.

[0329] In at least one embodiment, fabric 3260 is a system interconnect that facilitates data and control transfers across core complexes 3210(1)-3210(N) (where N is an integer greater than zero), I / O interface 3270, and memory controllers 3280. In at least one embodiment, CPU 3200 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 3260 that facilitate data and control transfers across any number and type of directly or indirectly linked components that can be internal or external to CPU 3200. In at least one embodiment, I / O interface 3270 represents any number and type of I / O interface (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3270. In at least one embodiment, peripheral devices coupled to I / O interface 3270 can include, without limitation, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other types of game controller, a media recording device, an external storage device, a network interface card, etc.

[0330] In at least one embodiment, memory controllers 3280 facilitate data transfers between CPU 3200 and system memory 3290. In at least one embodiment, core complex 3210 and graphics complex 3240 share system memory 3290. In at least one embodiment, CPU 3200 implements a memory subsystem that includes, without limitation, any number and type of memory controllers 3280 and memory devices that can be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 3200 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 3228 and L3 cache 3230), each of which can be private to a component or shared among any number of components (e.g., core 3220 and core complex 3210).

[0331] Figure 33 An exemplary accelerator integration slice 3390 is shown in accordance with at least one embodiment. As used herein, a “slice” includes a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, an accelerator integration circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines that are part of graphics acceleration modules. Graphics processing engines can each comprise a separate GPU. Alternatively, graphics processing engines can include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module can be a GPU with a plurality of graphics processing engines. In at least one embodiment, a graphics processing engine can be a separate GPU integrated on a common package, line card, or chip as the CPU.

[0332] Application effective address space 3382 within system memory 3314 stores process elements 3383. In one embodiment, process elements 3383 are stored in response to GPU invocations 3381 from applications 3380 executing on processor 3307. Process elements 3383 contain processing state for corresponding applications 3380. Work descriptors (WDs) 3384 contained in process elements 3383 can be individual jobs requested by an application or can contain pointers to queues of jobs. In at least one embodiment, WDs 3384 are pointers to job request queues in application effective address space 3382.

[0333] Graphics acceleration module 3346 and / or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, there can be included infrastructure for setting up processing state and sending WDs 3384 to graphics acceleration module 3346 to start a job in a virtualized environment.

[0334] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns a graphics acceleration module 3346 or individual graphics processing engines. As graphics acceleration module 3346 is owned by a single process, a hypervisor initializes the accelerator integration circuit for the owning partition and an operating system initializes the accelerator integration circuit for the owning partition when graphics acceleration module 3346 is assigned.

[0335] In operation, a WD fetch unit 3391 in accelerator integration slice 3390 fetches a next WD 3384 including an indication of work to be completed by one or more graphics processing engines of graphics acceleration module 3346. Data from WD 3384 can be stored in registers 3345 used by memory management unit (MMU) 3339, interrupt management circuit 3347, and / or environment management circuit 3348, as shown. At least one embodiment of MMU 3339 includes segment / page walk circuitry to access segment / page tables 3386 within an OS virtual address space 3385. Interrupt management circuit 3347 can handle interrupt events (INTs) 3392 received from graphics acceleration module 3346. As graphics processing engines generate effective addresses 3393 when executing graphics operations, MMU 3339 translates those effective addresses to real addresses.

[0336] In one embodiment, the same set of registers 3345 are replicated for each graphics processing engine and / or graphics acceleration module 3346 and can be initialized by a system hypervisor or operating system. Each of these replicated registers can be included in accelerator integration slice 3390. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0337] Table 1 - Hypervisor Initialized Registers

[0338] 1 Slice Control Register 2 Real Address (RA) Plan Process Region Pointer 3 Authorization Mask Override Register 4 Interrupt Vector Table Input Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Log Pointer 9 Storage Description Register

[0339] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0340] Table 2 - Operating System Initialized Registers

[0341] 1 Process and Thread Identification 2 Effective Address (EA) Environment Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Log Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work Descriptor

[0342] In one embodiment, each WD 3384 is specific to a particular graphics acceleration module 3346 and / or a particular graphics processing engine. It contains all information needed for the graphics processing engine to do the work or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

[0343] Figures 34A-34B An exemplary graphics processor according to at least one embodiment is shown. In at least one embodiment, any of the exemplary graphics processors can be fabricated using one or more IP cores. In addition to the illustrated, in at least one embodiment, other logic and circuitry can be included, including additional graphics processor cores, peripheral interface controllers or general-purpose processor cores. In at least one embodiment, an exemplary graphics processor is used within an SoC.

[0344] Figure 34A An exemplary graphics processor 3410 of an SoC integrated circuit, according to at least one embodiment, can be fabricated using one or more IP cores. Figure 34B An additional exemplary graphics processor 3440 of an SoC integrated circuit, according to at least one embodiment, can be fabricated using one or more IP cores. In at least one embodiment, Figure 34A The graphics processor 3410 of FIG. 34A is a low power graphics processor core. In at least one embodiment, Figure 34B The graphics processor 3440 of FIG. 34B is a higher performance graphics processor core. In at least one embodiment, each graphics processor 3410, 3440 can be Figure 5 Variants of the graphics processor 510 of FIG. 5.

[0345] In at least one embodiment, the graphics processor 3410 includes a vertex processor 3405 and one or more fragment processor(s) 3415A-3415N (e.g., 3415A, 3415B, 3415C, 3415D, through 3415N-1, and 3415N). In at least one embodiment, the graphics processor 3410 can execute different shader programs via separate logic for vertex processing, hence the vertex processor 3405, and for fragment or pixel processing, hence one or more fragment processor(s) 3415A-3415N. In at least one embodiment, vertex processor 3405 executes operations to be performed for vertex shader programs, such as vertex processing operations and lighting operations. In at least one embodiment, one or more fragment processor(s) 3415A-3415N

[0346] In at least one embodiment, the graphics processor 3410 additionally includes one or more MMUs 3420A-3420B, caches 3425A-3425B, and circuit interconnects 3430A-3430B. In at least one embodiment, the one or more MMUs 3420A-3420B provide a mapping of virtual to physical addresses for the graphics processor 3410, including for the vertex processor 3405 and / or the fragment processors 3415A-3415N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 3425A-3425B. In at least one embodiment, the one or more MMUs 3420A-3420B may synchronize with other MMUs within the system, including with Figure 5 One or more MMUs associated with one or more application processors 505, graphics processor 515, and / or video processor 520 enable each processor 505-520 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 3430A-3430B enable the graphics processor 3410 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0347] In at least one embodiment, graphics processor 3440 includes Figure 34A 3420A-3420B, caches 3425A-3425B, and circuit interconnects 3430A-3430B of the graphics processor 3410. In at least one embodiment, the graphics processor 3440 includes one or more shader cores 3455A-3455N (e.g., 3455A, 3455B, 3455C, 3455D, 3455E, 3455F, through 3455N-1 and 3455N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 3440 includes an inter-core task manager 3445 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3455A-3455N and a tiling unit 3458 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0348] Figure 35AA graphics core 3500 is shown, in accordance with at least one embodiment. In at least one embodiment, graphics core 3500 can be included within graphics processor 2410 of FIG. 2. In at least one embodiment, graphics core 3500 can be a unified shader core 3455A-3455N in Figure 24 Figure 34B In at least one embodiment, graphics core 3500 includes shared instruction cache 3502, texture units 3518 and cache / shared memory 3520, which are common to execution resources within graphics core 3500. In at least one embodiment, graphics core 3500 can include multiple slices 3501A-3501N or partitions of each core, and graphics processor can include multiple instances of graphics core 3500. Slices 3501A-3501N can include support logic including a local instruction cache 3504A-3504N, a thread scheduler 3506A-3506N, a thread dispatcher 3508A-3508N, and a set of registers 3510A-3510N. In at least one embodiment, slices 3501A-3501N can include a set of additional functional units (AFUs) 3512A-3512N, floating point units (FPUs) 3514A-3514N, integer arithmetic logic units (ALUs) 3516A-3516N, address computation units (ACUs) 3513A-3513N, double precision FPUs (DPFPUs) 3515A-3515N, and matrix processing units (MPUs) 3517A-3517N.

[0349] In one embodiment, FPUs 3514A-3514N can perform single precision (32-bit) and half precision (16-bit) floating point operations, while DPFPUs 3515A-3515N can perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 3516A-3516N can perform variable precision integer operations in 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 3517A-3517N can also be configured for mixed precision matrix operations, including half precision floating point operations and 8-bit integer operations. In at least one embodiment, MPUs 3517A-3517N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 3512A-3512N can perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0350] Figure 35B ​A general purpose graphics processing unit (GPGPU) 3530 is shown in at least one embodiment. In at least one embodiment, GPGPU 3530 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 3530 can be configured to enable highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 3530 can be directly linked to other instances of GPGPU 3530 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 3530 includes a host interface 3532 to enable connection to a host processor. In at least one embodiment, host interface 3532 is a PCIe interface. In at least one embodiment, host interface 3532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 3530 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 3536A-3536H using a global scheduler 3534. In at least one embodiment, compute clusters 3536A-3536H share cache memory 3538. In at least one embodiment, cache memory 3538 may serve as a higher level cache for cache memory within compute clusters 3536A-3536H.

[0351] In at least one embodiment, GPGPU 3530 includes memory 3544A-3544B coupled to a compute cluster 3536A-3536H via a set of memory controllers 3542A-3542B. In at least one embodiment, memory 3544A-3544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0352] In at least one embodiment, computing clusters 3536A-3536H each include a set of graphics cores, such as Figure 35A The graphics core 3500, which may include multiple types of integer and floating-point logic units, can perform computational operations at various precisions, including computations suitable for use with CUDA programs. In at least one embodiment, at least a subset of the floating-point units in each compute cluster 3536A-3536H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0353] In at least one embodiment, multiple instances of GPGPU 3530 can be configured to operate as a compute cluster. In at least one embodiment, compute clusters 3536A-3536H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 3530 communicate via host interface 3532. In at least one embodiment, GPGPU 3530 includes an I / O hub 3539 that couples GPGPU 3530 to a GPU link 3540, enabling direct connection to other instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 3530 are located in separate data processing systems and communicate via a network device accessible via host interface 3532. In at least one embodiment, GPU link 3540 may be configured to connect to a host processor, in addition to or in place of host interface 3532. In at least one embodiment, GPGPU 3530 may be configured to execute CUDA programs.

[0354] Figure 36A A parallel processor 3600 in accordance with at least one embodiment is shown. In at least one embodiment, the various components of the parallel processor 3600 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0355] In at least one embodiment, parallel processor 3600 includes parallel processing unit 3602. In at least one embodiment, parallel processing unit 3602 includes an I / O unit 3604 that enables communication with other devices, including other instances of parallel processing unit 3602. In at least one embodiment, I / O unit 3604 can be directly connected to other devices. In at least one embodiment, I / O unit 3604 connects to other devices using a hub or switch interface (e.g., memory hub 605). In at least one embodiment, the connection between memory hub 605 and I / O unit 3604 forms a communication link. In at least one embodiment, I / O unit 3604 is connected to a host interface 3606 and a memory crossbar switch 3616, where host interface 3606 receives commands for performing processing operations and memory crossbar switch 3616 receives commands for performing memory operations.

[0356] In at least one embodiment, when host interface 3606 receives a command buffer via I / O unit 3604, host interface 3606 can direct a work operation to execute those commands to front end 3608. In at least one embodiment, front end 3608 is coupled with scheduler 3610, which is configured to assign commands or other work items to processing array 3612. In at least one embodiment, scheduler 3610 ensures that processing array 3612 is properly configured and in an active state before assigning tasks to processing array 3612 of processing array 3612. In at least one embodiment, scheduler 3610 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, microcontroller- implemented scheduler 3610 is configurable to perform complex scheduling and work distribution operations with both coarse and fine grain, enabling fast preemption and context switching of threads executing on processing array 3612. In at least one embodiment, host software can prove a workload for scheduling on processing array 3612 through one of a number of graphics processing doorbells. In at least one embodiment, workload can then be automatically distributed on processing array 3612 by scheduler 3610 logic within microcontroller that includes scheduler 3610.

[0357] In at least one embodiment, processing array 3612 can include up to “N” processing clusters (e.g., cluster 3614A, cluster 3614B, through cluster 3614N). In at least one embodiment, each cluster 3614A-3614N of processing array 3612 can execute a large number of concurrent threads. In at least one embodiment, scheduler 3610 can use various scheduling and / or work distribution algorithms to assign work to clusters 3614A-3614N of processing array 3612, which can vary depending on workload produced by each program or type of computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 3610, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing array 3612. In at least one embodiment, different clusters 3614A-3614N of processing array 3612 can be allocated for processing different types of programs or for performing different types of computations.

[0358] In at least one embodiment, processing array 3612 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 3612 is configured to perform general purpose parallel compute operations. In at least one embodiment, processing array 3612 can include logic to perform processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0359] In at least one embodiment, processing array 3612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 3612 can include additional logic to support performance of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, processing array 3612 can be configured to execute shader programs associated with graphics processing, for example, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 3602 can transfer data to be processed from a system memory over I / O unit 3604. In at least one embodiment, data can be stored to on-chip memory (e.g., parallel processor memory 3622) during processing, and then written back to system memory.

[0360] In at least one embodiment, when parallel processing unit 3602 is used to perform graphics processing, scheduler 3610 can be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations across multiple clusters 3614A-3614N of processing array 3612. In at least one embodiment, portions of processing array 3612 can be configured to perform different types of processing. In at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters 3614A-3614N can be stored in buffers to allow transmission of the intermediate data between clusters 3614A-3614N for further processing.

[0361] In at least one embodiment, processing array 3612 can receive processing tasks to be executed via scheduler 3610, which receives commands defining the processing tasks from front end 3608. In at least one embodiment, a processing task can include an index into data to be processed, for example, which can include surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 3610 can be configured to fetch the index corresponding to a task, or can receive the index from front end 3608. In at least one embodiment, front end 3608 can be configured to ensure that processing array 3612 is configured in an effective state before launching a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0362] In at least one embodiment, each of one or more instances of parallel processing unit 3602 can be coupled to a parallel processor memory 3622. In at least one embodiment, parallel processor memory 3622 can be accessed by the processing array 3612, as well as the I / O unit 3604, via a memory crossbar 3616. In at least one embodiment, memory crossbar 3616 can be used to transfer data between memory elements and the processing array 3612. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar.

[0363] In at least one embodiment, memory units 3624A-3624N can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 3624A-3624N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across memory units 3624A-3624N, allowing partition units 3620A-3620N to write portions of each rendering target in parallel to effectively use available bandwidth of parallel processor memory 3622. In at least one embodiment, local instances of parallel processor memory 3622 can be excluded in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0364] In at least one embodiment, any of clusters 3614A-3614N of processing array 3612 can process data that is to be written into any of memory units 3624A-3624N within parallel processor memory 3622. In at least one embodiment, memory crossbar 3616 can be configured to transmit outputs of each cluster 3614A-3614N to any partition unit 3620A-3620N or another cluster 3614A-3614N, which can perform other processing operations on the outputs. In at least one embodiment, each cluster 3614A-3614N can communicate with memory interface 3618 through memory crossbar 3616 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 3616 has a connection to memory interface 3618 to communicate with I / O unit 3604, as well as a local instance of parallel processor memory 3622, to enable processing elements within different processing clusters 3614A-3614N to communicate with system memory or other memory that is not local to the parallel processing elements 3602. In at least one embodiment, memory crossbar 3616 can use virtual channels to separate traffic streams between clusters 3614A-3614N and partition units 3620A-3620N.

[0365] In at least one embodiment, multiple instances of parallel processing unit 3602 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate in coordination with each other to enable single program multi-processing (SPMP). In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate as a single unit even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences.

[0366] Figure 36B Processing cluster 3694 is shown according to at least one embodiment. In at least one embodiment, processing cluster 3694 is included in a parallel processing unit. In at least one embodiment, processing cluster 3694 is a Figure 36Aone of the processing clusters 3614A-3614N. In at least one embodiment, processing cluster 3694 can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executed by a particular group of one or more processing clusters. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads with no or negligible context switching overhead. In at least one embodiment, Single Instruction Multiple Thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronous threads, using a common instruction unit configured to issue instructions to a group of processing engines within each processing cluster 3694.

[0367] In at least one embodiment, operation of processing cluster 3694 can be controlled via a pipeline manager 3632 that allocates processing tasks to SIMT parallel processor. In at least one embodiment, pipeline manager 3632 receives instructions from scheduler 3610, and manages execution of those instructions via graphics multiprocessor 3634 and / or texture unit 3636. In at least one embodiment, graphics multiprocessor 3634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures can be included within processing cluster 3694. In at least one embodiment, one or more instances of graphics multiprocessor 3634 can be included within processing cluster 3694. In at least one embodiment, graphics multiprocessor 3634 can process data, and a data crossbar 3640 can be used to distribute processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, pipeline manager 3632 can facilitate distribution by specifying destinations for processed data as a function of its origin. Figure 36A

[0368] In at least one embodiment, each graphics multiprocessor 3634 within processing cluster 3694 can include an identical set of functional execution logic (e.g., arithmetic logic units, load store units (LSUs), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, shift operations, and the like. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations using different control signals. Any combination of

[0369] ​In at least one embodiment, instructions delivered to processing cluster 3694 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines constitutes a warp. In at least one embodiment, a thread group is a group of threads executing the same program, although each thread within a thread group can be at different instruction points within the program. In at least one embodiment, a thread group is associated with a same set of instruction boundaries. In at least one embodiment, a thread group includes fewer threads than are available processing engines within graphics multiprocessor 3634. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines within graphics multiprocessor 3634 available to be invoked, one or more of the processing engines can be idle during a cycle when a thread group is not available; in at least one embodiment, graphics multiprocessor 3634 can be configured to handle multiple thread groups, with each thread group being allocated to “threads” (where threads in a thread group are concurrently executing instmctions on the processing engines).

[0370] In at least one embodiment, graphics multiprocessor 3634 includes internal cache memory, to perform load and store operations. In at least one embodiment, graphics multiprocessor 3634 can bypass internal cache and use cache memory within processing cluster 3694 (e.g., LI cache 3648). In at least one embodiment, each graphics multiprocessor 3634 can also have access to L2 Cache within a partition unit (e.g., partition units 3620A-3620N) that is shared among multiple processing clusters 3694 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 3634 can also have access to off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processor 3602 can be used as global memory. In at least one embodiment, processing cluster 3694 includes multiple instances of graphics multiprocessor 3634 that share common memory, which can be stored in LI cache 3648. Figure 36A

[0371] In at least one embodiment, each processing cluster 3694 can include an MMU 3645 configured to translate virtual addresses into physical addresses, as is known to those skilled in the art. In at least one embodiment, one or more instances of MMU 3645 can reside within graphics multiprocessor 3634. In at least one embodiment, graphics multiprocessor 3634 includes a cache memory 3648 to cache data stored in system memory. In at least one embodiment, graphics multiprocessor 3634 includes a shared memory 3650 to store data for threads executing on graphics multiprocessor 3634. Figure 36A ​In at least one embodiment, MMU 3645 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses at a granularity of a page row (e.g., 4K bytes). In at least one embodiment, MMU 3645 can include address translation lookaside buffers (TLBs) to improve translation speed by storing recently used virtual to physical mappings. In at least one embodiment, MMU 3645 can include a set of page table entries (PTEs) for mapping virtual addresses to physical addresses at a granularity of a cache line (e.g., 64 bytes). In at least one embodiment, MMU 3645 can reside in graphics processing cluster 3694, L1 cache 3648, or graphics multiprocessor 3634.

[0372] In at least one embodiment, processing cluster 3694 can be configured such that each graphics multiprocessor 3634 is coupled to a texture unit 3636 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data can be read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 3634 and cached in an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 3634 outputs processed tasks to data crossbar 3640 to provide processed task data to another processing cluster 3694 for further processing or to store processed task data in an L2 cache, local parallel processor memory, or system memory via memory crossbar 3616. Figure 36A In at least one embodiment, pre-Raster Operations Unit (preROP) 3642 is configured to receive data from graphics multiprocessor 3634, direct data to ROP unit in a graphics processing cluster 3694 that can be co-located with the partition units (e.g., partition units 3620A-3620N described herein) as described herein. In at least one embodiment, preROP 3642 can perform optimizations to minimize or eliminate bandwidth adjacency to color blending, organize pixel color data, and perform address translations.

[0373] Figure 36C A graphics multiprocessor 3696 according to at least one embodiment is shown. In at least one embodiment, graphics multiprocessor 3696 is a GPC as described herein. In at least one embodiment, graphics multiprocessor 3696 is a graphics processing cluster (GPC) as described herein. Figure 36Bgraphics processor 3634. In at least one embodiment, graphics processor 3696 couples with the pipeline manager 3632 of processing cluster 3694. In at least one embodiment, graphics processor 3696 has an execution pipeline that includes, without limitation, an instruction cache 3652, an instruction unit 3654, an address mapping unit 3656, a register file 3658, one or more GPGPU cores 3662, and one or more LSU(s) 3666. GPGPU cores 3662 and LSUs 3666 couple with cache memory 3672 and shared memory 3670 via a memory and cache interconnect 3668.

[0374] In at least one embodiment, instruction cache 3652 receives a stream of instructions 3650 to execute from pipeline manager 3632. In at least one embodiment, instructions are cached in instruction cache 3652 and dispatched for execution by instruction unit 3654. In one embodiment, instruction unit 3654 can dispatch instructions to the various functional units available on GPGPU cores 3662 including, but not limited to, floating point units 3664, and integer arithmetic logic units (ALUs). In at least one embodiment, GPGPU cores 3662 can also include dedicated graphics processing units (GPUs) for processing vertex operations, like loading indices support various graphics primitives.

[0375] In at least one embodiment, register file 3658 provides a set of registers for functional units of graphics processor 3696. In at least one embodiment, register file 3658 provides temporary storage for operands of the data paths connected to the functional units (e.g., GPGPU cores 3662, LSUs 3666) of graphics processor 3696. In at least one embodiment, register file 3658 is split into allocated portions among the various functional units. In at least one embodiment, register file 3658 is partitioned between different thread groups executing on graphics processor 3696.

[0376] In at least one embodiment, GPGPU cores 3662 can each include FPUs and / or ALUs for executing instructions for graphics processing. GPGPU cores 3662 can be similar to each other in architecture or can include a mixture of different GPGPU core architectures. In at least one embodiment, a first portion of GPGPU cores 3662 include single precision FPUs and integer ALUs, while a second portion of GPGPU cores include double precision FPUs. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics processor 3696 can additionally include one or more fixed function or special-purpose processing units to perform specific computational tasks such as rectangle

[0377] In at least one embodiment, GPGPU cores 3662 include SIMD logic capable of performing a single -instruction multiple-data (SIMD) operation. In at least one embodiment GPGPU cores 3662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute a SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, a SIMD instruction involves multiple data elements, which can be floating point data elements, integer data elements, or other data elements. In at least one embodiment, a single SIMD instruction can be performed on multiple different data elements in a single clock cycle, where the clock cycle is the reciprocal of the clock frequency. In at least one embodiment, GPGPU cores 3662 can be used for general-purpose computing, including but not limited to symmetric multiprocessing (SMP) or symmetric multi-threading (SMT). In at least one embodiment, GPGPU cores 3662 can be effective at coding and media processing tasks, such as those used in video encoding, logging, and other media processing tasks.

[0378] In at least one embodiment, memory and cache interconnect 3668 is an interconnect network that connects each functional unit of graphics multiprocessor 3696 to register file 3658 and shared memory 3670. In at least one embodiment, memory and cache interconnect 3668 is a crossbar interconnect that allows LSUs 3666 to implement load and store operations between shared memory 3670 and register file 3658. In at least one embodiment, register file 3658 can operate at same frequency as GPGPU cores 3662, resulting in very low latency for data transfers between GPGPU cores 3662 and register file 3658. In at least one embodiment, shared memory 3670 can be used to enable communication between threads executing on functional units within graphics multiprocessor 3696. In at least one embodiment, cache memory 3672 can be used to store data for threads executing on functional units and texture data for textures accessed by these threads. In at least one embodiment, shared memory 3670 can also be used as a program managed cache.

[0379] In at least one embodiment, parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU can be communicatively coupled to host processor / cores over a bus or other interconnect (e.g., a high-speed

[0380] General-Purpose Computing

[0381] The following figures illustrate, without limitation, exemplary software configurations used in general-purpose computing to implement at least one embodiment.

[0382] Figure 37A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL, or Intel One API.

[0383] In at least one embodiment, the programming platform's software stack 3700 provides an execution environment for applications 3701. In at least one embodiment, applications 3701 may include any computer software capable of being launched on the software stack 3700. In at least one embodiment, applications 3701 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0384] In at least one embodiment, application 3701 and software stack 3700 run on hardware 3707. In at least one embodiment, hardware 3707 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support programming platforms. In at least one embodiment, for example, using CUDA, software stack 3700 may be vendor-specific and compatible only with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, software stack 3700 can be used with devices from different vendors. In at least one embodiment, hardware 3707 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within hardware 3707, which may include but is not limited to a CPU (but may also include computing devices) and their memory, the devices within hardware 3707 may include but are not limited to GPUs, FPGAs, AI engines, or other computing devices (but may also include a CPU) and their memory.

[0385] In at least one embodiment, software stack 3700 of a programming platform includes, without limitation, a plurality of libraries 3703, a runtime 3705, and a device kernel driver 3706. In at least one embodiment, each of libraries 3703 can include data and programming code that can be used by computer programs and leveraged during software development. In at least one embodiment, libraries 3703 can include, without limitation, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, libraries 3703 include functions that are optimized for execution on one or more types of devices. In at least one embodiment, libraries 3703 can include, without limitation, functions for performing mathematical, deep learning, and / or other types of operations on a device. In at least one embodiment, libraries 3803 are associated with corresponding APIs 3802, which can include one or more APIs that expose functions implemented in libraries 3803.

[0386] In at least one embodiment, application 3701 is written as source code that is compiled into executable code, as discussed in more detail below with respect to FIG. 37B. Figure 42 In at least one embodiment, executable code of application 3701 can run, at least partially, on an execution environment provided by software stack 3700. In at least one embodiment, during execution of application 3701, code can be derived that needs to run on a device (as opposed to a host). In such a case, in at least one embodiment, runtime 3705 can be invoked to load and launch the necessary code on a device. In at least one embodiment, runtime 3705 can include any technically feasible runtime system capable of supporting execution of application 3701.

[0387] In at least one embodiment, runtime 3705 is implemented as one or more runtime libraries associated with corresponding APIs (which are shown as APIs 3704). In at least one embodiment, one or more such runtime libraries can include, without limitation, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions can include, without limitation, functions for allocating, deallocating, and copying device memory, as well as transferring data between host memory and device memory. In at least one embodiment, execution control functions can include, without limitation, functions for launching functions on a device (sometimes referred to as “kernels” when functions are global functions that can be called from a host), and functions for setting attribute values in buffers maintained by a runtime library for a given function to be executed on a device.

[0388] In at least one embodiment, the runtime library and corresponding API 3704 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0389] In at least one embodiment, the device kernel driver 3706 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 3706 can provide APIs such as API 3704 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 3706 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 3706 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the device kernel driver 3706 compiling the IR code at runtime.

[0390] Figure 38 According to at least one embodiment, Figure 37 3800. In at least one embodiment, the CUDA software stack 3800, on which the application 3801 can be launched, includes a CUDA library 3803, a CUDA runtime 3805, a CUDA driver 3807, and a device kernel driver 3808. In at least one embodiment, the CUDA software stack 3800 executes on hardware 3809, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0391] In at least one embodiment, the application 3801, the CUDA runtime 3805, and the device kernel driver 3808 can perform similar functions as the application 3701, the runtime 3705, and the device kernel driver 3706, respectively. Figure 37CUDA Driver 3807, which includes a library (libcuda.so) that implements the CUDA Driver API 3806. In at least one embodiment, similar to the CUDA Runtime API 3804 implemented by the CUDA Runtime Library (cudart), the CUDA Driver API 3806 can expose, without limitation, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability, among others. In at least one embodiment, the CUDA Driver API 3806 differs from the CUDA Runtime API 3804 in that the CUDA Runtime API 3804 simplifies device code management by providing implicit initialization, context (similar to a process) management, and module (similar to a dynamically loaded library) management. In contrast to the high-level CUDA Runtime API 3804, in at least one embodiment, the CUDA Driver API 3806 is a low-level API that provides more granular control over a device, particularly with respect to contexts and module loading. In at least one embodiment, the CUDA Driver API 3806 can expose functions for context management that are not exposed by the CUDA Runtime API 3804. In at least one embodiment, the CUDA Driver API 3806 is also language agnostic and supports, for example, OpenCL in addition to the CUDA Runtime API 3804. Further, in at least one embodiment, development libraries including the CUDA Runtime 3805 can be considered separate from driver components, including the user-mode CUDA Driver 3807 and the kernel-mode device driver 3808 (sometimes also referred to as a “display” driver).

[0392] In at least one embodiment, CUDA Libraries 3803 can include, without limitation, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that can be utilized by parallel computing applications, such as application 3801. In at least one embodiment, CUDA Libraries 3803 can include mathematical libraries such as a cuBLAS library, which is an implementation of basic linear algebra subprograms (“BLAS”) for performing linear algebra operations; a cuFFT library for computing fast Fourier transforms (“FFTs”), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA Libraries 3803 can include deep learning libraries such as a cuDNN library for primitives of deep neural networks and a TensorRT platform for high-performance deep learning inference, among others.

[0393] Figure 39 FIG. 39 shows a diagram of a system including a training data pipeline, in accordance with at least one embodiment Figure 37ROCm implementation of the software stack 3700. In at least one embodiment, the ROCm software stack 3900 on which the application 3901 can launch includes a language runtime 3903, a system runtime 3905, a thunk 3907, a ROCm kernel driver 3908, and a device kernel driver 3909. In at least one embodiment, the ROCm software stack 3900 executes on hardware 3909, which can include a GPU that supports ROCm, which was developed by AMD Corporation of Santa Clara, California.

[0394] In at least one embodiment, the application 3901 can perform similar functions as the application 3701 discussed above in conjunction with Figure 37 In at least one embodiment, the language runtime 3903 and the system runtime 3905 can perform similar functions as the runtime 3705 discussed above in conjunction with Figure 37 In at least one embodiment, the language runtime 3903 and the system runtime 3905 differ in that the system runtime 3905 is a language-agnostic runtime that implements the ROCr system runtime API 3904 and utilizes a Heterogeneous System Architecture (“HAS”) runtime API. In at least one embodiment, the HAS runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with AMD GPUs, including functions for memory management, execution control dispatching of kernels through the architecture, error handling, system and agent information, and runtime initialization and shutdown, among others. In at least one embodiment, the language runtime 3903 is an implementation of a language-specific runtime API 3902 layered on top of the ROCr system runtime API 3904 as compared to the system runtime 3905. In at least one embodiment, a language runtime API can include, without limitation, a Portable Compute Interface (“HIP”) language runtime API, a Heterogeneous Compute Compiler (“HCC”) language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with functionally similar versions of CUDA mechanisms, and in at least one embodiment, the HIP language runtime API includes functions similar to the CUDA runtime API 3804 discussed above in conjunction with Figure 38

[0395] ​In at least one embodiment, thunk (ROCt) 3907 is an interface that can be used to interact with underlying ROCm drivers 3908. In at least one embodiment, ROCm drivers 3908 are ROCk drivers, which are a combination of AMDGPU drivers and HAS kernel drivers (amdkfd). In at least one embodiment, AMDGPU drivers are device kernel drivers for GPUs developed by AMD that perform similar functions to those discussed above in connection with Figure 37 In at least one embodiment, HAS kernel drivers are drivers that allow different types of processors to more efficiently share system resources via hardware features.

[0396] In at least one embodiment, various libraries (not shown) can be included in ROCm software stack 3900 above language runtime 3903 and provide similar functionality to CUDA libraries 3803 discussed above in connection with Figure 38 In at least one embodiment, various libraries can include, but are not limited to, math, deep learning, and / or other libraries such as a hipBLAS library that implements similar functions to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, etc.

[0397] Figure 40 FIG. 39 illustrates an OpenCL implementation of software stack 3700 in accordance with at least one embodiment Figure 37 In at least one embodiment, OpenCL software stack 4000 on which application 4001 can be launched includes an OpenCL framework 4005, an OpenCL runtime 4006, and drivers 4007. In at least one embodiment, OpenCL software stack 4000 executes on hardware 4008 that is not vendor-specific. In at least one embodiment, because device is supported by different vendors, specific OpenCL drivers can be required to interoperate with hardware from such vendors.

[0398] In at least one embodiment, application 4001, OpenCL runtime 4006, device kernel drivers 4007, and hardware 4008 can perform similar functions to those discussed above in connection with Figure 37 In at least one embodiment, application 4001 also includes OpenCL kernels 4002 that have code to be executed on a device. In at least one embodiment, application 4001, runtime 4006, device kernel drivers 4007, and hardware 4008 can perform similar functions to those discussed above in connection with

[0399] In at least one embodiment, OpenCL defines a “platform” that allows a host to control devices connected to that host. In at least one embodiment, OpenCL framework provides a platform layer API and a runtime API, shown as platform API 4003 and runtime API 4005. In at least one embodiment, runtime API 4005 uses a context to manage execution of kernels on a device. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 4005 can use to manage that device’s command queues, program and kernel objects, shared memory objects, etc. In at least one embodiment, platform API 4003 exposes functions that allow device contexts to be used for selecting and initializing devices, submitting work to devices via command queues, enabling data transfers to and from devices, etc. Additionally, in at least one embodiment, OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0400] In at least one embodiment, compiler 4004 is also included in OpenCL framework 4005. In at least one embodiment, source code can be compiled offline before executing an application or online during execution of an application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 4004, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0401] Figure 41 Software supported by a programming platform is shown, according to at least one embodiment. In at least one embodiment, programming platform 4104 is configured to support various programming models 4103, middleware and / or libraries 4102, and frameworks 4101 that an application 4100 can rely on. In at least one embodiment, application 4100 can be an AI / ML application implemented using, for example, a deep learning framework (in at least one embodiment, MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIACollective Communications Library (“NCCL”), and / or NVIDIADeveloper Data Loading Library (“DALI”) CUDA libraries to provide accelerated computation on underlying hardware.

[0402] In at least one embodiment, the programming platform 4104 can be a combination of the above Figure 38 、 Figure 39 and Figure 40 In at least one embodiment, programming platform 4104 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, programming platform 4104 supports multiple programming models 4103, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, programming model 4103 can expose features of the underlying hardware to improve performance. In at least one embodiment, programming model 4103 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0403] In at least one embodiment, library and / or middleware 4102 provides an abstract implementation of programming model 4104. In at least one embodiment, such library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from programming platform 4104, such middleware also includes software that provides services to applications. In at least one embodiment, library and / or middleware 4102 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, library and / or middleware 4102 may include NCCL and ROCm communication collection library ("RCCL") library, which provides communication routines for GPU, MIOpen library for deep learning acceleration and / or intrinsic library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers and related algorithms.

[0404] In at least one embodiment, application framework 4101 relies on libraries and / or middleware 4102. In at least one embodiment, each application framework 4101 is a software framework for implementing a standard structure for application software. In at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0405] Figure 42 Compiled code is shown in accordance with at least one embodiment to Figures 37-40on one of the programming platforms. In at least one embodiment, compiler 4201 receives source code 4200, which includes both host code and device code. In at least one embodiment, compiler 42...

Claims

1. A heat recovery system for a data center cooling system, comprising: an absorption chiller comprising a generator vessel coupled to one or more computing components of a data center via a primary cooling loop to receive heat from a fluid returning from the one or more computing components; an auxiliary coolant associated with the auxiliary cooling circuit and operable to serve as said fluid; as well as One or more flow control valves associated with the auxiliary cooling circuit for enabling the auxiliary coolant to be diverted from the auxiliary cooling circuit to the heat recovery system and for returning the fluid to a cooling distribution unit (CDU) or to the one or more computing components.

2. The heat recovery system according to claim 1, further comprising: The generator vessel is maintained at a pressure below atmospheric pressure and is used to separate the absorbent material from the carrier material using the heat; a condenser for enabling condensation of the absorbent material; an evaporation region for enabling the absorbent material to undergo a phase change; as well as An absorber vessel for combining the phase-changed absorber material with recovered carrier material from the generator vessel.

3. The heat recovery system according to claim 1, further comprising: A flow path is provided for enabling further cooling of the fluid in the evaporation region of the absorption chiller.

4. The heat recovery system according to claim 1, further comprising: An inlet path from the heat recovery system for the fluid to the one or more computing components or to a cooling distribution unit (CDU), the CDU enabling waste heat in the fluid to be exchanged with a primary coolant of the primary cooling circuit associated with a chiller located externally relative to the data center.

5. The heat recovery system according to claim 1, further comprising: A first diversion of the auxiliary cooling circuit diverts the fluid from the one or more computing components to the heat recovery system, and a second diversion of the auxiliary cooling circuit enables the fluid to enter the one or more computing components.

6. The heat recovery system according to claim 1, further comprising: A carrier material and an absorbent material in a mixed solution in said generator vessel, said absorbent material being adapted to partially evaporate due to said heat from said fluid.

7. The heat recovery system according to claim 2, further comprising: The fluid causing heating of the contents of the generator vessel under the pressure, the absorption material adapted to evaporate in the generator vessel, the absorption material adapted to condense in a condenser, and the absorption material adapted to be remixed into a mixed solution in an absorber vessel, the carrier material adapted to carry the absorption material between the generator vessel and the absorber vessel.

8. The heat recovery system of claim 1 , further comprising: a first path for delivering the fluid to the generator vessel at a pressure below atmospheric pressure to heat the contents of the generator vessel; said cooling distribution unit; a second path for conveying a first portion of the fluid from the generator vessel to the cooling distribution unit; as well as A third path is provided for conveying a second portion of the fluid from the generator vessel to the one or more computing components.

9. A data center cooling system comprising: a generator vessel coupled to one or more computing components of a data center via a primary cooling loop to receive heat from a fluid returning from the one or more computing components, the generator vessel being included in an absorption chiller within a cooling system of the data center; an auxiliary coolant associated with the auxiliary cooling circuit and operable to serve as said fluid; as well as One or more flow control valves associated with the auxiliary cooling circuit for enabling diversion of the auxiliary coolant from the auxiliary cooling circuit to the generator vessel and for returning the fluid to a cooling distribution unit (CDU) or to the one or more computing components.

10. The data center cooling system of claim 9, further comprising: The generator vessel is maintained at a pressure below atmospheric pressure and is used to separate the absorbent material from the carrier material using the heat; a condenser for enabling condensation of the absorbent material; an evaporation region for enabling the absorbent material to undergo a phase change; as well as An absorber vessel for combining the phase-changed absorber material with recovered carrier material from the generator vessel.

11. The data center cooling system of claim 9, further comprising: A flow path is provided for enabling further cooling of the fluid in the evaporation region of the absorption chiller.

12. The data center cooling system of claim 9, further comprising: an inlet path from the generator vessel for the fluid to the one or more computing components or to a cooling distribution unit (CDU) of the data center, the CDU enabling waste heat in the fluid to be exchanged with a primary coolant of a primary cooling circuit associated with a chiller located externally relative to the data center.

13. The data center cooling system of claim 9, further comprising: a first path for delivering the fluid to the generator vessel at a pressure below atmospheric pressure to heat the contents of the generator vessel; said cooling distribution unit; a second path for conveying a first portion of the fluid from the generator vessel to the cooling distribution unit; A third path is provided for conveying a second portion of the fluid from the generator vessel to the one or more computing components.

14. A method for a data center liquid cooling system, comprising: providing a heat recovery system including an absorption chiller having a generator vessel; coupling the generator vessel to one or more computing components of a data center via a primary cooling loop to receive heat from a fluid returning from the one or more computing components; determining that fluid returning from the one or more computing components has a heat content that can be resolved by the absorption chiller; enabling the generator vessel to remove at least a portion of heat from the fluid; providing an auxiliary coolant associated with the auxiliary cooling circuit to be operable for use as the fluid; diverting the auxiliary coolant from the auxiliary cooling circuit to the heat recovery system; as well as The fluid is enabled to return to the cooling distribution unit (CDU) or to the one or more computing components.

15. The method of claim 14, further comprising: maintaining the pressure of the generator vessel below atmospheric pressure; using at least a portion of the heat to enable separation of the absorbent material from the carrier material; enabling a condenser to condense the absorbent material; enabling the evaporation region to induce a phase change in the absorbent material; as well as In an absorber vessel, the phase-changed absorbent material is combined with recycled carrier material from the generator vessel.

16. The method of claim 14, further comprising: This enables further cooling of the fluid in the evaporation region of the absorption chiller.

17. The method of claim 14, further comprising: Enabling an inlet path from the heat recovery system for the fluid to the one or more computing components or to a cooling distribution unit (CDU), the CDU enabling waste heat in the fluid to be exchanged with a primary coolant of a primary cooling circuit associated with a chiller located externally relative to the data center.

18. The method of claim 14, further comprising: providing a first diversion of an auxiliary cooling loop to return the fluid from the one or more computing components to the heat recovery system; as well as A second split of the auxiliary cooling loop is provided to enable the fluid to enter the one or more computing components.

19. The method of claim 15, further comprising: having a carrier material and an absorbent material in a mixed solution in the generator container; allowing the absorbent material to evaporate; as well as The carrier material is enabled to support the absorber material between the generator vessel and the absorber vessel.

20. The method of claim 15, further comprising: heating the contents of the generator vessel under the pressure using at least a portion of the heat; evaporating the absorbent material in the generator vessel; condensing the absorbent material in a condenser; as well as The absorber material is remixed with the carrier material in the absorber container.

21. The method of claim 14, further comprising: delivering the fluid to the generator vessel using a first path to heat the contents of the generator vessel at a pressure below atmospheric pressure; transferring a first portion of the fluid from the generator vessel to the cooling distribution unit (CDU) using a second pathway; as well as A second portion of the fluid is conveyed from the generator vessel to the one or more computing components using a third pathway.

22. The method of claim 14, further comprising: determining a first temperature of the fluid returned from the one or more computing components; determining a second temperature associated with separation of the absorbent material; as well as The absorption chiller is switched on for the fluid when the first temperature is within a threshold of the second temperature.

Images