A PCIE interface verification board, a test system and a test method

Abstract

The present invention provides a PCIE interface verification board, a test system and a test method. The PCIE interface verification board includes a circuit board and a first PCIE connector disposed on the circuit board. The first PCIE connector is plugged into the PCIE interface to be tested. At least one switching chip is disposed on the circuit board, and each switching chip is connected to the first PCIE connector. At least two second PCIE connectors are further disposed on the circuit board, and each second PCIE connector is connected to one switching chip. The at least two second PCIE connectors are plugged into multiple PCIE devices. The multiple PCIE devices correspond one-to-one to multiple PCIE ports configured by the PCIE interface to be tested, and at least one switching chip is used to configure each PCIE device to communicate with the corresponding PCIE port. It is possible to simultaneously test multiple PCIE ports configured by the PCIE interface to be tested under one configuration type, reduce the deviation between the test data and the actual application, and improve the accuracy and reliability of the test data. Reduce the number of times of testing PCIE ports, improve the test efficiency, and save time and effort.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a PCIE interface verification board, a test system, and a test method. Background Art

[0002] As an important component within a computer, the motherboard directly affects the computing and data transmission performance of the computer. A PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) slot is usually provided on the motherboard to plug in different PCIE devices. Generally, only one PCIE device can be plugged into one PCIE slot. However, when the channel width required by the PCIE device is less than the channel width of the PCIE slot, there will be a waste of the PCIE slot channels. In response to this, in the prior art, there is a design method of configuring multiple PCIE ports from one PCIE slot, and each PCIE port is connected to a PCIE device, thereby improving the waste of the PCIE slot channels.

[0003] Currently, when testing the design method of configuring multiple PCIE ports from one PCIE slot, the prior art still adopts the traditional test method. First, determine the configuration type of the multiple PCIE ports configured by the PCIE slot, and then only test one PCIE port at a time, and successively test all the PCIE ports under this configuration type. After that, change the configuration type of the multiple PCIE ports configured by the PCIE slot, and test all the PCIE ports under this new configuration type one by one. Since there are multiple configuration types of configuring multiple PCIE ports for one PCIE slot, and each configuration type includes multiple PCIE ports, the number of times of testing the PCIE ports increases geometrically, which is time-consuming and laborious, and the multiple PCIE ports configured by the entire PCIE slot cannot be tested simultaneously, resulting in a deviation between the test data and the actual application effect, thereby reducing the accuracy and reliability of the test data. Summary of the Invention

[0004] The present invention provides a PCIE interface verification board, a test system, and a test method to reduce the number of times of testing the PCIE ports, improve the test efficiency, save time and effort; and can also simultaneously test the multiple PCIE ports configured by the entire PCIE interface, reduce the deviation between the test data and the actual application effect, and improve the accuracy and reliability of the test data.

[0005] In a first aspect, the present invention provides a PCIE interface verification board, which is used to test a single PCIE interface that supports configuration as multiple PCIE ports. The PCIE interface verification board includes a circuit board and a first PCIE connector arranged on the circuit board, wherein the first PCIE connector is used to be plugged into the PCIE interface to be tested. At least one switching chip is arranged on the circuit board, and each switching chip is connected to the first PCIE connector. At least two second PCIE connectors are also arranged on the circuit board, each second PCIE connector is connected to a switching chip, and each switching chip is connected to at least one second PCIE connector. At least two second PCIE connectors are used to plug in multiple PCIE devices, each PCIE device is plugged into a second PCIE connector, and each second PCIE connector is plugged into at most one PCIE device. Multiple PCIE devices correspond one to one with multiple PCIE ports configured with the PCIE interface to be tested, and at least one switching chip is used to configure each PCIE device to communicate with the corresponding PCIE port.

[0006] In the above scheme, a PCIE interface verification board is designed as a switching device connecting the PCIE interface to be tested and multiple PCIE devices, so that at least one switching chip controls the conduction or disconnection between the first PCIE connector and each second PCIE connector, and configures each PCIE device to communicate with the corresponding PCIE port, so that multiple PCIE ports configured by the PCIE interface to be tested under a configuration type can be tested simultaneously, so that the test scenario is very close to the actual application scenario, thereby reducing the deviation between the test data and the actual application effect, and improving the accuracy and reliability of the test data. And because multiple PCIE ports under the same configuration type can be tested at the same time, there is no need to test a single PCIE port under the same configuration type one by one, which reduces the number of times the PCIE port is tested, improves the test efficiency, and saves time and effort.

[0007] In a specific implementation, the channel width of the first PCIE connector is equal to the channel width of the PCIE interface to be tested, so that the channel width of the first PCIE connector can completely cover the channel width of the PCIE interface to be tested, and the channel width of the first PCIE connector is not wasted. The channel widths of at least two second PCIE connectors are equal, so that when the PCIE device is plugged into at least two second PCIE connectors, each PCIE device can be plugged into any second PCIE connector at will, and the communication connection between each PCIE device and the corresponding PCIE port can be completed by simply identifying and pairing through the switching chip, so that no additional plug-in restrictions are required.

[0008] In a specific embodiment, the channel width of each second PCIE plug-in is equal to the channel width of the PCIE interface to be tested. Or the channel width of each second PCIE plug-in is half of the channel width of the PCIE interface to be tested. This enables the second PCIE plug-in to test the PCIE interface to be tested under all configuration types.

[0009] In a specific embodiment, the channel width of the PCIE interface to be tested is X4, X8, or X16. The channel width of each second PCIE plug-in is X2, X4, X8, or X16. This meets the requirements for testing common types of PCIE interfaces.

[0010] In a specific embodiment, a first interface and a storage module are further provided on the circuit board, both of which are connected to each switching chip. The first interface is used to receive configuration firmware and write the configuration firmware into the storage module. Each switching chip is used to run the configuration firmware in the storage module and control the conduction or disconnection of the first PCIE plug-in and each second PCIE plug-in, so as to configure each PCIE device to communicate with the corresponding PCIE port. This facilitates the saving and running of different types of configuration firmware.

[0011] In a specific embodiment, the storage module is a flash memory programmer, which can improve the running and reading speed of the configuration firmware and thus improve the test efficiency.

[0012] In a specific embodiment, a complex programmable logic device is further provided on the circuit board. The complex programmable logic device is connected to each switching chip to control the power-on, error alarm, presence detection, or reset of each switching chip. This is used to perform power-on, error alarm, presence detection, or reset on the switching chip.

[0013] In a specific embodiment, a second interface and a JTAG (Joint Test Action Group, an international standard test protocol) interface, both of which are connected to the complex programmable logic device, are further provided on the circuit board. Among them, the second interface is used to connect to the baseboard management controller on the main board to enable information interaction between the baseboard management controller and the complex programmable logic device. The JTAG interface is used to update the firmware in the complex programmable logic device. This is used to perform information interaction with the baseboard management controller on the main board during the test process and at the same time facilitate the update of the firmware in the complex programmable logic device.

[0014] In a specific embodiment, a clock buffer and a third interface connected to the clock buffer are also provided on the circuit board. The third interface is used to receive a clock signal generated by a central processor connected to the PCIE interface to be tested. The clock buffer is connected to each switching chip to transmit a clock signal to each switching chip. The multiple PCIE devices connected to the second PCIE connector adopt a homologous clock design, which is closer to the actual application scenario, further reduces the deviation between the test data and the actual application effect, and further improves the accuracy and reliability of the test data.

[0015] In a second aspect, the present invention further provides a PCIE interface test system. The PCIE interface test system includes a mainboard, a central processing unit located on the mainboard, and at least one PCIE interface to be tested located on the mainboard and connected to the central processing unit, wherein each PCIE interface to be tested supports configuration as a multi-PCIE port. The PCIE interface test system also includes any one of the above-mentioned PCIE interface verification boards, and a plurality of PCIE devices plugged into at least two second PCIE connectors.

[0016] In the above scheme, a PCIE interface verification board is designed as a switching device connecting the PCIE interface to be tested and multiple PCIE devices, so that at least one switching chip controls the conduction or disconnection between the first PCIE connector and each second PCIE connector, and configures each PCIE device to communicate with the corresponding PCIE port, so that multiple PCIE ports configured by the PCIE interface to be tested under a configuration type can be tested simultaneously, so that the test scenario is very close to the actual application scenario, thereby reducing the deviation between the test data and the actual application effect, and improving the accuracy and reliability of the test data. And because multiple PCIE ports under the same configuration type can be tested at the same time, there is no need to test a single PCIE port under the same configuration type one by one, which reduces the number of times the PCIE port is tested, improves the test efficiency, and saves time and effort.

[0017] In a third aspect, the present invention further provides a PCIE interface test method based on any one of the above-mentioned PCIE interface verification boards, the test method being used to test a single PCIE interface that supports configuration as multiple PCIE ports. The test method comprises: plugging the PCIE interface to be tested into a first PCIE connector; plugging multiple PCIE devices into at least two second PCIE connectors; and configuring each PCIE device to communicate with the corresponding PCIE port by at least one switching chip.

[0018] In the above solution, a PCIE interface verification board is designed as a transfer device for the connection between the PCIE interface to be tested and multiple PCIE devices. At least one switching chip controls the conduction or disconnection between the first PCIE connector and each second PCIE connector, and configures each PCIE device to communicate with the corresponding PCIE port. Thus, multiple PCIE ports configured by the PCIE interface to be tested under a certain configuration type can be tested simultaneously, making the test scenario very close to the actual application scenario, thereby reducing the deviation between the test data and the actual application effect, and improving the accuracy and reliability of the test data. Moreover, since multiple PCIE ports under the same configuration type can be tested simultaneously, there is no need to test each single PCIE port under the same configuration type one by one, reducing the number of times of testing PCIE ports, improving the test efficiency, and saving time and effort. Description of the Drawings

[0019] Figure 1 It is the overall topology block diagram of a PCIE interface verification board provided by an embodiment of the present invention;

[0020] Figure 2 It is the overall topology block diagram of another PCIE interface verification board provided by an embodiment of the present invention;

[0021] Figure 3 It is the topology diagram of a connection method of a switching chip provided by an embodiment of the present invention;

[0022] Figure 4 It is the topology diagram of a connection method of a complex programmable logic device provided by an embodiment of the present invention;

[0023] Figure 5 It is the schematic diagram of the working mode of a clock buffer provided by an embodiment of the present invention;

[0024] Figure 6 It is the configuration schematic diagram of multiple PCIE ports configured by a PCIE interface to be tested provided by an embodiment of the present invention.

[0025] Reference Signs:

[0026] 10 - Circuit board 11 - First PCIE connector 12 - Second PCIE connector

[0027] 20 - Switching chip 21 - First interface 22 - Storage module

[0028] 30 - Complex programmable logic device 31 - Second interface 32 - JTAG interface

[0029] 40 - Clock buffer 41 - Third interface 50 - Baseboard management controller Detailed Embodiment

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] To facilitate the understanding of the PCIE interface verification board provided by the embodiments of the present invention, the application scenario of the PCIE interface verification board provided by the embodiments of the present invention will be described first below. The PCIE interface verification board is used to test a single PCIE interface configured to support multiple PCIE ports. The PCIE interface to be tested is located on the main board and is connected to the central processing unit on the main board. The central processing unit configures multiple PCIE ports from the PCIE interface to be tested. The PCIE interface verification board will be described in detail below with reference to the accompanying drawings.

[0032] Refer to Figure 1 and Figure 2 The PCIE interface verification board provided by the embodiments of the present invention includes a circuit board 10 and a first PCIE connector 11 disposed on the circuit board 10. The first PCIE connector 11 is used to plug into the PCIE interface to be tested. At least one switching chip 20 is disposed on the circuit board 10, and each switching chip 20 is connected to the first PCIE connector 11. At least two second PCIE connectors 12 are further disposed on the circuit board 10. Each second PCIE connector 12 is connected to one switching chip 20, and each switching chip 20 is connected to at least one second PCIE connector 12. The at least two second PCIE connectors 12 are used to plug in multiple PCIE devices. Each PCIE device is plugged into one second PCIE connector 12, and each second PCIE connector 12 can plug in at most one PCIE device. The multiple PCIE devices correspond one-to-one to the multiple PCIE ports configured from the PCIE interface to be tested, and at least one switching chip 20 is used to configure each PCIE device to communicate with the corresponding PCIE port.

[0033] In the above solution, a PCIE interface verification board is designed as a transfer device for the connection between the PCIE interface to be tested and multiple PCIE devices. At least one switching chip 20 controls the conduction or disconnection between the first PCIE connector 11 and each second PCIE connector 12, configures each PCIE device to communicate with the corresponding PCIE port, so that multiple PCIE ports configured by the PCIE interface to be tested under one configuration type can be tested simultaneously, making the test scenario very close to the actual application scenario, thereby reducing the deviation between the test data and the actual application effect, and improving the accuracy and reliability of the test data. And because multiple PCIE ports under the same configuration type can be tested simultaneously, there is no need to test each single PCIE port under the same configuration type one by one, reducing the number of times of testing PCIE ports, improving the test efficiency, and saving time and effort. The following will introduce each of the above structures in detail with reference to the drawings.

[0034] When setting the circuit board 10, referring to Figure 1 , the circuit board 10, as a support and interconnection structure for setting devices such as PCIE connectors and switching chips 20, can use a printed circuit board 10 as the circuit board 10, set devices such as PCIE connectors and switching chips 20 on the circuit board 10, and interconnect them through traces and vias on or inside the circuit board 10.

[0035] As Figure 1 and Figure 2 shown, a first PCIE connector 11 is provided on the circuit board 10. The first PCIE connector 11 is used to plug and connect with the PCIE interface to be tested to realize the connection between the PCIE interface verification board and the PCIE to be tested. Among them, the channel width of the PCIE interface to be tested can be X4, X8 or X16, etc. When determining the channel width of the first PCIE connector 11, it is necessary to ensure that the channel width of the first PCIE connector 11 can completely cover the channel width of the PCIE interface to be tested. For example, the channel width of the first PCIE connector 11 can be made equal to the channel width of the PCIE interface to be tested to avoid wasting the channel width of the first PCIE connector 11. For example, as Figure 1 shown, the channel width of the first PCIE connector 11 is X16, and at this time the channel width of the PCIE interface to be tested is also X16. Of course, the channel width of the first PCIE connector 11 can also be made greater than the channel width of the PCIE interface to be tested to ensure that the channel width of the first PCIE connector 11 can completely cover the channel width of the PCIE interface to be tested.

[0036] Referring to Figure 1, at least one switching chip 20 is provided on the circuit board 10, and each switching chip 20 is connected to the first PCIE connector 11 to realize connection with the PCIE interface to be tested through the first PCIE connector 11. As Figure 1 shown, one switching chip 20 is provided on the circuit board 10; as Figure 2 shown, two switching chips 20 are provided on the circuit board 10. It should be understood that the number of switching chips 20 is not limited to 1 or 2. In addition, the number of switching chips 20 can also be any value not less than 3, such as 3, 4, etc. As Figure 1 and Figure 2 shown, at least two second PCIE connectors 12 are further provided on the circuit board 10. Each second PCIE connector 12 is connected to one switching chip 20, and each switching chip 20 is connected to at least one second PCIE connector 12. That is, the number of second PCIE connectors 12 connected to each switching chip 20 can be one, or any value not less than two, such as two, three, four, etc. However, each second PCIE connector 12 is only connected to one switching chip 20 and is not connected to other switching chips 20. When determining the number of second PCIE connectors 12, the number of second PCIE connectors 12 can be any value not less than 2, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, etc.

[0037] When determining the channel width of at least two second PCIE connectors 12, the channel widths of at least two second PCIE connectors 12 can be made equal. When the PCIE device is plugged into at least two second PCIE connectors 12, each PCIE device can be randomly plugged into one second PCIE connector 12, and only by identifying and pairing through the switching chip 20 can the communication connection between each PCIE device and the corresponding PCIE port be completed, thus eliminating the need for additional plugging restrictions. Of course, the channel widths of at least two second PCIE connectors 12 are not limited to the same setting method. In addition, other setting methods can also be adopted. For example, the channel widths of some second PCIE connectors 12 can be made equal, while the channel widths of some second PCIE connectors 12 are not equal; or the channel widths of all second PCIE connectors 12 are not equal.

[0038] In addition, the channel width of each second PCIE connector 12 can be made equal to the channel width of the PCIE interface to be tested, so as to ensure that the PCIE device can be plugged into each second PCIE connector 12. Of course, the channel width of each second PCIE connector 12 can also be half of the channel width of the PCIE interface to be tested, enabling the second PCIE connector 12 to test the PCIE interfaces to be tested under all configuration types. The channel width of each second PCIE connector 12 can be X2, X4, X8, or X16 to meet the requirements for testing common types of PCIE interfaces. It should be understood that the setting method of the channel width of the second PCIE connector 12 is not limited to the methods shown above. In addition, other setting methods can also be adopted.

[0039] The number of the second PCIE connectors 12 is specifically related to the central processor connected to the PCIE interface to be tested and the maximum number of PCIE ports that can be configured for the PCIE interface to be tested. In the optimal implementation, the number of the second PCIE connectors 12 needs to be at least not less than the maximum number of PCIE ports that the central processor can configure for the PCIE interface to be tested. Among them, the central processor directly determines the number of PCIE ports that the PCIE interface to be tested can be configured. As Figure 6 shown, the channel width of the PCIE interface to be tested is X16. The PCIE port types configured by the central processor for this PCIE interface to be tested can be X8, X4, X2, X1, etc. As Figure 6 shown, three PCIE ports with a channel width of X4 and two PCIE ports with a channel width of X2 are configured for the PCIE interface to be tested. For a PCIE interface to be tested with a channel width of n, if the minimum channel width of the PCIE ports that the central processor can configure for the PCIE interface to be tested is X2, then the PCIE interface to be tested can be configured with at most n / 2 PCIE ports, and it is necessary to ensure that the number of the second PCIE connectors 12 is as much as possible more than n / 2. If the minimum channel width of the PCIE ports that the central processor can configure for the PCIE interface to be tested is X1, then the PCIE interface to be tested can be configured with at most n PCIE ports, and it is necessary to ensure that the number of the second PCIE connectors 12 is as much as possible more than n.

[0040] The number of switching chips 20 is specifically related to the central processing unit connected to the PCIE interface to be tested and the maximum number of PCIE ports that can be configured for the PCIE interface to be tested. When the PCIE interface to be tested can be configured with more PCIE ports by the central processing unit, more switching chips 20 need to be set; when the PCIE interface to be tested can be configured with fewer PCIE ports by the central processing unit, fewer switching chips 20 can be set. In addition, the number of switching chips 20 is also related to the maximum number of ports supported by each switching chip 20. For example, some switching chips 20 support 4 downstream PCIE ports, and some switching chips 20 support 8 downstream PCIE ports. In the case of the same PCIE interface to be tested, due to the different numbers of downstream PCIE ports supported by different switching chips 20, the number of switching chips 20 used is also different.

[0041] During specific testing, at least two second PCIE connectors 12 are plugged with multiple PCIE devices. Each PCIE device is plugged on one second PCIE connector 12, and each second PCIE connector 12 can be plugged with at most one PCIE device. The multiple PCIE devices correspond one-to-one with the multiple PCIE ports configured for the PCIE interface to be tested, and at least one switching chip 20 configures each PCIE device to communicate with the corresponding PCIE port. By designing a PCIE interface verification board as a transfer device for the connection between the PCIE interface to be tested and multiple PCIE devices, at least one switching chip 20 configures each PCIE device to communicate with the corresponding PCIE port by controlling the conduction or disconnection between the first PCIE connector 11 and each second PCIE connector 12, so as to be able to simultaneously test the multiple PCIE ports configured for the PCIE interface to be tested under a certain configuration type, making the test scenario very close to the actual application scenario, thereby reducing the deviation between the test data and the actual application effect and improving the accuracy and reliability of the test data. And because multiple PCIE ports under the same configuration type can be tested simultaneously, there is no need to test each single PCIE port under the same configuration type one by one, reducing the number of times of testing PCIE ports, improving the test efficiency, and saving time and effort.

[0042] The following takes Figure 2 the channel width of the PCIE interface to be tested shown as X16, and there are two switching chips 20 arranged on the circuit board 10, and each switching chip 20 is connected with four second PCIE connectors 12 with a channel width of X16 as an example to show several configuration schemes.

[0043] Example 1, the central processing unit can Figure 2The to-be-tested PCIE interface configures 4 PCIE ports each with a channel width of X4. At this time, the number of PCIE devices plugged into the second PCIE connector 12 is also four, and the channel width of each PCIE device is also X4. Obviously, the X4 PCIE devices can be plugged into the X16 second PCIE connector 12. At this time, the four PCIE devices can be plugged into any four second PCIE connectors 12 under any one switching chip 20, so as to meet the requirement of simultaneously testing the 4 X4 PCIE ports configured by the to-be-tested PCIE interface. Of course, two PCIE devices can also be plugged into any two second PCIE connectors 12 under one switching chip 20, and the other two PCIE devices can be plugged into any two second PCIE connectors 12 under another switching chip 20, so as to meet the requirement of simultaneously testing the 4 X4 PCIE ports configured by the to-be-tested PCIE interface.

[0044] Example 2, the central processing unit can configure Figure 2 a to-be-tested PCIE interface as shown, with 1 PCIE port having a channel width of X4 and 6 PCIE ports having a channel width of X2. At this time, the number of PCIE devices plugged into the second PCIE connector 12 is seven. Among the seven PCIE devices, one PCIE device has a channel width of X4, and the other six PCIE devices have a channel width of X2. Obviously, the X4 or X2 PCIE devices can be plugged into the X16 second PCIE connector 12. At this time, four X2 PCIE devices can be plugged into four second PCIE connectors 12 under one switching chip 20, and the other two X2 PCIE devices and one X4 PCIE device can be plugged into any three second PCIE connectors 12 under another switching chip 20, so as to meet the requirement of simultaneously testing the 6 X2 and 1 X4 PCIE ports configured by the to-be-tested PCIE interface.

[0045] Refer to Figure 1 、 Figure 2 and Figure 3, a first interface 21 and a storage module 22 connected to each switching chip 20 can also be provided on the circuit board 10. Among them, the first interface 21 is used to receive the configuration firmware and write the configuration firmware into the storage module 22. Each switching chip 20 is used to run the configuration firmware in the storage module 22, and control the conduction or disconnection of the first PCIE plug-in 11 and each second PCIE plug-in 12, so as to configure each PCIE device to communicate with the corresponding PCIE port. This is convenient for saving and running different types of configuration firmware. When determining the storage module 22, a flash memory programmer can be used as the storage module 22 to improve the running and reading speed of the configuration firmware and improve the test efficiency. It should be understood that the storage module 22 is not limited to using a flash memory programmer. In addition, other types of storage media can also be used as the storage module 22. Reference Figure 1 , the switching chip 20 can be connected to the storage module 22 through interfaces such as but not limited to an SPI (Serial Peripheral Interface) interface. Continue to refer to Figure 1 , the first interface 21 can be interface types such as but not limited to an SDB (Smart Deep Buffer) interface, a UART (Universal Asynchronous Receiver / Transmitter) interface, etc.

[0046] Reference Figure 1 And Figure 4 , a complex programmable logic device 30 can also be provided on the circuit board 10. The complex programmable logic device 30 is connected to each switching chip 20 to control functions such as power-on, error alarm, in-position detection, or reset of each switching chip 20. Specifically, refer to Figure 1 , where PWR_PGD represents the power ground signal, PEX_ERROR_N represents the error alarm signal of the Nth switching chip 20, PRESENT_SLOT_N represents the in-position detection signal of the Nth second PCIE plug-in 12, PWEON_RST_PEX_N represents the restart power-on signal of the Nth switching chip 20, and RST_SLOT_N represents the reset signal of the Nth second PCIE plug-in 12. To power on, error alarm, in-position detect, or reset the switching chip 20, etc. In addition, as Figure 1 And Figure 4As shown, a second interface 31 and a JTAG interface 32, both connected to the complex programmable logic device 30, can be further provided on the circuit board 10. Among them, the second interface 31 is used to connect to the baseboard management controller 50 on the main board, enabling information interaction between the baseboard management controller 50 and the complex programmable logic device 30. The second interface 31 can adopt communication interfaces such as but not limited to the I2C interface. The JTAG interface 32 is used to update the firmware in the complex programmable logic device 30. When a JTAG interface is reserved on the main board, the JTAG interface 32 on the main board can be connected to the JTAG interface 32 on the PCIE interface verification board, so that the firmware in the complex programmable logic device 30 can be updated through the baseboard management controller 50 on the main board. Through the above method, information interaction with the baseboard management controller 50 on the main board can be achieved during the test, and at the same time, it is convenient to update the firmware in the complex programmable logic device 30.

[0047] Reference Figure 1 and Figure 5 , a clock buffer 40 and a third interface 41 connected to the clock buffer 40 can also be provided on the circuit board 10. Among them, the third interface 41 is used to receive the clock signal generated by the central processing unit connected to the PCIE interface to be tested. As Figure 1 shown, the CLK_100M (a kind of clock signal) output by the first interface 41 is transmitted to the clock buffer 40. And the clock buffer 40 is connected to each switching chip 20 to transmit the clock signal to each switching chip 20. That is, the switching chips 20 on the circuit board 10 and the PCIE devices connected to the downstream ports of the switching chips 20 adopt a common-source clock design, so that the CPU differential clock signal of the central processing unit is sequentially connected to the clock buffer 40 through the traces on the main board, the third interface 41, and the traces on the circuit board 10. Various types of CLK_100M output by the clock buffer 40 are then connected to the switching chips 20 and each second PCIE plug-in 12, thereby realizing the use of a common-source clock signal between the switching chips 20 and the PCIE devices. Specifically, various types of CLK_100M output by the clock buffer 40 can be such as Figure 1 shown CLK_100M_SLOT0~n (respectively representing the clock signals transmitted to different second PCIE plug-ins 12) and CLK_100M_PEX (representing the clock signal transmitted to the switching chip 20).

[0048] Making multiple PCIE devices connected to the second PCIE plug-in 12 adopt a common-source clock design is closer to the actual application scenario, further reducing the deviation between the test data and the actual application effect, and further improving the accuracy and reliability of the test data.

[0049] By designing a PCIE interface verification board as a transfer device for the connection between the PCIE interface to be tested and multiple PCIE devices, at least one switching chip 20 controls the conduction or disconnection between the first PCIE connector 11 and each second PCIE connector 12, configures each PCIE device to communicate with the corresponding PCIE port, so as to be able to simultaneously test multiple PCIE ports configured by the PCIE interface to be tested under a certain configuration type, making the test scenario very close to the actual application scenario, thereby reducing the deviation between the test data and the actual application effect, and improving the accuracy and reliability of the test data. And because multiple PCIE ports of the same configuration type can be tested simultaneously, there is no need to test each single PCIE port of the same configuration type one by one, reducing the number of times of testing PCIE ports, improving the test efficiency, and saving time and effort.

[0050] In addition, an embodiment of the present invention also provides a PCIE interface test system. The PCIE interface test system includes a main board, a central processing unit located on the main board, and at least one PCIE interface to be tested located on the main board and connected to the central processing unit. Specifically, the number of PCIE interfaces to be tested that can be included on the main board can be any number such as 1, 2, 3, 4, etc., and each PCIE interface to be tested supports being configured as multiple PCIE ports. Refer to Figure 1 and Figure 2 , the PCIE interface test system further includes any one of the above-mentioned PCIE interface verification boards, and multiple PCIE devices plugged into at least two second PCIE connectors 12. By designing a PCIE interface verification board as a transfer device for the connection between the PCIE interface to be tested and multiple PCIE devices, at least one switching chip 20 controls the conduction or disconnection between the first PCIE connector 11 and each second PCIE connector 12, configures each PCIE device to communicate with the corresponding PCIE port, so as to be able to simultaneously test multiple PCIE ports configured by the PCIE interface to be tested under a certain configuration type, making the test scenario very close to the actual application scenario, thereby reducing the deviation between the test data and the actual application effect, and improving the accuracy and reliability of the test data. And because multiple PCIE ports of the same configuration type can be tested simultaneously, there is no need to test each single PCIE port of the same configuration type one by one, reducing the number of times of testing PCIE ports, improving the test efficiency, and saving time and effort.

[0051] In addition, as described in the foregoing part of the PCIE interface verification board, refer to Figure 1 and Figure 4A baseboard management controller 50 may also be provided on the mainboard, so that the baseboard management controller 50 can be connected to the complex programmable logic device 30 on the circuit board 10 through the second interface 31 on the circuit board 10, so that the baseboard management controller 50 and the complex programmable logic device 30 can exchange information.

[0052] Furthermore, the present invention also provides a PCIE interface testing method based on any one of the above-mentioned PCIE interface verification boards, and the testing method is used to test a single PCIE interface that supports configuration of multiple PCIE ports. Figure 1 and Figure 2 , the test method includes:

[0053] Connecting the PCIE interface to be tested to the first PCIE connector 11;

[0054] Connecting multiple PCIE devices to at least two second PCIE connectors 12;

[0055] At least one switching chip 20 configures each PCIE device to communicate with the corresponding PCIE port. The specific implementation of configuring each PCIE device to communicate with the corresponding PCIE port is described in the above description of the PCIE interface verification board, which will not be repeated here.

[0056] By designing a PCIE interface verification board as a switching device connecting the PCIE interface to be tested and multiple PCIE devices, at least one switching chip 20 controls the conduction or disconnection between the first PCIE connector 11 and each second PCIE connector 12, and configures each PCIE device to communicate with the corresponding PCIE port, so that multiple PCIE ports configured by the PCIE interface to be tested under a configuration type can be tested simultaneously, so that the test scenario is very close to the actual application scenario, thereby reducing the deviation between the test data and the actual application effect, and improving the accuracy and reliability of the test data. And because multiple PCIE ports under the same configuration type can be tested at the same time, there is no need to test a single PCIE port under the same configuration type one by one, which reduces the number of times the PCIE port is tested, improves the test efficiency, and saves time and effort.

[0057] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A PCIE interface verification board for testing a single PCIE interface configured to support multiple PCIE ports, characterized in that, Including: A circuit board; A first PCIE connector disposed on the circuit board, the first PCIE connector being used for plugging into a to-be-tested PCIE interface, and the channel width of the first PCIE connector being equal to the channel width of the to-be-tested PCIE interface; At least one switching chip disposed on the circuit board; each switching chip is connected to the first PCIE connector; At least two second PCIE connectors disposed on the circuit board, each second PCIE connector connecting one of the switching chips, and each switching chip connecting at least one of the second PCIE connectors; Wherein, the at least two second PCIE connectors are used for plugging in a plurality of PCIE devices, each PCIE device being plugged into one of the second PCIE connectors, and each second PCIE connector plugging in at most one of the PCIE devices; The plurality of PCIE devices and the to-be-tested PCIE interface are configured to correspond to a plurality of PCIE ports one by one, and the at least one switching chip is used for controlling the conduction or disconnection between the first PCIE connector and each second PCIE connector, so as to configure each PCIE device to communicate with the corresponding PCIE port.

2. The PCIE interface verification board according to claim 1, characterized in that The channel widths of the at least two second PCIE connectors are equal.

3. The PCIE interface verification board according to claim 2, characterized in that The channel width of each second PCIE connector is equal to the channel width of the to-be-tested PCIE interface; or, The channel width of each second PCIE connector is half of the channel width of the to-be-tested PCIE interface.

4. The PCIE interface verification board according to claim 1, characterized in that The channel width of the to-be-tested PCIE interface is X4, X8 or X16; The channel width of each second PCIE connector is X2, X4, X8 or X16.

5. The PCIE interface verification board according to claim 1, characterized in that, A first interface and a storage module that are both connected to each switching chip are further disposed on the circuit board; The first interface is used for receiving configuration firmware and writing the configuration firmware into the storage module; Each switching chip is used for running the configuration firmware in the storage module, controlling the conduction or disconnection between the first PCIE connector and each second PCIE connector, so as to configure each PCIE device to communicate with the corresponding PCIE port.

6. The PCIE interface verification board according to claim 5, wherein The storage module is a flash memory programmer.

7. The PCIE interface verification board according to claim 1, characterized in that A complex programmable logic device is further disposed on the circuit board; The complex programmable logic device is connected to each switching chip to control the power-on, error alarm, presence detection or reset of each switching chip.

8. The PCIE interface verification board according to claim 7, characterized in that, A second interface and a JTAG interface that are both connected to the complex programmable logic device are further disposed on the circuit board; Wherein, the second interface is used for connecting to a baseboard management controller on a main board, so that the baseboard management controller and the complex programmable logic device perform information interaction; The JTAG interface is used for updating the firmware in the complex programmable logic device.

9. The PCIE interface verification board according to claim 1, wherein A clock buffer and a third interface connected to the clock buffer are further disposed on the circuit board; Wherein, the third interface is used for receiving a clock signal generated by a central processing unit connected to the to-be-tested PCIE interface; And the clock buffer is connected to each switching chip to transmit the clock signal to each switching chip.

10. A PCIE interface test system, characterized in that, Comprising: Motherboard; A central processing unit located on the motherboard; At least one PCIE interface to be tested located on the motherboard and connected to the central processing unit, wherein each PCIE interface to be tested supports being configured as multiple PCIE ports; The PCIE interface verification board according to any one of claims 1 to 9; Multiple PCIE devices plugged into the at least two second PCIE connectors.

11. A PCIE interface testing method based on the PCIE interface verification board according to any one of claims 1 to 9, which is used to test a single PCIE interface supporting configuration as multiple PCIE ports, and is characterized in that, Comprising: Plug the PCIE interface to be tested into the first PCIE connector; Plug multiple PCIE devices into at least two second PCIE connectors; At least one switching chip configures each PCIE device to communicate with the corresponding PCIE port.

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