Signal demodulation method, device, receiver and computer readable storage medium

Abstract

The application provides a signal demodulation method, device, receiver and computer readable storage medium. The method comprises: obtaining a first baseband envelope signal in a first symbol period; a logic level of the first baseband envelope signal is a normal bit level; obtaining a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period; determining an average value of the first baseband envelope signal to obtain a first average value; performing a direct current removal on the second baseband envelope signal according to the first average value to obtain a reference second signal; and determining a logic level of the second baseband envelope signal according to the reference second signal. The method can determine an abnormal bit level and improve the accuracy of logic level determination.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, and in particular to a signal demodulation method, device, receiver and computer readable storage medium. BACKGROUND

[0002] The principle of RFID (Radio Frequency Identification) is to achieve the purpose of identifying targets through non-contact data communication between a reader and a tag. The NFC (Near Field Communication) technology is generated from this, and devices using NFC can exchange data when close to each other, and is evolved from non-contact radio frequency identification and interconnection technology.

[0003] In the determination of the logic level of a signal, a traditional method uses a sliding average method to obtain a threshold value, in which three groups of 64 continuous data shift registers are used to obtain the average values of the three groups of data, so as to determine the logic level of the signal. The traditional demodulation method cannot accurately detect abnormal logic levels of a signal. SUMMARY

[0004] Therefore, it is necessary to provide a signal demodulation method, device, receiver and computer readable storage medium in view of the above technical problems.

[0005] A signal demodulation method, the method comprising:

[0006] obtaining a first baseband envelope signal in a first symbol period; the logic level of the first baseband envelope signal is a normal bit level;

[0007] obtaining a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period;

[0008] determining the average value of the first baseband envelope signal to obtain a first average value;

[0009] performing direct current processing on the second baseband envelope signal according to the first average value to obtain a reference second signal;

[0010] determining the logic level of the second baseband envelope signal according to the reference second signal.

[0011] A signal demodulation device, the device comprising:

[0012] a baseband envelope signal monitoring module, configured to obtain a first baseband envelope signal in a first symbol period; the logic level of the first baseband envelope signal is a normal bit level;

[0013] The baseband envelope signal monitoring module is further configured to acquire a second baseband envelope signal in a second symbol period, the second symbol period being a backward period of the first symbol period.

[0014] The DC removing module is configured to determine an average value of the first baseband envelope signal, and obtain a first average value.

[0015] The DC removing module is further configured to perform DC removing processing on the second baseband envelope signal according to the first average value, and obtain a reference second signal.

[0016] The symbol determining module is configured to determine a logic level of the second baseband envelope signal according to the reference second signal.

[0017] In one of the embodiments, the signal demodulation apparatus further comprises a digital rectifying module and a digital channel filtering module; the digital rectifying module is configured to acquire a modulation signal in a first symbol period, and rectify the modulation signal in the first symbol period to obtain a double-frequency modulation carrier signal; and the digital channel filtering module is configured to filter the double-frequency modulation carrier signal to obtain a first baseband envelope signal in the first symbol period.

[0018] In one of the embodiments, the digital channel filtering module is configured to filter the double-frequency modulation carrier signal through a cascaded integral comb filter to obtain the first baseband envelope signal in the first symbol period.

[0019] In one of the embodiments, the digital channel filtering module is configured to filter the double-frequency modulation carrier signal through a cascaded integral comb filter to obtain a filtered double-frequency modulation carrier signal.

[0020] When the communication protocol adopted by the modulation signal is a preset communication protocol, the filtered double-frequency modulation carrier signal is down-sampled through a down-sampling filter to obtain the first baseband envelope signal in the first symbol period.

[0021] A receiver comprises a memory and a processor, the memory stores a computer program, and the processor implements the steps of the method of each embodiment of the application when executing the computer program.

[0022] A computer readable storage medium, which stores a computer program, the computer program is executed by a processor to implement the steps of the method of each embodiment of the application.

[0023] The signal demodulation method, device, receiver and computer readable storage medium in the embodiment are particularly important in determining the determination threshold for determining the logic level due to the existence of the DC component, and since the logic level of the first baseband envelope signal is the normal bit level, the logic level of the second baseband envelope signal is determined by determining the average value of the first baseband envelope signal, obtaining the first average value, and performing DC removal on the second baseband envelope signal according to the first average value to obtain the reference second signal, that is, the average value of the signal based on the normal bit level is removed from the DC, the logic level of the second baseband envelope signal is determined, and the abnormal bit level is determined, thereby improving the accuracy of the logic level determination. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A front-end analog circuit block diagram of the signal demodulation method in one embodiment;

[0025] Figure 2 A demodulation waveform of the front-end analog circuit in one embodiment;

[0026] Figure 3 A schematic diagram of the ADC conversion waveform in one embodiment;

[0027] Figure 4 A synchronization timing diagram of the I and Q ASK modulation signals in one embodiment;

[0028] Figure 5 A waveform diagram of the bit type in one embodiment;

[0029] Figure 6 A timing diagram of the DC component removal signal in one embodiment;

[0030] Figure 7 A timing diagram of the DC component removal signal in another embodiment;

[0031] Figure 8 A flowchart of the signal demodulation method in one embodiment;

[0032] Figure 9 A waveform diagram of sampling the subcarrier in one embodiment;

[0033] Figure 10 A timing diagram of the DC component removal signal of the end bit signal in one embodiment;

[0034] Figure 11 A timing diagram of the DC component removal signal of the conflict bit signal in one embodiment;

[0035] Figure 12 A principle block diagram of the in-phase and quadrature integration type bit synchronization circuit in one embodiment;

[0036] Figure 13Timing diagram of the decision output of the in-phase quadrature integral type phase synchronization circuit in one embodiment;

[0037] Figure 14 Waveform diagram of the modulation signal rectification in one embodiment;

[0038] Figure 15 Waveform diagram of the low-pass filtering in one embodiment;

[0039] Figure 16 Structural diagram of the second-order CIC filter in one embodiment;

[0040] Figure 17 Waveform diagram of the baseband envelope signal in one embodiment;

[0041] Figure 18 Structural block diagram of the signal demodulation apparatus in one embodiment;

[0042] Figure 19 Structural block diagram of the signal demodulation apparatus in another embodiment;

[0043] Figure 20 Flowchart of the signal demodulation method in another embodiment;

[0044] Figure 21 Waveform diagram of the digital signal demodulation in one embodiment. DETAILED DESCRIPTION

[0045] It should be understood that the specific embodiments described herein merely exemplify the application and do not limit the application.

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0047] It should be noted that all the directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings). If the specific posture changes, the directionality indications also change accordingly. The connection can be direct connection or indirect connection.

[0048] Furthermore, references to "first," "second," and so on in this disclosure are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features designated as "first" or "second" may explicitly or implicitly include at least one such feature. For ease of understanding, "first" in each embodiment may be considered to relate to the first baseband envelope signal, and "second" may be considered to relate to the second baseband envelope signal.

[0049] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0050] In one embodiment, Figure 1 FIG. 1 is a block diagram of a front-end analog circuit of a signal demodulation method in one embodiment, including a contactless tag 110 and a receiver 120. The communication protocols supported by the contactless tag 110 include, but are not limited to, ISO 1443A and ISO 15693. Figure 1 The receiver 120 in the figure is a circuit block diagram of the receiver analog front end. It includes an integrator, a bandpass filter, a gain amplifier, and an ADC (Analog to Digital Convertor) connected in sequence. The subcarrier with a frequency of 13.56MHz (megahertz) is multiplied by the mutually orthogonal 13.56MHz I and Q sampling clocks. The sampled signal is passed to the bandpass filter to filter out the subcarrier component and out-of-band noise. After amplification by the gain amplifier, the two ASK modulated carrier signals of 848KHz (kilohertz) I and Q are obtained. Figure 2 1 and 2 are demodulated waveforms of a front-end analog circuit in one embodiment, including (a) a subcarrier waveform, (b) an I-channel sampling waveform, and (c) a Q-channel sampling waveform.

[0051] The 848KHz I and Q ASK modulated carrier signals are converted by the ADC and quantized into 4-bit data. Figure 3 Schematic diagram of ADC conversion waveform in one embodiment. Figure 3 (b) Figure 2 (b) The I-channel sampling waveform. Figure 3 (c) Figure 2 (c) Q-path sampling waveform. Figure 3 The ADC sampling clock is also included. Figure 3 (d) shows the ADC data of channel 1. Figure 3 (e) shows the Q-channel ADC data.

[0052] like Figure 4 Figure 2 shows a timing diagram for synchronizing I and Q ASK modulated signals in one embodiment. The I and Q ADC sampling clocks are inverted 6.78 MHz clocks. Before digital signal processing, the 4-bit I and Q data is synchronized to the 27.12 MHz digital clock domain. The following embodiments use the synchronized I and Q channels as an example.

[0053] In one embodiment, the ASK baseband envelope signal contains a DC component. In digital circuits, the DC component is the mean value of the baseband envelope signal. Removing the DC component involves subtracting the mean value from the level of the baseband envelope signal, so that the high level of the baseband envelope signal falls within the positive integer domain and the low level falls within the negative integer domain. Therefore, the baseband data can be determined by removing the DC component from the baseband envelope signal.

[0054] In one symbol period, three bit types must be identified: valid data bit, end bit (maintained low level in one symbol period) and conflict bit (high level in one symbol period). Figure 5 FIG. 1 is a waveform diagram of a bit type in an embodiment. Figure 5 (a) is the waveform of the valid data bit. Figure 5 (b) is the waveform of the end bit. Figure 5 (c) is the waveform of the conflicting bit.

[0055] like Figure 6 FIG. 1 is a timing diagram of removing a DC component signal in an embodiment. Figure 6 (a) is the baseband envelope signal, the first bit represents the baseband envelope signal of the first cycle, and so on. Figure 6 (b) is the baseband envelope signal delayed by one symbol period. Figure 6 (c) is the average value of the baseband envelope signal. Figure 6 (d) is the signal after removing the DC component.

[0056] Here's how it works:

[0057] Since the average value of the bits needs to be calculated in advance, the baseband envelope signal needs to be delayed by one symbol period (ie, 16 sampling periods). At the same time, the baseband signal monitoring will not destroy the integrity of the baseband envelope signal.

[0058] When in the signal monitoring stage, the baseband envelope signal ( Figure 6 (a)) can calculate the mean of the first bit ( Figure 6(c)). Wherein, the mean of the 1st bit is the direct current component of the 1st bit. When removing the direct current component of the 1st bit, the 1st bit signal of the baseband envelope signal delayed for one symbol period is subtracted by the direct current component of the 1st bit signal, so as to obtain the 1st bit signal of the direct current component removed signal. While removing the direct current component of the 1st bit signal, the direct current component of the 2nd bit is calculated in advance from the baseband envelope signal (a), and other bits are calculated in the same way. Figure 6

[0059] If the above method is used to remove the direct current of the ending bit and the conflict bit, the ending bit and the conflict bit after the direct current removal fluctuate around zero. As shown in Figure 7 Figure 7 It can be seen that if the ending bit and the conflict bit are removed by the direct current in the way as shown in Figure 6 It can be seen that if the ending bit and the conflict bit are removed by the direct current in the way as shown in

[0060] In an embodiment, as shown in Figure 8 the flowchart of the signal demodulation method in an embodiment is shown. Taking the method applied to the receiver as an example, the method comprises the following steps.

[0061] In step 802, a first baseband envelope signal in a first symbol period is obtained; the logic level of the first baseband envelope signal is a normal bit level.

[0062] Wherein, the first symbol period can refer to the current processing period of the receiver. For example, the first symbol period includes but is not limited to the first period, the second period, etc.

[0063] The first baseband envelope signal can be a first ASK baseband envelope signal. The first ASK baseband envelope signal can be obtained after the first ASK modulated signal is rectified and filtered. The first baseband envelope signal can be obtained by the signal received through the ISO1443A or ISO15693 communication protocol. The first baseband envelope signal can be the signal of the first envelope protrusion or the ASK baseband envelope signal after the first envelope protrusion. The first baseband envelope signal can be a digital signal. Specifically, the receiver obtains the I-channel ASK modulated signal and the Q-channel ASK modulated signal with synchronized timing; determines the signal strength of the I-channel ASK modulated signal and the signal strength of the Q-channel ASK modulated signal; determines the ASK modulated signal with stronger signal strength from the signal strength of the I-channel ASK modulated signal and the signal strength of the Q-channel ASK modulated signal; and obtains the first baseband envelope signal in the first symbol period according to the ASK modulated signal with stronger signal strength.

[0064] ​​In this embodiment, as shown in Figure 9 is a waveform diagram of sampling sub-carriers in an embodiment. Figure 9 The white dots represent the sampling time of I channel, and the black dots represent the sampling time of Q channel. The analog front end samples the sub-carriers. Since the sampling points are random, there are four possibilities of the sampling results.

[0065] As shown in Figure 9 (a), the I channel sampling obtains an 848 KHz modulated carrier, and the Q channel obtains no modulated carrier. Then, the signal with stronger signal strength is the I channel modulated signal. Therefore, the first baseband signal in the first symbol period is obtained from the I channel modulated signal.

[0066] As shown in Figure 9 (b), the I channel obtains no modulated carrier, and the Q channel sampling obtains an 848 KHz modulated carrier. Then, the signal with stronger signal strength is the Q channel modulated signal. Therefore, the first baseband signal in the first symbol period is obtained from the Q channel modulated signal.

[0067] As shown in Figure 9 (c), both the I channel and the Q channel have 848 KHz modulated carriers, and the signal strength of the I channel modulated signal > the signal strength of the Q channel modulated signal. Therefore, the first baseband signal in the first symbol period is obtained from the I channel modulated signal.

[0068] As shown in Figure 9 (d), both the I channel and the Q channel have 848 KHz modulated carriers, and the signal strength of the I channel modulated signal < the signal strength of the Q channel modulated signal. Therefore, the first baseband signal in the first symbol period is obtained from the Q channel modulated signal.

[0069] Step 804, obtaining a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period.

[0070] Specifically, the second symbol period is a backward period of the first symbol period. Specifically, the second symbol period can be the next period of the first symbol period. The second baseband envelope signal can be a second ASK baseband envelope signal. The second ASK baseband envelope signal can be obtained after the second ASK modulated signal is rectified and filtered. The second baseband envelope signal can be obtained from a signal received through ISO1443A or ISO15693 communication protocol.

[0071] Similarly, the receiver obtains the second baseband envelope signal in the second symbol period from the ASK modulated signal with stronger signal strength. The second baseband envelope signal in the second symbol period can be a digital signal.

[0072] Step 806, determining the average value of the first baseband envelope signal to obtain a first average value.

[0073] Specifically, the receiver integrates and averages the first baseband envelope signal to obtain a first average.

[0074] At step 808, the second baseband envelope signal is DC-removed according to the first average to obtain a reference second signal.

[0075] The DC-removal is to remove the DC component signal. The reference second signal is specifically the second baseband envelope signal after the DC removal by the first average. The baseband envelope signal contains the DC component, and the DC component is the average of the baseband envelope signal. The DC removal is to subtract the average from the baseband envelope signal, so that the high level of the baseband signal is in the positive integer domain, and the low level is in the negative integer domain. Therefore, the baseband envelope signal after the DC removal can determine the baseband data.

[0076] Specifically, the receiver subtracts the first average from the signal level value in the second baseband signal to obtain the reference second signal.

[0077] In one embodiment, as shown in FIG. 8, a timing diagram for removing the DC component signal of the end bit signal in one embodiment is shown. Figure 10 Figure 10 (a) is the obtained baseband envelope signal. Figure 10 (b) is the baseband envelope signal delayed by one symbol period. Figure 10 (c) is the bit average of the baseband envelope signal of (a). The bit average is the average of the signal in one symbol period. Figure 10 (d) is the bit average of the baseband envelope signal after the delay of one symbol period. Figure 10 (e) is the baseband envelope signal after the DC component signal is removed and delayed by one symbol period. That is, Figure 10 (e) is the baseband envelope signal after the DC component signal is removed and delayed by one symbol period. That is, Figure 10 (e) is the signal obtained by subtracting the signal of (d) from the signal of (b). For example, Figure 10 (e) is the signal obtained by subtracting the signal of (d) from the signal of (b). For example, Figure 10 (e) is the signal obtained by subtracting the signal of (d) from the signal of (b). For example, Figure 10 The nth bit signal in (e) is obtained by subtracting the bit average of the (n-1)th bit in (d) from the nth bit signal in (b). Other signals are calculated in the same way. Wherein, the nth bit signal can be regarded as the second baseband envelope signal, the (n-1)th bit is the first baseband envelope signal, and the (n-1)th bit average is the first average. Then at the end bit, the average of the nth bit is used for DC removal, and then the logic level is determined, so the end bit can be determined. Figure 10 Figure 10 In one embodiment, as shown in FIG. 9, a timing diagram for removing the DC component signal of the conflict bit signal in one embodiment is shown.

[0078] In one embodiment, as shown in FIG. 9, a timing diagram for removing the DC component signal of the conflict bit signal in one embodiment is shown. Figure 11 Figure 11 ​​​(a) is the baseband envelope signal obtained. Figure 11 (b) is the baseband envelope signal delayed by one symbol period. Figure 11 (c) is the baseband envelope signal delayed by one symbol period. Figure 11 (a) is the bit average of the baseband envelope signal. The bit average is the average of the electrical values in one symbol period. Figure 11 (d) is the bit average of the baseband envelope signal delayed by one symbol period. Figure 11 (e) is the baseband envelope signal delayed by one symbol period after removing the DC component signal. That is Figure 11 (e) is the baseband envelope signal delayed by one symbol period. Figure 11 (b) minus Figure 11 (d) is obtained. For example, Figure 11 The (n-a+1)th bit signal in (e) is Figure 11 The (n-a+1)th bit signal in (b) minus Figure 11 The (n-a)th bit average in (d). Other signals are derived in the same way. The (n-a+1)th bit signal can be regarded as the second baseband envelope signal, the (n-a)th bit is the first baseband envelope signal, and the (n-a)th bit average is the first average. Therefore, the conflict bit can be determined by using the average of the (n-a+1)th bit to remove the DC component and then determining the logic level.

[0079] Step 810, determining the logic level of the second baseband envelope signal according to the reference second signal.

[0080] The logic level is 0 or 1. Alternatively, the logic level is high or low. The logic level in one symbol period includes normal bit level and abnormal bit level. The normal bit level includes 0 and 1. The abnormal bit level includes conflict bit level and end bit level. The conflict bit level includes only 1 or only high. The end bit level includes only 0 or only low.

[0081] Specifically, the receiver integrates every half symbol period in the reference second signal to obtain each half integration value; and determines the logic level of the second envelope signal according to the positive and negative of each half integration value. For example, when the half integration value is positive, it is determined that the logic level of the second baseband envelope signal contains 1; when the half integration value is negative, it is determined that the logic level of the second baseband envelope signal contains 0. Alternatively, the receiver can determine the logic level of the second envelope signal according to the size of each half integration value. When an abnormal bit logic level is detected, the demodulation is ended.

[0082] The determination threshold for determining the logic level is particularly important due to the existence of the DC component in the signal demodulation method in the embodiment. Since the logic level of the first baseband envelope signal is the normal bit level, the first average value is obtained by determining the average value of the first baseband envelope signal, and the second baseband envelope signal is subjected to DC removal according to the first average value to obtain the reference second signal, that is, the average value of the signal based on the normal bit level is subjected to DC removal, the logic level of the second baseband envelope signal can be determined, and the abnormal bit level can be determined, thereby improving the accuracy of the logic level determination.

[0083] In one embodiment, the logic level of the second baseband envelope signal is determined according to the reference second signal, including: integrating the reference second signal to obtain a second integral value; and determining the logic level of the second baseband envelope signal as an abnormal bit level when the second integral value satisfies an abnormal bit determination condition.

[0084] The abnormal bit includes a conflict bit and an end bit. The abnormal bit determination condition is used to represent that the logic levels in the symbol period are all 1 or all 0. The conflict bit is that the logic levels in the symbol period are all 1, such as Figure 11 (c). The end bit is that the logic levels in the symbol period are all 0, such as Figure 5 (b).

[0085] Specifically, the receiver integrates the reference second signal to obtain a second integral value, and determines the logic level of the second baseband envelope signal as an abnormal bit level when the second integral value satisfies an abnormal bit determination condition. The abnormal bit determination condition includes that the second integral value is not in a preset integral range. For example, the preset integral value range refers to the range corresponding to the normal bit level. When the abnormal bit level is detected, the demodulation is ended.

[0086] In the embodiment, the receiver integrates every half symbol period in the reference second signal to obtain two second integral values, and determines the logic level of the second baseband envelope signal as an abnormal bit level when the two second integral values satisfy an abnormal bit determination condition. The abnormal bit determination condition includes that the two integral values are both positive or the two integral values are both negative.

[0087] In the embodiment, the reference second signal is integrated to obtain a second integral value, and the logic level of the second baseband envelope signal is determined as an abnormal bit level when the second integral value satisfies an abnormal bit determination condition. The abnormal bit level can be determined without increasing the cost, and the accuracy of the logic level determination is improved.

[0088] In one embodiment, the logic level of the second baseband envelope signal according to the reference second signal further comprises: determining an average value of the second baseband envelope signal to obtain a second average value; when the second integral value does not satisfy the abnormal bit determination condition, performing DC removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal; and determining the normal bit level of the second baseband envelope signal according to the target second signal.

[0089] In one embodiment, the logic level of the second baseband envelope signal according to the reference second signal further comprises: determining an average value of the second baseband envelope signal to obtain a second average value; when the second integral value does not satisfy the abnormal bit determination condition, performing DC removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal; and determining the normal bit level of the second baseband envelope signal according to the target second signal.

[0090] In one embodiment, the logic level of the second baseband envelope signal according to the reference second signal further comprises: determining an average value of the second baseband envelope signal to obtain a second average value; when the second integral value does not satisfy the abnormal bit determination condition, performing DC removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal; and determining the normal bit level of the second baseband envelope signal according to the target second signal.

[0091] In one embodiment, the logic level of the second baseband envelope signal according to the reference second signal further comprises: determining an average value of the second baseband envelope signal to obtain a second average value; when the second integral value does not satisfy the abnormal bit determination condition, performing DC removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal; and determining the normal bit level of the second baseband envelope signal according to the target second signal.

[0092] In one embodiment, the logic level of the second baseband envelope signal according to the reference second signal further comprises: determining an average value of the second baseband envelope signal to obtain a second average value; when the second integral value does not satisfy the abnormal bit determination condition, performing DC removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal; and determining the normal bit level of the second baseband envelope signal according to the target second signal.

[0093] In one embodiment, the logic level of the second baseband envelope signal according to the reference second signal further comprises: determining an average value of the second baseband envelope signal to obtain a second average value; when the second integral value does not satisfy the abnormal bit determination condition, performing DC removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal; and determining the normal bit level of the second baseband envelope signal according to the target second signal.

[0094] In one embodiment, the logic level of the second baseband envelope signal according to the reference second signal further comprises: determining an average value of the second baseband envelope signal to obtain a second average value; when the second integral value does not satisfy the abnormal bit determination condition, performing DC removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal; and determining the normal bit level of the second baseband envelope signal according to the target second signal.

[0095] In this embodiment, the first baseband envelope signal is subjected to DC removal processing according to the first mean value to obtain the first baseband envelope signal from which DC is removed, and a first bit synchronization signal corresponding to the first baseband envelope signal is obtained. The second baseband envelope signal can be corrected by using the first bit synchronization signal, so that the obtained second mean value is more accurate.

[0096] In one embodiment, Figure 5 The figure shows a block diagram of the principle of an in-phase orthogonal integral type bit synchronization circuit in one embodiment. In order to enhance the anti-interference performance of the bit synchronization circuit and the judgment output, the embodiment of the present application adopts an in-phase orthogonal integral type bit synchronization circuit. The integral type bit synchronization circuit applies the principle of matched filtering to optimally detect the baseband envelope signal with the DC component removed, greatly reducing the impact of interference, and the extracted bit synchronization signal has better anti-interference performance. The integral type bit synchronization circuit also meets the design requirement of judging the baseband envelope at the moment when the signal-to-noise ratio is maximum, and ensures that each bit of data is judged once, thereby improving the accuracy of the judgment.

[0097] The clock conversion circuit generates two mutually orthogonal bidirectional clock signals, namely clk_d1 and clk_d2. The duty cycle of the two signals is 1:3, and the high-level pulse width is one crystal oscillator clock cycle.

[0098] The in-phase integration and sample-and-hold circuit is used to accumulate the envelope signal (excluding the DC component) within the half symbol period and output the accumulated value at the end of the half symbol period. If the accumulated value is greater than 0, the half symbol is determined to be at a high level; otherwise, it is determined to be at a low level.

[0099] The phase detector consists of an edge detector, an XOR gate, and an AND gate (pd_bef and pd_aft). When the bit synchronization signal is ahead, pd_bef outputs a high-level pulse; otherwise, pd_aft outputs a high-level pulse.

[0100] The controller consists of flip-flops (pd_before and pd_after) and AND gates (gate_open and gate_close), which complete the "add / subtract" pulse function and thus achieve the purpose of adjusting the bit synchronization signal output by the divider.

[0101] Figure 12 FIG. 1 is a timing diagram of the determination output of an in-phase, quadrature integration type bit synchronization circuit in one embodiment. Figure 13 (a) is the baseband envelope signal after removing the DC component signal. Figure 13 (b) is the bit synchronization signal. Figure 13 (c) is the integration over half a symbol period. Figure 13(d) Demodulate the obtained baseband signal. When the integral value in a half code period is greater than 0, determine that the half code is a high level, otherwise determine that it is a low level. Since the signal is a return-to-zero code, a decoding sampling pulse is generated at a three-quarter code period. Sample the baseband signal at the decoding sampling pulse. If the baseband signal is a low level, the bit is decoded as 0, otherwise decoded as 1.

[0102] In one embodiment, the first baseband envelope signal in the first code period is obtained by: obtaining a modulated signal in the first code period; rectifying the modulated signal in the first code period to obtain a double-frequency modulated carrier signal; and filtering the double-frequency modulated carrier signal to obtain the first baseband envelope signal in the first code period.

[0103] In one embodiment, the modulated signal in the first code period is a digital signal, and the double-frequency modulated carrier signal and the first baseband envelope signal in the first code period are also digital signals.

[0104] Specifically, the receiver obtains the modulated signal in the first code period from the modulated signal with a strong signal. The receiver flips the negative half of the modulated signal in the first code period to the positive half to obtain the double-frequency modulated carrier signal. As shown in FIG. 3, it is a waveform diagram of the rectification of the modulated signal in one embodiment. Figure 13 Figure 14 In one embodiment, the modulated signal in the first code period is a digital signal, and the double-frequency modulated carrier signal and the first baseband envelope signal in the first code period are also digital signals.

[0105]

[0106] The receiver obtains the first baseband envelope signal in the first code period by low-pass filtering the double-frequency modulated carrier signal. As shown in FIG. 4, it is a waveform diagram of low-pass filtering in one embodiment. Figure 14 Figure 15 In one embodiment, the modulated signal in the first code period is a digital signal, and the double-frequency modulated carrier signal and the first baseband envelope signal in the first code period are also digital signals.

[0107] In this embodiment, the first baseband envelope signal in the first code period is obtained by obtaining the modulated signal in the first code period, rectifying the modulated signal in the first code period, and then filtering. In this way, the circuit operation and the circuit operation load can be reduced without changing the sample rate of the signal.

[0108] ​​In one embodiment, filtering the double frequency modulated carrier signal to obtain a first baseband envelope signal within a first symbol period includes: filtering the double frequency modulated carrier signal through a cascaded integrator comb filter to obtain the first baseband envelope signal within the first symbol period.

[0109] The cascaded integrator-comb (CIC) filter does not require a multiplier or a storage unit, and occupies relatively few resources when processing high-frequency signals. In the embodiment of the present application, a digital channel filter structure of a second-order CIC filter is used.

[0110] Specifically, the cascaded integrator-comb filter includes one or more pairs of integrator-comb filters, wherein the multiple pairs of integrator-comb filters are separated by a decimator with a decimation factor of M. Figure 15 The figure shows the structure of a second-order CIC filter in one embodiment. -1 is a comb filter and M is a decimator.

[0111] Common communication protocols used by receivers include ISO 14443A and ISO 15693. It is understood that common protocols may also include other communication protocols.

[0112] Because ISO14443A and ISO15693 use different modulation carrier frequencies and bit rates, the frequencies filtered by the CIC differ for each communication protocol. Table 2 shows the ASK modulation carrier frequencies and bit rates for ISO14443A and ISO15693 cards.

[0113] Table 2 ASK (Amplitude Shift Keying) modulation carrier frequency and code rate

[0114]

[0115] When demodulating the ASK modulated signal of the ISO14443A card, the CIC digital low-pass filter must meet the following conditions:

[0116] The 1.69MHz modulated carrier signal is filtered to retain the 106KHz baseband signal.

[0117] When demodulating the ASK modulated signal of the ISO15693 card, the CIC digital low-pass filter must meet the following conditions:

[0118] The modulated carrier signal of 847.5KHz is filtered and the signals with frequencies below 53KHz are retained.

[0119] By analyzing the amplitude-frequency characteristic of the 2-order 4-times-extracted CIC filter, it is known that the signal of the frequency near 1.69MHz is greatly attenuated, thus the effect of filtering out the 1.69MHz signal can be achieved; and the signal of the frequency below 106KHz is greatly attenuated, thus the purpose of reserving the 106KHz signal can be achieved. Therefore, when demodulating the ASK modulated signal of the ISO14443A card, the 2-order 4-times-extracted CIC filter is suitable to be adopted.

[0120] By analyzing the amplitude-frequency characteristic of the 2-order 8-times-extracted CIC filter, it is known that the signal of the frequency near 847.5KHz is greatly attenuated, thus the effect of filtering out the 847.5KHz signal can be achieved; and the signal of the frequency below 53KHz is greatly attenuated, thus the purpose of reserving the signal below 53KHz can be achieved. Therefore, when demodulating the ASK modulated signal of the ISO15693 card, the 2-order 8-times-extracted CIC filter is suitable to be adopted.

[0121] The main functions of the cascaded integration comb filter are as follows:

[0122] 1. Filtering out the band-out quantization noise. After digital rectification, the double frequency modulated carrier signal is obtained. The channel filter needs to filter the double frequency modulated carrier signal and filter out the band-out noise signal.

[0123] 2. Reducing the sampling frequency. After digital rectification, the signal retains the sampling frequency of 6.78MHz, and there is redundant data, thus the signal needs to be processed by the downsampling.

[0124] 3. Anti-aliasing. In the extraction process of the rectified signal, the band-in quantization noise will also be extracted, thus the signal needs to be processed by the cascaded integration comb filter for anti-aliasing.

[0125] In this embodiment, the double frequency modulated carrier signal is filtered by the cascaded integration comb filter to obtain the first baseband envelope signal in the first code element period, which can filter out the band-out quantization noise, reduce the sampling frequency, and process the signal for anti-aliasing, thus the accuracy of the obtained first baseband envelope signal is improved.

[0126] In one embodiment, the double frequency modulated carrier signal is filtered by the cascaded integration comb filter to obtain the first baseband envelope signal in the first code element period, including: filtering the double frequency modulated carrier signal by the cascaded integration comb filter to obtain the filtered double frequency modulated carrier signal; when the communication protocol adopted by the modulated signal is a preset communication protocol, the filtered double frequency modulated carrier signal is processed by the downsampling filter for downsampling to obtain the first baseband envelope signal in the first code element period.

[0127] The preset communication protocol includes one in which the number of samples after filtering exceeds the preset number of samples. Advantageously, the preset number of samples can be 8. Analysis of Table 3 shows that the number of samples after ISO 14443A filtering is 8, requiring no further downsampling. The ISO 15693 filtered signal requires downsampling. A first-order 8x decimation CIC filter is used to downsample the ISO 15693 card's 6.62 bit rate signal, while a first-order 2x decimation CIC filter is used to downsample the ISO 15693 card's 26.48 bit rate signal.

[0128] Table 3 Number of samples in half a symbol period after digital low-pass filtering

[0129]

[0130] In the digital signal processing process of the DC removal circuit and the integral bit synchronization circuit, only 8 samples are required for half a code element period. In order to reduce the chip overhead and power consumption, the filtered signal is downsampled to achieve the effect of 8 samples corresponding to half a code element period.

[0131] In this embodiment, since the sampling frequency of some filtered double-frequency modulated carrier signals is relatively high, it is necessary to determine whether downsampling is required based on the communication protocol used by the modulated signal. When the communication protocol used by the modulated signal is a preset communication protocol, downsampling is performed through a downsampling filter, which can reduce the chip's overhead and power consumption.

[0132] In one embodiment, obtaining a first baseband envelope signal within a first symbol period includes: monitoring the baseband envelope signal; and obtaining the first baseband envelope signal within the first symbol period when a first envelope protrusion is detected.

[0133] The first baseband envelope signal within the first symbol period may be the baseband envelope signal of the first symbol period in the signal.

[0134] Specifically, when the tag does not send valid data, the signal is in a low level state. The receiver monitors the baseband envelope signal; when the first envelope bump is detected, it starts processing the signal to obtain the first baseband envelope signal within the first symbol period.

[0135] like Figure 16 Figure 2 shows a waveform diagram of a baseband envelope signal in one embodiment. The signal includes a constant carrier signal and a signal with an envelope bump. The constant carrier signal does not have an envelope bump. Therefore, by detecting the first envelope bump, the first baseband envelope signal within the first symbol period can be located.

[0136] In this embodiment, by detecting the baseband envelope signal, when the first envelope protrusion is detected, the signal processing begins, and the signal can be processed correctly.

[0137] In one embodiment, a demodulation method comprises:

[0138] Step (a1), obtaining a modulated signal in a first symbol period.

[0139] Step (a2), rectifying the modulated signal in the first symbol period to obtain a double-frequency modulated carrier signal.

[0140] Step (a3), filtering the double-frequency modulated carrier signal by cascading an integral comb filter to obtain a filtered double-frequency modulated carrier signal.

[0141] Step (a4), when the communication protocol adopted by the modulated signal is a preset communication protocol, downsampling the filtered double-frequency modulated carrier signal by a downsampling filter to obtain a first baseband envelope signal in the first symbol period.

[0142] Step (a5), obtaining the first baseband envelope signal in the first symbol period.

[0143] Step (a6), obtaining a second baseband envelope signal in a second symbol period. The second symbol period is a backward period of the first symbol period.

[0144] Step (a7), determining an average value of the first baseband envelope signal to obtain a first average value.

[0145] Step (a8), performing a direct current (DC) removal on the second baseband envelope signal according to the first average value to obtain a reference second signal.

[0146] Step (a9), integrating the reference second signal to obtain a second integral value.

[0147] Step (a10), when the second integral value satisfies an abnormal bit determination condition, determining that a logic level of the second baseband envelope signal is an abnormal bit level.

[0148] Step (a11), performing a DC removal on the first baseband envelope signal according to the first average value to obtain a DC-removed first baseband envelope signal.

[0149] Step (a12), performing bit synchronization on the DC-removed first baseband envelope signal to obtain a first bit synchronization signal.

[0150] Step (a13), determining an average value of the second baseband envelope signal according to the first bit synchronization signal to obtain a second average value.

[0151] Step (a14), when the second integral value does not satisfy the abnormal bit determination condition, performing a DC removal on the second baseband envelope signal according to the second average value to obtain a target second signal.

[0152] Step (a15): determining a normal bit level of the second baseband envelope signal according to the target second signal.

[0153] In this embodiment, filtering is performed through a cascaded integral comb filter to filter out the subcarrier signal, while downsampling and anti-aliasing are simultaneously possible. Averaging is performed after downsampling to reduce resource consumption. By averaging according to the symbol period, abnormal bit levels and normal bit levels can be determined, thereby improving the accuracy of logic level determination.

[0154] The above steps (a1) to (a15) can be implemented by hardware, or by FPGA (Field Programmable Gate Array), or by computer circuit simulation.

[0155] It should be understood that although the above Figure 17 The steps in the flowchart are shown in sequence as indicated by arrows, and the steps (a1) to (a15) are shown in sequence as indicated by numbers, but these steps are not necessarily performed in the order indicated by arrows or numbers. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be performed in other orders. Moreover, Figure 8 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0156] In one embodiment, Figure 8 FIG. 1 is a structural block diagram of a signal demodulation device in one embodiment. Figure 18 A signal demodulation device is provided. The device can be implemented as a software module or a hardware module, or a combination of both, and formed as part of a computer device. The device specifically includes a baseband envelope signal monitoring module 1802, a DC removal module 1804, and a symbol determination module 1806, which are connected in sequence.

[0157] A baseband envelope signal monitoring module 1802 is configured to obtain a first baseband envelope signal within a first symbol period;

[0158] The baseband envelope signal monitoring module 1802 is further configured to obtain a second baseband envelope signal within a second symbol period; the second symbol period is a backward period of the first symbol period;

[0159] a DC removal module 1804, configured to determine an electrical average value of the first baseband envelope signal to obtain a first average value;

[0160] The DC removal module 1804 is further configured to perform DC removal on the second baseband envelope signal according to the first average value to obtain a reference second signal;

[0161] The symbol determination module 1806 is configured to determine the logic level of the second baseband envelope signal according to the reference second signal.

[0162] In this embodiment, the determination threshold for determining the logic level is particularly important due to the existence of the DC component, and since the logic level of the first baseband envelope signal is the normal bit level, the first average value is obtained by determining the average value of the first baseband envelope signal, and the reference second signal is obtained by performing DC removal on the second baseband envelope signal according to the first average value, that is, the DC removal is performed based on the average value of the signal of the normal bit level, the logic level of the second baseband envelope signal can be determined, and the abnormal bit level can be determined, thereby improving the determination accuracy of the logic level.

[0163] In one embodiment, the signal demodulation apparatus further includes an integral bit synchronization module. The integral bit synchronization module is configured to integrate the reference second signal to obtain an integral value; and the symbol determination module 1806 is configured to determine the logic level of the second baseband envelope signal as the abnormal bit level when the integral value meets an abnormal bit determination condition.

[0164] In this embodiment, the second integral value is obtained by integrating the reference second signal, and the logic level of the second baseband envelope signal is determined as the abnormal bit level when the second integral value meets the abnormal bit determination condition, so that the abnormal bit level can be determined without increasing the cost, and the determination accuracy of the logic level is improved.

[0165] In one embodiment, the DC removal module 1804 is further configured to determine an average value of the second baseband envelope signal to obtain a second average value;

[0166] and perform DC removal on the second baseband envelope signal according to the second average value to obtain a target second signal when the integral value does not meet the abnormal bit determination condition;

[0167] The symbol determination module 1806 is further configured to determine the normal bit level of the second baseband envelope signal according to the signal level value of the target second signal.

[0168] In this embodiment, the second average value of the second baseband envelope signal itself is used for DC removal and the normal bit level is determined, so that the determination accuracy of the logic level is improved.

[0169] In one embodiment, the DC removal module 1804 is further configured to perform DC removal on the first baseband envelope signal according to the first average value to obtain a DC-removed first baseband envelope signal;

[0170] The integral bit synchronization module is also configured to perform bit synchronization on the direct current removed first baseband envelope signal to obtain a first bit synchronization signal.

[0171] The direct current removing module 1804 is further configured to determine an average value of the second baseband envelope signal according to the first bit synchronization signal to obtain a second average value.

[0172] In this embodiment, the first baseband envelope signal is subjected to direct current removing processing according to the first average value to obtain a direct current removed first baseband envelope signal, and a first bit synchronization signal corresponding to the first baseband envelope signal is obtained, and the second baseband envelope signal can be corrected through the first bit synchronization signal, so that the obtained second average value is more accurate.

[0173] In one embodiment, the signal demodulation apparatus further comprises a digital rectification module and a digital channel filter module; the digital rectification module is configured to obtain a modulation signal in a first symbol period; and rectify the modulation signal in the first symbol period to obtain a double-frequency modulation carrier signal; and the digital channel filter module is configured to filter the double-frequency modulation carrier signal to obtain a first baseband envelope signal in the first symbol period.

[0174] In this embodiment, the first baseband envelope signal in the first symbol period is obtained by obtaining the modulation signal in the first symbol period, rectifying the modulation signal in the first symbol period, and then filtering, so that the circuit operation and the circuit operation load can be reduced without changing the sample rate of the signal.

[0175] In one embodiment, the digital channel filter module is configured to filter the double-frequency modulation carrier signal through a cascaded integral comb filter to obtain the first baseband envelope signal in the first symbol period.

[0176] In this embodiment, the first baseband envelope signal in the first symbol period is obtained by filtering the double-frequency modulation carrier signal through the cascaded integral comb filter, so that the out-of-band quantization noise can be filtered out, the sampling frequency can be reduced, the signal can be subjected to anti-aliasing processing, and the accuracy of the obtained first baseband envelope signal can be improved.

[0177] In one embodiment, the digital channel filter module is configured to filter the double-frequency modulation carrier signal through a cascaded integral comb filter to obtain a filtered double-frequency modulation carrier signal.

[0178] When the communication protocol adopted by the modulation signal is a preset communication protocol, the filtered double-frequency modulation carrier signal is subjected to down-sampling through a down-sampling filter to obtain the first baseband envelope signal in the first symbol period.

[0179] In this embodiment, since the sampling frequency of some filtered double-frequency modulated carrier signals is relatively high, it is necessary to determine whether downsampling is required based on the communication protocol used by the modulated signal. When the communication protocol used by the modulated signal is a preset communication protocol, downsampling is performed through a downsampling filter, which can reduce the chip's overhead and power consumption.

[0180] In one embodiment, the baseband envelope signal monitoring module 1802 is further configured to monitor the baseband envelope signal; when the first envelope protrusion is detected, a first baseband envelope signal within a first symbol period is obtained.

[0181] In this embodiment, by detecting the baseband envelope signal, when the first envelope protrusion is detected, the signal processing begins, and the signal can be processed correctly.

[0182] In one embodiment, the signal demodulation device may further include a signal synchronization module, a digital rectification module, and a digital channel filtering module connected in sequence, wherein the digital channel filtering module is connected to the baseband envelope signal monitoring module. Figure 18 FIG. 1 is a structural block diagram of a signal demodulation device in another embodiment. Figure 19 Can be used with Figure 19 The block diagram is connected. Figure 1 The system includes an I / Q signal synchronization module, a digital rectifier module, a digital channel filter module, a baseband envelope signal monitoring module, a DC removal module, an integral bit synchronization module, and a symbol determination module. The digital signals processed by the contactless IC card receiver's ASK digital demodulation algorithm include I and Q ASK modulated signals, which are 4-bit ASK digital modulated signals with different signal strengths. The signal demodulation device processes the following:

[0183] The signal synchronization module is used to synchronize the I and Q modulated signals to the digital clock domain.

[0184] The channel selection module is used to select one of the I and Q modulated signals for demodulation. This can be selected through the configuration register or by selecting the signal with the stronger signal strength between the I and Q modulated signals.

[0185] The digital rectifier module is used to rectify the selected modulated signal to obtain a double frequency modulated carrier signal.

[0186] The digital channel filter module is used to filter and downsample the double frequency modulated carrier signal to obtain a baseband envelope signal.

[0187] The baseband envelope signal monitoring module monitors the baseband signal and detects the location of the first baseband envelope bump. If an envelope bump is detected, it is considered a baseband signal and the first envelope bump is used as the start bit for bit synchronization. If no envelope bump is detected, the module continues to monitor for envelope bumps.

[0188] Figure 19 FIG. 1 is a flowchart of a signal demodulation method according to another embodiment. The following will be described in combination with Figure 20 and Figure 19 FIG. 2.

[0189] The DC removal module is configured to determine a first mean value of the first baseband envelope signal when the first baseband envelope signal in the first symbol period is received, and perform DC removal processing on the first baseband envelope signal according to the first mean value to obtain a target first signal.

[0190] The integral bit synchronization module is configured to integrate each half symbol in the target first signal to obtain a first integral value.

[0191] The symbol judgment module is configured to judge whether the logic level is 0 or 1 according to the first integral value, so as to obtain the baseband signal. When the first integral value is positive, the half symbol is high; when the first integral value is negative, the half symbol is low.

[0192] The integral bit synchronization module is configured to determine a first bit synchronization signal of the target first signal.

[0193] The DC removal module is further configured to perform DC removal processing on the second baseband envelope signal according to the first mean value to obtain a reference second signal when the second baseband envelope signal in the second symbol period is received.

[0194] The integral bit synchronization module is further configured to integrate each half symbol in the reference second signal to obtain a second integral value.

[0195] The symbol judgment module is further configured to judge the abnormal bit level according to the second integral value.

[0196] The DC removal module is further configured to determine a second mean value of the second baseband envelope signal according to the first bit synchronization signal, and perform DC removal processing on the second baseband envelope signal according to the second mean value to obtain a target second signal.

[0197] The integral bit synchronization module is configured to integrate each half symbol in the target second signal when the second baseband envelope signal is not the abnormal bit level, i.e., the second integral value does not satisfy the abnormal bit determination condition.

[0198] The symbol judgment module is configured to judge whether the normal bit level is 0 or 1 according to the integral result of each half symbol in the target second signal, so as to obtain the baseband signal.

[0199] The integral bit synchronization module is further configured to input the target second signal into the in-phase quadrature integral type bit synchronization circuit to obtain a second bit synchronization signal, and the second bit synchronization signal is used for processing a third baseband envelope signal in a third symbol period.

[0200] In one embodiment, as shown in FIG. 6, is a waveform diagram of the digital signal demodulation in one embodiment. The diagram includes (a) an ASK modulated signal, (b) a double frequency modulated carrier signal, (c) a low pass filtered signal, (d) a decimated signal, (e) a DC removed baseband envelope signal, (f) a bit synchronization signal, and finally (g) a baseband signal. Figure 20 In one embodiment, as shown in FIG. 6, is a waveform diagram of the digital signal demodulation in one embodiment. The diagram includes (a) an ASK modulated signal, (b) a double frequency modulated carrier signal, (c) a low pass filtered signal, (d) a decimated signal, (e) a DC removed baseband envelope signal, (f) a bit synchronization signal, and finally (g) a baseband signal.

[0201] In one embodiment, the mean value of the previous baseband envelope signal is used to determine whether the current baseband envelope signal is a conflict bit level, and when the abnormal bit determination condition is not met, i.e., when it is not an abnormal bit level, the normal bit level is further determined, which can ensure that the previous baseband envelope signal is a normal bit level. The signal is repeatedly determined until the conflict bit is finally determined and output, and the demodulation is ended, which can reduce resource occupation and improve the determination accuracy of the logic level.

[0202] The specific limitations of the receiver can be referred to the limitations of the signal demodulation method in the above, which will not be repeated here. Each module in the above receiver can be realized by software, hardware and their combination in whole or in part. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to each module.

[0203] In one embodiment, a receiver is provided, which includes the structure in the above device embodiments. In combination with the structure in the above device embodiments, the receiver can further include an integrator, a band pass filter, a gain amplifier and an ADC connected in sequence. The receiver can specifically include a card reader and the like. Figure 21 Figure 1

[0204] In one embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps of the above method embodiments.

[0205] In one embodiment, a computer program product or computer program is provided, which includes computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to make the computer device execute the steps in the above method embodiments.

[0206] ​Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by computer programs instructing relevant hardware, and the computer programs can be stored in a non-volatile computer readable storage medium. When the computer programs are executed, the computer programs can include the processes in the above-mentioned embodiments of each method. Any reference to memory, storage, database or other medium used in each embodiment provided by the present application can include at least one of non-volatile and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. The volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0207] The above only describes the preferred embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields based on the content of the present application specification and drawings, are also included in the patent protection scope of the present application.

Claims

1. A signal demodulation method characterized by comprising: The method comprises: obtaining a first baseband envelope signal in a first symbol period; a logic level of the first baseband envelope signal is a normal bit level; obtaining a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period; determining an average value of the first baseband envelope signal to obtain a first average value; performing DC removal processing on the second baseband envelope signal according to the first average value to obtain a reference second signal; integrating the reference second signal to obtain a second integral value; when the second integral value meets an abnormal bit determination condition, determining that a logic level of the second baseband envelope signal is an abnormal bit level; determining an average value of the second baseband envelope signal to obtain a second average value; when the second integral value does not meet the abnormal bit determination condition, performing DC removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal; determining a normal bit level of the second baseband envelope signal according to the target second signal.

2. The method of claim 1, wherein, The determination of the average value of the second baseband envelope signal to obtain the second average value comprises: performing DC removal processing on the first baseband envelope signal according to the first average value to obtain a DC-removed first baseband envelope signal; performing bit synchronization on the DC-removed first baseband envelope signal to obtain a first bit synchronization signal; determining the average value of the second baseband envelope signal according to the first bit synchronization signal to obtain a second average value.

3. The method of claim 1, wherein, The obtaining of the first baseband envelope signal in the first symbol period comprises: obtaining a modulation signal in the first symbol period; rectifying the modulation signal in the first symbol period to obtain a double-frequency modulation carrier signal; filtering the double-frequency modulation carrier signal to obtain the first baseband envelope signal in the first symbol period.

4. The method of claim 3, wherein, The filtering of the double-frequency modulation carrier signal to obtain the first baseband envelope signal in the first symbol period comprises: filtering the double-frequency modulation carrier signal through a cascaded integral comb filter to obtain the first baseband envelope signal in the first symbol period.

5. The method according to claim 4, characterized in that The filtering of the double-frequency modulation carrier signal through the cascaded integral comb filter to obtain the first baseband envelope signal in the first symbol period comprises: filtering the double-frequency modulation carrier signal through the cascaded integral comb filter to obtain a filtered double-frequency modulation carrier signal; when a communication protocol adopted by the modulation signal is a preset communication protocol, performing down-sampling on the filtered double-frequency modulation carrier signal through a down-sampling filter to obtain the first baseband envelope signal in the first symbol period.

6. A signal demodulation apparatus characterized by comprising: The apparatus comprises: a baseband envelope signal monitoring module configured to obtain a first baseband envelope signal in a first symbol period; a logic level of the first baseband envelope signal is a normal bit level; the baseband envelope signal monitoring module is further configured to obtain a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period; a DC removal module configured to determine an average value of the first baseband envelope signal to obtain a first average value; The DC removal module is further configured to perform DC removal on the second baseband envelope signal according to the first average value to obtain a reference second signal; The integral bit synchronization module is configured to integrate the reference second signal to obtain a second integral value; The symbol determination module is configured to determine a logic level of the second baseband envelope signal as an abnormal bit level when the second integral value satisfies an abnormal bit determination condition; The DC removal module is further configured to determine an average value of the logic level of the second baseband envelope signal to obtain a second average value; and perform DC removal on the second baseband envelope signal according to the second average value to obtain a target second signal when the second integral value does not satisfy the abnormal bit determination condition; The symbol determination module is further configured to determine a normal bit level of the second baseband envelope signal according to a signal level value of the target second signal.

7. The apparatus of claim 6, wherein, The DC removal module is further configured to perform DC removal on the first baseband envelope signal according to the first average value to obtain a DC-removed first baseband envelope signal; The integral bit synchronization module is further configured to perform bit synchronization on the DC-removed first baseband envelope signal to obtain a first bit synchronization signal; The DC removal module is further configured to determine the average value of the logic level of the second baseband envelope signal according to the first bit synchronization signal to obtain the second average value.

8. A receiver, characterized by The signal demodulation apparatus according to any one of claims 6 or 7.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 5. The computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 5.

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