Display device with adjustable pulse width scanning signal

By employing a pixel block adaptive output scanning signal method in a flat panel display, and utilizing multiple scanning drivers and timing controllers to adjust the pulse width, the display quality problem caused by RC load unevenness is solved, achieving a higher quality display effect.

CN114267275BActive Publication Date: 2026-05-26SAMSUNG DISPLAY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SAMSUNG DISPLAY CO LTD
Filing Date
2021-09-07
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

In single-sided driven flat panel displays, RC load non-uniformity causes the timing of the scan signal and data signal supply to the pixels to be asynchronous, resulting in data charging rate deviation and display quality degradation.

Method used

The method of adaptive output scanning signal by pixel block is adopted. The first scan driver, the second scan driver and the third scan driver respectively supply scanning signals with different pulse widths to different areas of the display panel. Combined with the timing controller, different sub-clock signals are generated to adjust the pulse width, so as to ensure synchronous and uniform signal supply.

Benefits of technology

It effectively reduces RC load unevenness, improves display quality, reduces data signal noise and charging rate deviation, and enhances display effect.

✦ Generated by Eureka AI based on patent content.

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Abstract

A display device is provided. The display device includes: a display panel including scan lines, a first signal line connected to scan lines in a first pixel block, a second signal line connected to scan lines in a second pixel block, and a third signal line connected to scan lines in a third pixel block; a first scan driver supplying a first output signal to the first signal line based on a first sub-clock signal; a second scan driver supplying a second output signal to the second signal line based on a second sub-clock signal; a third scan driver supplying a third output signal to the third signal line based on a third sub-clock signal; and a timing controller. The pulse width variation of the first output signal and the pulse width variation of the third output signal are different within one frame period.
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