Gate driving circuit and display device including the same

Abstract

A gate driving circuit and a display device including the gate driving circuit are provided. The gate driving circuit includes a plurality of cell stages interconnected with each other, wherein each of the plurality of cell stages includes a first transistor, a first capacitor and a second capacitor. The first transistor has a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer and a second electrode contacting a second portion of the active layer. The first capacitor is defined by a first region where the lower gate electrode and the upper gate electrode overlap, and the second capacitor is defined by a second region where the upper gate electrode and the first electrode overlap, wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor.

Description

Technical Field

[0001] The embodiments described herein relate to gate driving circuits, and more specifically, to display devices including gate driving circuits. Background Technology

[0002] The display device includes a display area and a non-display area. Multiple pixels, multiple gate lines, and multiple data lines can be formed in the display area. A gate driving circuit can be formed in the non-display area. The gate driving circuit can send gate signals to the multiple gate lines. The multiple pixels can emit light by receiving data voltage under the control of the gate signals.

[0003] To reduce the area of ​​the gate drive circuit and increase the area of ​​the display area, a dual-gate transistor can be used in the gate drive circuit. When using a dual-gate transistor, contacts may be needed to electrically connect the upper and lower gate electrodes.

[0004] The information disclosed in this background section is only for understanding the background of the concept of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] The applicant recognized that when using dual-gate transistors, the area of ​​the gate drive circuit could increase due to the contact portion. When using dual-gate transistors in the gate drive circuit of a display device, there is a need to reduce the area of ​​the gate drive circuit.

[0006] The gate driving circuit and display device comprising the gate driving circuit, constructed according to the principles and illustrative implementations of the present invention, can reduce the area of ​​the gate driving circuit and thereby increase the display area available for displaying images. For example, the gate driving circuit can use a dual-gate transistor that does not require a contact portion for connecting the upper gate electrode to the lower gate electrode. Therefore, compared with conventional gate driving circuits and display devices, the gate driving circuit can have a smaller size, and the display device having the gate driving circuit can have a smaller non-display area.

[0007] According to an embodiment, a gate driving circuit for a display device may include a plurality of cell stages that are subordinate to each other, wherein each of the plurality of cell stages includes a first transistor, a first capacitor and a second capacitor. The first transistor includes a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer and a second electrode contacting a second portion of the active layer. The first capacitor is defined by a first region where the lower gate electrode and the upper gate electrode overlap, and the second capacitor is defined by a second region where the upper gate electrode and the first electrode overlap. The upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor.

[0008] The first transistor can be an NMOS transistor (simply referred to as NMOS, and PMOS is similar).

[0009] When the voltage at the upper gate electrode is a high gate voltage and the voltage at the second electrode changes from a low gate voltage to a high gate voltage, the second capacitor can bootstrap the voltage at the upper gate electrode and the voltage at the first electrode.

[0010] The first transistor can be a PMOS transistor.

[0011] When the voltage at the upper gate electrode is a low gate voltage and the voltage at the second electrode changes from a high gate voltage to a low gate voltage, the second capacitor can bootstrap the voltage at the upper gate electrode and the voltage at the first electrode.

[0012] The lower gate electrode and the upper gate electrode can completely overlap each other in a plan view.

[0013] The active layer may include an opening that overlaps with the upper gate electrode.

[0014] The first transistor may include a lower gate insulating layer disposed between the lower gate electrode and the active layer, a first insulating layer disposed between the lower gate insulating layer and the upper gate electrode and covering the active layer, and an upper gate insulating layer disposed on the first insulating layer and covering the upper gate electrode.

[0015] Each of the multiple unit stages may include a second transistor capable of operating in response to a previous output signal from the previous unit stage, a third transistor discharging a second capacitor in response to a next output signal from the next unit stage, and a fourth transistor discharging an output signal in response to a next output signal.

[0016] Multiple unit levels can be connected to each other such that the output of a corresponding unit level is connected to the input of another unit level located adjacent to the corresponding unit level, and the output of the other unit level is connected to the input of the corresponding unit level.

[0017] The display device according to the embodiment may include a substrate comprising a display area and a non-display area, a plurality of pixels formed in the display area, and a gate driving circuit formed in the non-display area, wherein the gate driving circuit includes a plurality of cell levels subordinate to each other, wherein each of the plurality of cell levels includes a first transistor, a first capacitor and a second capacitor, the first transistor including a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer and a second electrode contacting a second portion of the active layer, the first capacitor being defined by the lower gate electrode and the upper gate electrode, and the second capacitor being defined by the upper gate electrode and the first electrode, wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in a first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor.

[0018] The first transistor can be an NMOS transistor.

[0019] When the voltage at the upper gate electrode is a high gate voltage and the voltage at the second electrode changes from a low gate voltage to a high gate voltage, the second capacitor can bootstrap the voltage at the upper gate electrode and the voltage at the first electrode.

[0020] The first transistor can be a PMOS transistor.

[0021] When the voltage at the upper gate electrode is a low gate voltage and the voltage at the second electrode changes from a high gate voltage to a low gate voltage, the second capacitor can bootstrap the voltage at the upper gate electrode and the voltage at the first electrode.

[0022] The lower gate electrode and the upper gate electrode can completely overlap each other in a plan view.

[0023] The active layer may include an opening that overlaps with the upper gate electrode.

[0024] The first transistor may include a lower gate insulating layer disposed between the lower gate electrode and the active layer, a first insulating layer disposed between the lower gate insulating layer and the upper gate electrode and covering the active layer, and an upper gate insulating layer disposed on the first insulating layer and covering the upper gate electrode.

[0025] Each of the multiple unit stages may include a second transistor capable of operating in response to a previous output signal from the previous unit stage, a third transistor discharging a second capacitor in response to a next output signal from the next unit stage, and a fourth transistor discharging an output signal in response to a next output signal.

[0026] The lower gate electrode and upper gate electrode of the first transistor in the gate drive circuit can be electrically coupled by a first capacitor.

[0027] Accordingly, the area of ​​the gate drive circuit can be reduced by removing the contact portion that electrically connects the lower gate electrode and the upper gate electrode.

[0028] The first transistor can be a dual-gate transistor having an upper gate electrode and a lower gate electrode. The dual-gate transistor can have a relatively large area of ​​the gate electrode overlapping the active layer. Accordingly, the capacitance of the first transistor can be greater than the capacitance of a single-gate transistor having only an upper gate electrode or only a lower gate electrode. Conversely, even if the area of ​​the first transistor is smaller than that of a single-gate transistor, the capacitance of the first transistor can be equal to or greater than that of the single-gate transistor.

[0029] The display device according to the embodiments may include a gate driving circuit with a small area, and thus the area of ​​the non-display area of ​​the display device can be reduced.

[0030] It will be understood that the foregoing general description and the following detailed description are exemplary, illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0031] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary and illustrative embodiments of the invention and, together with the description, serve to explain the concepts of the invention.

[0032] Figure 1 This is a block diagram illustrating an embodiment of a display device constructed according to the principles of the present invention.

[0033] Figure 2 yes Figure 1 The block diagram of the gate drive circuit shown is shown.

[0034] Figure 3 yes Figure 2 The circuit diagram of the k-th unit level among multiple unit levels in the circuit.

[0035] Figure 4 It is shown Figure 3 The waveform diagram of the potential of the Q node and the output signal is shown.

[0036] Figure 5 , Figure 6 and Figure 7 It shows the basis Figure 4 The circuit diagram of the signal flow in the waveform diagram.

[0037] Figure 8 This is a plan view illustrating a portion of an embodiment of a gate drive circuit constructed according to the principles of the present invention.

[0038] Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a layout diagram showing an embodiment of a portion of the gate drive circuit.

[0039] Figure 13 It is intercepted along line I-I' Figure 8 A cross-sectional view of the gate drive circuit.

[0040] Figure 14 It is taken along line II-II' Figure 8 A cross-sectional view of the gate drive circuit. Detailed Implementation

[0041] In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of apparatuses or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or in one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0042] Unless otherwise stated, the embodiments shown should be understood as illustrative features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise indicated, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0043] Crosshairs and / or shading are typically provided in accompanying drawings to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, properties, performance, etc., of the elements. Additionally, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented in different ways, the specific process sequence may be performed differently than the sequence described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, similar reference numerals denote similar elements.

[0044] When a component (such as a layer) is referred to as being "on," "connected to," or "coupled to" another component or layer, the component (such as a layer) may be directly on, directly connected to, or directly coupled to the other component or layer, or an intermediary component or layer may be present. However, when a component or layer is referred to as being "directly" on, directly connected to, or directly coupled to another component or layer, an intermediary component or layer is not present. Therefore, the term "connection" can refer to a physical, electrical, and / or fluid connection with or without an intermediary component. Furthermore, the D1-axis, D2-axis, and D3-axis are not limited to the three axes of a Cartesian coordinate system (such as the x-axis, y-axis, and z-axis) and can be interpreted in a broader sense. For example, the D1-axis, D2-axis, and D3-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the cluster consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] While the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below can be referred to as the second element.

[0046] Spatial relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”) and similar words may be used herein for descriptive purposes and thereby to describe the relationship between one element and another as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and thus, the spatial relative descriptive terms used herein are interpreted accordingly.

[0047] The technical terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the,” as used herein, are intended to include the plural forms as well. Furthermore, the terms “comprises,” “comprising,” “includes,” and / or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or clusters thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or clusters thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are thus utilized to account for inherent biases in measurements, calculations, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0048] Various embodiments are described herein with reference to sectional and / or exploded views as schematic illustrations of idealized implementations and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Consequently, the embodiments disclosed herein should not necessarily be interpreted as limited to the shape of a particular shown area, but will include deviations in shape due to, for example, manufacturing processes. In this way, the areas shown in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0049] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense.

[0050] Figure 1 This is a block diagram illustrating a display device constructed according to an embodiment based on the principles of the present invention.

[0051] Reference Figure 1 The display device 100 may include a display panel PN, a gate drive circuit GDV, a data drive circuit DDV, and a timing controller CON. The display panel PN may include a display area DP and a non-display area ADP. The gate drive circuit GDV, the data drive circuit DDV, and the timing controller CON may be arranged in the non-display area ADP.

[0052] A plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels P may be arranged in the display area DP. The gate lines GL1 to GLn may intersect with the data lines DL1 to DLm and are insulated from each other. The pixels P may be electrically connected to the gate lines GL1 to GLn and the data lines DL1 to DLm. Each of the pixels P may include a light-emitting diode (LED). In the display area DP, the LED can display an image. For example, the LED may include an organic light-emitting diode (OLED), a quantum dot organic light-emitting diode (QDOLED), and a quantum dot nanoLED, etc.

[0053] The timing controller CON can generate the gate control signal GCTRL, the data control signal DCTRL, and the output image data ODAT based on the control signal CTRL and the input image data IDAT. For example, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. For example, the input image data IDAT may be RGB data including red image data, green image data, and blue image data. Alternatively, the input image data IDAT may include magenta image data, cyan image data, and yellow image data.

[0054] The gate drive circuit GDV can generate gate signals based on the gate control signal GCTRL provided by the timing controller CON. For example, the gate control signal GCTRL may include a vertical start signal, a clock signal, a gate turn-off signal, etc.

[0055] The gate drive circuit GDV can be electrically connected to the pixel P via multiple gate lines GL1 to GLn, and can sequentially output gate signals. Each of the multiple pixels P can receive a data voltage according to the control of the corresponding gate signal in the gate signals.

[0056] The data drive circuit DDV can generate a data voltage based on the data control signal DCTRL provided by the timing controller CON and the output image data ODAT. For example, the data control signal DCTRL may include an output data enable signal, a level start signal, and a load signal.

[0057] The data drive circuit DDV can be electrically connected to the pixel P via multiple data lines DL1 to DLm, and can generate data voltages. Each of the multiple pixels P can display an image by receiving a signal for brightness corresponding to the corresponding data voltage.

[0058] Figure 2 yes Figure 1 The block diagram of the gate drive circuit shown is shown.

[0059] Reference Figure 2The gate drive circuit GDV can be a shift register. The shift register can include multiple cell levels ST1 to STn and a virtual level STD. The virtual level STD may not be connected to gate lines GL1 to GLn. Each of the multiple cell levels ST1 to STn can be dependently connected in the following manner: the output of the first cell level ST1 is provided as an input to the second cell level ST2 and the output of the second cell level ST2 is provided as an input to the first cell level ST1, the output of the second cell level ST2 is provided as an input to the third cell level ST3 and the output of the third cell level ST3 is provided as an input to the second cell level ST2, and so on. Each of the multiple cell levels ST1 to STn can sequentially output output signals CR1 to CRn to the corresponding gate lines GL1 to GLn. Each of the multiple cell levels ST1 to STn can receive a gate control signal GCTRL from the timing controller CON. The gate control signal GCTRL can include a vertical start signal and at least one clock signal. For example, the gate control signal GCTRL can include a vertical start signal STV, a clock signal CLK, and a gate turn-off signal VSS.

[0060] The first unit stage ST1 can receive the vertical start signal STV, the clock signal CLK, the gate turn-off signal VSS, and the second output signal CR2 output from the second unit stage ST2. The first unit stage ST1 can output the first output signal CR1 to the first gate line GL1. In this case, the first output signal CR1 can be the clock signal CLK.

[0061] Each of the second unit stage ST2 to the nth unit stage STn can receive an output signal from the previous unit stage, an output signal from the next unit stage, a clock signal CLK, and a gate turn-off signal VSS. For example, the second unit stage ST2 can receive a first output signal CR1 output from the first unit stage ST1, a third output signal CR3 output from the third unit stage ST3, the clock signal CLK, and the gate turn-off signal VSS. The second unit stage ST2 can output a second output signal CR2 to the second gate line GL2. In this case, the second output signal CR2 can be the clock signal CLK.

[0062] Figure 3 yes Figure 2 The circuit diagram of the k-th unit level among multiple unit levels.

[0063] Reference Figure 3 The k-th unit level STk may include at least a first transistor TR1, a first capacitor C1, and a second capacitor C2. For example, the k-th unit level STk may include a first capacitor C1, a second capacitor C2, a first transistor TR1, a second transistor TR2, a third transistor TR3, and a fourth transistor TR4.

[0064] The first transistor TR1 may include a lower gate electrode M10, an upper gate electrode M20 connected to the Q node QN, a second electrode M32 to which a clock signal CLK is input, and a first electrode M31 connected to the output node ON. The lower gate electrode M10 and the upper gate electrode M20 may be electrically coupled by a first capacitor C1. A second capacitor C2 may be defined by the upper gate electrode M20 and the first electrode M31. (See below for further details.) Figure 8 The detailed structure of the first transistor TR1, the first capacitor C1, and the second capacitor C2 is described.

[0065] When the first transistor TR1 is an NMOS, the second electrode M32 can be the drain electrode, and the first electrode M31 can be the source electrode. When the first transistor TR1 is a PMOS, the second electrode M32 can be the source electrode, and the first electrode M31 can be the drain electrode. In the following description, only the case where the first transistor TR1 is an NMOS will be discussed; however, the first transistor TR1 can alternatively be a PMOS. Those skilled in the art will clearly understand the case where the first transistor TR1 is a PMOS.

[0066] The drain and gate electrodes of the second transistor TR2 can receive the (k-1)th output signal CRk-1 of the (k-1)th unit stage. The source electrode of the second transistor TR2 can be connected to the drain electrode of the third transistor TR3.

[0067] The gate electrode of the third transistor TR3 can receive the (k+1)th output signal CRk+1 of the (k+1)th unit stage. The drain electrode of the third transistor TR3 can receive the gate turn-off signal VSS.

[0068] The gate electrode of the fourth transistor TR4 can receive the (k+1)th output signal CRk+1 of the (k+1)th unit stage. The drain electrode of the fourth transistor TR4 can receive the gate turn-off signal VSS. The source electrode of the fourth transistor TR4 can be connected to the output node ON.

[0069] Figure 4 It is shown Figure 3 The waveform diagram of the potential of the Q node and the output signal is shown.

[0070] Reference Figure 4The clock signal CLK, the (k-1)th output signal CRk-1 of the (k-1)th unit level, the (k+1)th output signal CRk+1 of the (k+1)th unit level, and the gate turn-off signal VSS can be either a gate high voltage or a gate low voltage. When the first transistor TR1 is an NMOS, it turns on when a gate high voltage VGH is applied to the upper gate electrode M20 and the lower gate electrode M10. When the first transistor TR1 is a PMOS, it turns on when a gate low voltage VGL is applied to the upper gate electrode M20 and the lower gate electrode M10. In the following description, only the case where the first transistor TR1 is an NMOS will be discussed; however, the first transistor TR1 can alternatively be a PMOS. Those skilled in the art will clearly understand the case where the first transistor TR1 is a PMOS.

[0071] In the first time period t1, the (k-1)th output signal CRk-1 is input to the k-th cell stage STk as a gate high voltage, and the clock signal CLK, the (k+1)th output signal CRk+1, and the gate turn-off signal VSS are input as gate low voltages.

[0072] In the second time period t2, the clock signal CLK is input to the k-th cell stage STk as a gate high voltage, and the (k-1)-th output signal CRk-1 and the (k+1)-th output signal CRk+1, as well as the gate turn-off signal VSS, are input as a gate low voltage.

[0073] In the third time period t3, the (k+1)th output signal CRk+1 is input to the kth cell level STk as a gate high voltage, and the (k-1)th output signal CRk-1, the clock signal CLK, and the gate turn-off signal VSS are input as a gate low voltage.

[0074] Figure 5 , Figure 6 and Figure 7 It shows the basis Figure 4 The circuit diagram of the signal flow with waveforms.

[0075] Reference Figure 4 and Figure 5When the (k-1)th output signal CRk-1 is input as a pulse with a high gate voltage to the k-th cell stage STk during the first time period t1, the second transistor TR2 can be turned on. Accordingly, the (k-1)th output signal CRk-1 can be supplied to Q-node QN through the turned-on second transistor TR2. When Q-node QN is supplied with the (k-1)th output signal CRk-1, the voltage of Q-node QN can increase. Accordingly, the voltage of the upper gate electrode M20 connected to Q-node QN and the voltage of the lower gate electrode M10 electrically coupled to the upper gate electrode M20 through the first capacitor C1 can increase. Accordingly, the first transistor TR1 can be turned on. The turned-on first transistor TR1 can output the clock signal CLK, which is input as a low gate voltage, to the output node ON.

[0076] Reference Figure 4 and Figure 6 The Q node QN can have a sufficiently high voltage to turn on the first transistor TR1 during the second time period t2. Accordingly, the first transistor TR1 can be turned on. When the first transistor TR1 is turned on, the clock signal CLK supplied to the second electrode M32 of the first transistor TR1 can be output to the output node ON.

[0077] When the clock signal CLK changes from a gate low voltage to a gate high voltage during the second time period t2, the second capacitor C2 can bootstrap the voltage at Q node QN and the voltage at output node ON connected to the first electrode M31. Specifically, when a pulse with a gate high voltage of the clock signal CLK is supplied to output node ON, the voltage at Q node QN also increases due to the coupling of the second capacitor C2. Accordingly, since the voltages at the upper gate electrode M20 and lower gate electrode M10 of the first transistor TR1 and the voltage at the first electrode M31 are bootstrap, the voltages between the upper gate electrode M20, the lower gate electrode M10, and the first electrode M31 can remain constant. Accordingly, the first transistor TR1 can remain in the on state.

[0078] Reference Figure 4 and Figure 7 In the third time period t3, when the (k+1)th output signal CRk+1 is output as a pulse with a high gate voltage, the third transistor TR3 and the fourth transistor TR4 can be turned on. Correspondingly, a gate turn-off signal VSS with a low gate voltage can be supplied to Q node QN and output node ON. Consequently, the voltage of Q node QN decreases, and the voltage of the upper gate electrode M20 connected to Q node QN and the voltage of the lower gate electrode M10 electrically coupled to the upper gate electrode M20 through the first capacitor C1 also decrease. When the voltages of the upper gate electrode M20 and the lower gate electrode M10 decrease, the first transistor TR1 can be turned off. Furthermore, the gate turn-off signal VSS can be supplied to output node ON through the turned-on fourth transistor TR4.

[0079] Figure 8 It illustrates the construction based on the principles of the present invention. Figure 3 A plan view of part 3A of an embodiment of the gate drive circuit. Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a layout diagram showing an embodiment of a portion of the gate drive circuit.

[0080] Reference Figure 8 The first transistor TR1 may include a lower gate electrode M10, an upper gate electrode M20, an active layer ATV, a first electrode M31, and a second electrode M32. The upper gate electrode M20 may be disposed on the lower gate electrode M10 and connected to the Q node QN. The active layer ATV may be disposed between the lower gate electrode M10 and the upper gate electrode M20. The first electrode M31 is connected to the output node ON and may contact the first portion 31 of the active layer ATV. The second electrode M32 contacts the second portion 32 of the active layer ATV and may receive the clock signal CLK.

[0081] When the first transistor TR1 is an NMOS, it can be turned on when a high gate voltage is applied to the upper gate electrode M20 and the lower gate electrode M10. When the first transistor TR1 is turned on, the clock signal CLK input to the second electrode M32 can be output to the output node ON through the active layer ATV and the first electrode M31.

[0082] When the first transistor TR1 is a PMOS, it can be turned on when a low gate voltage is applied to the upper gate electrode M20 and the lower gate electrode M10. When the first transistor TR1 is turned on, the clock signal CLK input to the second electrode M32 can be output to the output node ON through the active layer ATV and the first electrode M31.

[0083] The capacitance of the first transistor TR1, which has an upper gate electrode M20 and a lower gate electrode M10, can be greater than the capacitance of a single-gate transistor that has only an upper gate electrode M20 or only a lower gate electrode M10. Accordingly, even if the area of ​​the first transistor TR1 is smaller than that of a single-gate transistor, the capacitance of the first transistor TR1 can be equal to or greater than that of a single-gate transistor.

[0084] The first capacitor C1 can be defined as the region where the lower gate electrode M10 and the upper gate electrode M20 overlap. Figure 11(A111). Accordingly, compared to the case where the first capacitor C1 is formed separately from the first transistor TR1, the area of ​​the gate drive circuit GDV can be reduced. Furthermore, since the first capacitor C1 electrically couples the lower gate electrode M10 and the upper gate electrode M20, the first transistor TR1 may not include a contact portion for electrically connecting the lower gate electrode M10 and the upper gate electrode M20. Accordingly, the area of ​​the gate drive circuit GDV can be reduced by an amount corresponding to the area of ​​the contact portion.

[0085] The second capacitor C2 can be defined as the region where the upper gate electrode M20 overlaps with the first electrode M31. Figure 10 (A102). Accordingly, compared to the case where the second capacitor C2 is formed separately from the first transistor TR1, the area of ​​the gate drive circuit GDV can be reduced. The first electrode M31 can be formed by stacking it on the upper gate electrode M20. Accordingly, the area of ​​the gate drive circuit GDV can be further reduced.

[0086] Reference Figure 9 The first electrode M31 can be connected to the output node ON via the first connection part A91. The second electrode M32 can receive the clock signal CLK via the second connection part A92.

[0087] Reference Figure 10 The upper gate electrode M20 can be connected to the Q node QN via the third connection A101. The second capacitor C2 can be defined as the region A102 where the upper gate electrode M20 overlaps with the first electrode M31.

[0088] Reference Figure 11 The first capacitor C1 can be defined as region A111 where the lower gate electrode M10 and the upper gate electrode M20 overlap.

[0089] The first electrode M31, the second electrode M32, the upper gate electrode M20, and the lower gate electrode M10 may comprise metals. For example, the first electrode M31, the second electrode M32, the upper gate electrode M20, and the lower gate electrode M10 may be formed from one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or multiple layers.

[0090] Reference Figure 12The active layer ATV may include a first portion 31 and a second portion 32. The first portion 31 may contact the first electrode M31, and the second portion 32 may contact the second electrode M32. The active layer ATV may include one or more openings 120. The openings 120 may overlap with the upper gate electrode M20. The openings 120 may reduce heat generation in the active layer ATV. In some embodiments, the active layer ATV may include an oxide semiconductor. In other embodiments, the active layer ATV may include polysilicon containing impurities.

[0091] Figure 13 It is intercepted along line I-I' Figure 8 A cross-sectional view of the gate drive circuit.

[0092] Reference Figure 13 The first transistor TR1 may include a lower gate insulating layer 131, a first insulating layer 132, and an upper gate insulating layer 133.

[0093] A lower gate insulating layer 131 may be disposed between the lower gate electrode M10 and the active layer ATV. The lower gate insulating layer 131 provides electrical insulation between the lower gate electrode M10 and the active layer ATV. A first insulating layer 132 may be disposed between the lower gate insulating layer 131 and the upper gate electrode M20, and may cover the active layer ATV. The first insulating layer 132 provides electrical insulation between the active layer ATV and the upper gate electrode M20.

[0094] The upper gate insulating layer 133 may be disposed on the first insulating layer 132 and may cover the upper gate electrode M20. The upper gate insulating layer 133 may electrically insulate the first electrode M31 and the second electrode M32 from the upper gate electrode M20.

[0095] The lower gate insulating layer 131, the first insulating layer 132, and the upper gate insulating layer 133 may include insulating materials. For example, each of the lower gate insulating layer 131, the first insulating layer 132, and the upper gate insulating layer 133 may include silicon oxide.

[0096] Figure 14 It is taken along line II-II' Figure 8 A cross-sectional view of the gate drive circuit.

[0097] Reference Figure 14 The first capacitor C1 can be defined as the region where the lower gate electrode M10 and the upper gate electrode M20 overlap. Figure 11 (A111). The second capacitor C2 can be defined as the region where the first electrode M31 overlaps with the upper gate electrode M20 ( Figure 10 (A102). The active layer ATV may include an opening 120 that overlaps with the upper gate electrode M20. The opening 120 may reduce heat generation in the active layer ATV.

[0098] Gate drivers constructed according to the principles and embodiments of the present invention can be applied to display devices and electronic devices including such display devices. For example, they can be used in high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, etc.

[0099] While certain implementations and methods have been described herein, other implementations and variations will become apparent from this description. Accordingly, as will be apparent to those skilled in the art, the inventive concept is not limited to such implementations, but is limited to the broader scope of the appended claims and various obvious variations and equivalents.

Claims

1. A gate driving circuit for a display device, the gate driving circuit comprising: Multiple unit levels, which are interconnected. Each of the plurality of unit levels includes: A first transistor has a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer. A first capacitor, the first capacitor being defined by a first region overlapping the lower gate electrode and the upper gate electrode; and The second capacitor is defined by a second region where the upper gate electrode overlaps with the first electrode. The upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor. The first transistor further includes: A lower gate insulating layer is disposed between the lower gate electrode and the active layer; A first insulating layer is disposed between the lower gate insulating layer and the upper gate electrode and covers the active layer. The first insulating layer has a first opening and a second opening extending from the top surface of the first insulating layer to the bottom surface of the first insulating layer. The first insulating layer covers the entire top surface of the active layer, except where the first and second openings are located. An upper gate insulating layer is disposed on the first insulating layer and covers the upper gate electrode.

2. The gate driving circuit as described in claim 1, wherein, The first transistor is an NMOS transistor.

3. The gate driving circuit as described in claim 2, wherein, When the voltage at the upper gate electrode is a gate high voltage and the voltage at the second electrode changes from a gate low voltage to the gate high voltage. The second capacitor bootstraps the voltage at the upper gate electrode and the voltage at the first electrode.

4. The gate driving circuit as described in claim 1, wherein, The lower gate electrode and the upper gate electrode completely overlap each other in a plan view.

5. The gate driving circuit as described in claim 1, wherein, The active layer includes an opening that overlaps with the upper gate electrode and extends from the top surface of the active layer to the bottom surface of the active layer.

6. A display device, comprising: A substrate having a display area and a non-display area; Multiple pixels, the multiple pixels being in the display area; as well as Gate driving circuit, the gate driving circuit being located in the non-display area, The gate drive circuit includes multiple interconnected unit stages. Each of the plurality of unit levels includes: A first transistor includes a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer. A first capacitor, the first capacitor being defined by a first region overlapping the lower gate electrode and the upper gate electrode; and The second capacitor is defined by a second region where the upper gate electrode overlaps with the first electrode. The upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor. The active layer includes an opening that overlaps with the upper gate electrode, the opening extending from the top surface of the active layer to the bottom surface of the active layer.

7. The display device as claimed in claim 6, wherein, The first transistor is an NMOS transistor.

8. The display device as claimed in claim 7, wherein, When the voltage at the upper gate electrode is a gate high voltage and the voltage at the second electrode changes from a gate low voltage to the gate high voltage. The second capacitor bootstraps the voltage at the upper gate electrode and the voltage at the first electrode.

9. The display device as claimed in claim 6, wherein, The lower gate electrode and the upper gate electrode completely overlap each other in a plan view.

10. The display device as claimed in claim 6, wherein, The first transistor further includes: A lower gate insulating layer is disposed between the lower gate electrode and the active layer; A first insulating layer is disposed between the lower gate insulating layer and the upper gate electrode and covers the active layer. The first insulating layer has a first opening and a second opening extending from the top surface of the first insulating layer to the bottom surface of the first insulating layer. The first insulating layer covers the entire top surface of the active layer, except where the first and second openings are located. An upper gate insulating layer is disposed on the first insulating layer and covers the upper gate electrode.

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