Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a kind of semiconductor devices and its preparation method, by the first surface layer of drift region is provided with the resistance structure with first end and second end, and first end is electrically connected with gate region, second end is electrically connected with drain region, it is equivalent to parallel resistance between gate region and drain region, so when semiconductor device is applied to semiconductor chip, then no additional integrated resistance in semiconductor chip, by integrating resistance in semiconductor device, it is convenient to adjust resistance value, and can reduce the manufacturing cost of semiconductor chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Generally, after a high-voltage MOSFET is combined with a control chip in a plastic package, a large resistor needs to be integrated in the control chip to provide a current path, thereby providing a gate drive voltage for the high-voltage MOSFET to make the high-voltage MOSFET conduct.

[0003] At present, the control chip is mostly produced in a wafer factory with a diameter of 8 inches or more, and the manufacturing cost per unit area of the chip is high, and the control chip has many integrated devices, which greatly affects the adjustment of the resistance value. Therefore, the scheme of integrating a resistor in the control chip is not high in economy and practicability. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor device capable of improving the economy and practicability of a control chip.

[0005] A semiconductor device comprises:

[0006] a drift region having a first conductivity type;

[0007] a body region located at a first surface layer of the drift region and formed with a channel, the body region having a second conductivity type opposite to the first conductivity type;

[0008] a gate region located at the first surface layer of the drift region and covering the channel, and extending to cover a surface of the body region;

[0009] a source region arranged at a surface of the body region away from the drift region and arranged adjacent to the gate region;

[0010] a resistor structure arranged at the first surface layer of the drift region and comprising opposite first and second ends, the first end being electrically connected to the gate region;

[0011] a drain region located at a second surface layer of the drift region and electrically connected to the second end, the second surface layer being arranged opposite to the first surface layer.

[0012] In one embodiment, the resistor structure comprises:

[0013] a first oxide layer located at the first surface layer of the drift region;

[0014] a polysilicon strip located at a surface of the first oxide layer away from the drift region, the polysilicon strip being provided with a first contact and a second contact in an extension direction of the polysilicon strip, the first contact serving as the first end, and the second contact serving as the second end.

[0015] In one embodiment, the polysilicon strip includes a plurality of crystal strips arranged in an array, each of the crystal strips being connected in series or in parallel.

[0016] In one embodiment, the second contact is located at an end of the polysilicon strip, and the resistance structure further includes:

[0017] an insulating layer covering the first oxide layer and a surface of the polysilicon strip away from the drift region, and exposing the second contact.

[0018] In one embodiment, the source region is located adjacent to the insulating layer or the insulating layer is at least partially embedded in the source region.

[0019] In one embodiment, the resistance structure further includes:

[0020] a conductive layer covering the second contact and electrically connected to the drain region.

[0021] In one embodiment, the body region includes:

[0022] a doped well located at a first surface layer of the drift region and having a second conductivity type;

[0023] a junction termination extension region located at the first surface layer of the drift region and overlapping the doped well.

[0024] In one embodiment, the gate region is at least partially embedded in the source region in a direction parallel to the drift region.

[0025] A method for manufacturing a semiconductor device, the method comprising:

[0026] providing a substrate having a first doping type, and forming a drift region on the substrate, the drift region having a first conductivity type;

[0027] forming a body region at a first surface layer of the drift region, the body region having a second conductivity type, the second conductivity type being opposite to the first conductivity type;

[0028] forming a gate region at the first surface layer of the drift region, the gate region covering the channel and extending to cover a surface of the body region;

[0029] forming a source region at the first surface layer of the drift region, the source region being located adjacent to the gate region;

[0030] forming a resistance structure at the first surface layer of the drift region, the resistance structure including opposite first and second ends, the first end being electrically connected to the gate region;

[0031] A drain region is formed in a second surface layer of the drift region, the drain region is electrically connected with the second end, and the second surface layer is arranged opposite to the first surface layer.

[0032] In one of the embodiments, forming the resistance structure in the first surface layer of the drift region comprises:

[0033] Thermally and oxidatively growing a first oxide layer in the first surface layer of the drift region;

[0034] Depositing a polysilicon layer on the first oxide layer, and respectively implanting P31 ions, N+ ions and P+ ions into the polysilicon layer;

[0035] Performing photoetching and dry etching on the polysilicon layer to obtain polysilicon strips, wherein the polysilicon strips comprise a plurality of crystal strips arranged in an array.

[0036] The semiconductor device described above, by arranging the resistance structure with the first end and the second end in the first surface layer of the drift region, and electrically connecting the first end with the gate region and the second end with the drain region, a resistance is equivalent to being connected in parallel between the gate region and the drain region, so that when the semiconductor device is applied to a semiconductor chip, there is no need to additionally integrate a resistance in the semiconductor chip, by integrating the resistance in the semiconductor device, the resistance value can be adjusted, and the manufacturing cost of the semiconductor chip can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0038] Figure 1 A structural schematic diagram of a semiconductor device of an embodiment;

[0039] Figure 2 A partial top view of a semiconductor device of an embodiment;

[0040] Figure 3 An equivalent circuit diagram of a semiconductor device of an embodiment;

[0041] Figure 4 A structural schematic diagram of a semiconductor device of another embodiment;

[0042] Figure 5 A structural schematic diagram of a semiconductor device of another embodiment;

[0043] Figure 6 A structural schematic diagram of a semiconductor device of another embodiment;

[0044] Figure 7 Structure diagram of a semiconductor device according to another embodiment;

[0045] Figure 8 Partial top view of a semiconductor device according to another embodiment.

[0046] Element number explanation:

[0047] Drift region: 100; body region: 110; gate region: 120; source region: 130; resistance structure: 140; first oxide layer: 141; polysilicon strip: 142; insulation layer: 143; conductive layer: 144; drain region: 150; doped well: 111; junction terminal extension region: 112 DETAILED DESCRIPTION

[0048] In order to facilitate the understanding of the present application, a more complete and comprehensive description of the present application will be made with reference to the relevant drawings. The drawings show embodiments of the present application. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the specification of the present application is only for the purpose of describing the specific embodiments of the present application, and is not intended to limit the present application.

[0050] It can be understood that the terms "first", "second" and the like used in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of the present application, the first resistor can be referred to as the second resistor, and similarly, the second resistor can be referred to as the first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0051] It can be understood that "connection" in the following embodiments, if the circuits, modules, units and the like connected to each other have the transmission of electrical signals or data, should be understood as "electrically connected", "communicatively connected" and the like.

[0052] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "having" etc. specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, the term "and / or" as used in the specification includes any and all combinations of one or more of the associated listed items.

[0053] Figure 1 A schematic diagram of a structure of a semiconductor device according to an embodiment is shown in FIG. 1, which can be applied to a semiconductor chip, including a drift region 100, a body region 110, a gate region 120, a source region 130, a resistance structure 140, and a drain region 150, wherein the drift region 100 has a first conductivity type; the two body regions 110 are spaced apart on a first surface layer of the drift region 100 and have a second conductivity type opposite to the first conductivity type; the gate region 120 is located on the first surface layer of the drift region 100 and extends to cover the surfaces of the two body regions 110; the source region 130 is disposed on the first surface layer of the drift region 100 and is adjacent to the gate region 120; the resistance structure 140 is disposed on the first surface layer of the drift region 100 and includes opposite first and second ends, the first end being electrically connected to the gate region 120; and the drain region 150 is located on a second surface layer of the drift region 100 opposite to the first surface layer and is electrically connected to the second end. Figure 1

[0054] The conductivity types of the drift region 100 and the body region 110 are opposite. The first conductivity type and the second conductivity type are one of P-type and N-type, and the first conductivity type and the second conductivity type are different. For example, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type. In an example, the first conductivity type is N-type and the second conductivity type is P-type, i.e., the conductivity type of the drift region 100 is N-type and the conductivity type of the body region 110 is P-type.

[0055] Specifically, the drift region 100 can be formed by light ion implantation or doping, wherein the type of the implanted ions can be selected according to actual needs.

[0056] The first surface layer of the drift region 100 can be an upper surface layer in Figure 1 The body region 110 on the first surface layer of the drift region 100 can be formed as a channel by being recessed inward, as shown in Figure 2 The gate region 120 covers the channel and extends to cover the surfaces of the body regions 110, and the source region 130 is disposed on the surfaces of the body regions 110 away from the drift region 100, for example, can be​Figure 1 The upper surface of the body region 110, and the source region 130 has a first conductive type opposite to the second conductive type of the body region 110, so that a PN junction is formed between the source region 130 and the body region 110, finally forming a field effect tube. Wherein, the source region 130 is arranged adjacent to the gate region 120, and the source region 130 and the gate region 120 are insulated. In addition, the gate region 120 can cover part of the channel; the source region 130 and the gate region 120 are insulated.

[0057] The resistance structure 140 includes a first end and a second end, the first end is electrically connected with the gate region 120, and the second end is connected with the drain region 150, that is, a resistance structure 140 is connected in parallel between the gate region 120 and the drain region 150 of the field effect tube, and the equivalent circuit diagram can be referred to as shown in Figure 3 Wherein, the resistance R in the figure represents the resistance structure 140. Wherein, the first end of the resistance structure 140 can be electrically connected with the gate region 120 through an internal lead wire.

[0058] It can be understood that, Figure 1 It is exemplarily shown that the resistance structure 140 is partially overlapped on the upper surface of the body region 110, in fact, it can be located in the first surface layer of the drift region 100 and does not cover the body region 110, so as to avoid electrical connection with the body region 110.

[0059] The semiconductor device of the embodiment of the present application sets the resistance structure 140 with a first end and a second end in the first surface layer of the drift region 100, and electrically connects the first end with the gate region 120 and the second end with the drain region 150, which is equivalent to connecting a resistance in parallel between the gate region 120 and the drain region 150, so that when the semiconductor device is applied to a semiconductor chip, there is no need to additionally integrate a resistance in the semiconductor chip, by integrating the resistance in the semiconductor device, the resistance value can be adjusted, and the manufacturing cost of the semiconductor chip can be reduced.

[0060] In one embodiment, the resistance structure 140 at least partially covers the body region 110, and the resistance structure 140 is insulated from the body region 110.

[0061] It can be understood that, in order to reduce the volume of the semiconductor device, the resistance structure 140 can be at least partially overlapped on the upper surface of the body region 110, wherein the resistance structure 140 is insulated from the body region 110.

[0062] In one embodiment, the resistance structure 140 can also be partially embedded in the source region 130 to improve the compactness of the structure layer, thereby reducing the overall volume of the device, wherein the resistance structure 140 is insulated from the source region 130.

[0063] In one embodiment, the resistance structure 140 can include a first oxide layer 141 and a polysilicon strip 142, as shown in Figure 4As shown in the figure. The first oxide layer 141 is located on the first surface layer of the drift region 100; the polysilicon strip 142 is located on the surface of the first oxide layer 141 away from the drift region 100, and the first contact and the second contact are arranged in the extension direction of the polysilicon strip 142, the first contact as the first end, and the second contact as the second end.

[0064] Among them, the first oxide layer 141 can be a silicon dioxide layer, and the polysilicon strip 142 is arranged away from the source region 130 to avoid electrical connection between the polysilicon strip 142 and the source region 130.

[0065] It can be understood that the polysilicon strip can be a single strip with an elongated Z-shaped, S-shaped shape, an elongated and spiral square shape, and an elongated and spiral circular shape, and the polysilicon strip 142 is provided with a first contact and a second contact, and the positions of the first contact and the second contact can be adjusted according to actual needs, and the length of the polysilicon strip 142 between the first contact and the second contact can be determined according to the resistance value of the resistance connected to the gate region 120 and the drain region 150. In one embodiment, the polysilicon strip 142 can be provided with a plurality of external contacts, and in use, two contacts can be selected as the first contact and the second contact according to actual needs.

[0066] In one embodiment, the polysilicon strip includes a plurality of arrayed crystal strips, each of which is connected in series or in parallel.

[0067] Among them, the width of the crystal strip can range from 1um to 4um, and the spacing between adjacent two crystal strips can range from 1um to 3um.

[0068] In one embodiment, the second contact is located at the end of the polysilicon strip 142, and the resistance structure 140 further includes an insulating layer 143 covering the first oxide layer 141 and the surface of the polysilicon strip 142 away from the drift region 100, and exposing the second contact.

[0069] Among them, the insulating layer can be a phosphorus-silicon glass material or a boron-phosphorus-silicon glass material.

[0070] It can be understood that, as Figure 5 shown, in order to facilitate wiring, the two contacts of the polysilicon strip 142 can be located at the proximal end and the distal end of the first oxide layer 141 relative to the gate region 120, wherein the first contact is located at the proximal end to shorten the lead length when electrically connected to the gate region 120, and the second contact is located at the distal end to facilitate lead-out to the drain region 150.

[0071] The insulating layer 143 is used to isolate the polysilicon strip 142 to avoid contact between the polysilicon strip 142 and other conductive layers 144, and at the same time, the polysilicon strip 142 is only exposed to the second contact to facilitate external connection to the drain region 150.

[0072] In one embodiment, the source region 130 is disposed adjacent to the insulating layer 143 or the insulating layer 143 is at least partially embedded in the source region 130.

[0073] It is understood that in order to improve the density of the distribution of each structural layer and thus reduce the overall volume of the semiconductor device, the source region 130 and the insulating layer 143 can be arranged adjacent to each other, or the insulating layer 143 can be at least partially embedded in the source region 130. In this way, due to the insulation of the insulating layer 143, the source region 130 and the polysilicon strip 142 will not be short-circuited, and the density of the distribution of each structural layer will be improved, thereby reducing the overall volume of the semiconductor device.

[0074] In one embodiment, the resistor structure 140 may further include a conductive layer 144, such as Figure 6 As shown, the conductive layer 144 covers the second contact and is electrically connected to the drain region 150.

[0075] It is understandable that, in order to facilitate the connection between the polysilicon strip 142 and the drain region 150, a conductive layer 144 can be provided at the exposed second contact of the polysilicon strip 142. The electrical connection between the polysilicon strip 142 and the drain region 150 is achieved through the electrical connection between the conductive layer 144 and the drain region 150.

[0076] In one embodiment, to Figure 1 Taking a semiconductor device as an example, the body region 110 may include a doped well 111 and a junction termination extension region 112, such as Figure 7 As shown, the doped well 111 is located on the first surface layer of the drift region 100 and has a second conductivity type; the junction termination extension region 112 is located on the first surface layer of the drift region 100 and overlaps with the doped well 111 (the overlapping area is shown by the dashed shaded area in the figure).

[0077] Specifically, the junction termination extension region 112 can be formed at the edge of the main junction by injecting impurities of the same type as the main junction, thereby creating a low-concentration doped region, i.e., the junction termination extension region 112. The junction termination extension region 112 has the same conductivity type as the doped well 111. It can be understood that a deeper pn junction will be formed at the end of the doped well 111, resulting in a larger curvature at the end of the pn junction. The peak electric field appears on the device surface, causing a decrease in the device termination breakdown voltage. By setting the junction termination extension region 112, the breakdown voltage of the semiconductor device can be improved.

[0078] In one embodiment, the gate region 120 is at least partially embedded in the source region 130 in a direction parallel to the drift region 100.

[0079] like Figure 8As shown, it can be understood that the source region 130 can have a recess, and the gate region 120 can be at least partially embedded in the recess, wherein the gate region 120 is arranged to be insulated from the source region 130, so that the device area can be effectively utilized without affecting the current transmission performance when the device is turned on.

[0080] In one embodiment, the gate region 120 includes a second oxide layer, a polysilicon layer and an isolation layer, the second oxide layer is located on the first surface layer of the drift region 100 and extends to cover the surface of the body region 110; the polysilicon layer is located on the surface of the second oxide layer away from the drift region 100; and the isolation layer is located between the polysilicon layer and the source region 130.

[0081] The second oxide layer is used to isolate the polysilicon layer from the drift region 100 and the body region 110, and the isolation layer is used to isolate the polysilicon layer and the source region 130. The polysilicon layer can be a polysilicon material, or a metal, a metal nitride, a metal silicide, etc.

[0082] In one embodiment, the drift region 100 includes a doped region having a first conductivity type and an epitaxial layer, wherein the epitaxial layer is also of the first conductivity type, and the epitaxial layer is located on the upper surface of the doped region and can be formed by ion implantation.

[0083] The embodiment of the present application also provides a preparation method of a semiconductor device, which includes steps S110 to S160.

[0084] In step S110, a substrate having a first doping type is provided, and a drift region 100 is formed on the substrate, wherein the drift region 100 has a first conductivity type.

[0085] Specifically, the first conductivity type can be one of P type and N type, and the drift region 100 is formed by doping ions. The drift region 100 can include a doped region having a first conductivity type and an epitaxial layer, wherein the epitaxial layer is also of the first conductivity type, and the epitaxial layer is located on the upper surface of the doped region and can be formed by ion implantation.

[0086] In one embodiment, the drift region 100 can be of N conductivity type, and is formed by implanting N ions with a dose of 4E15-6E15 / cm2.

[0087] In step S120, a body region 110 is formed on the first surface layer of the drift region 100, wherein the body region 110 has a second conductivity type, and the second conductivity type is opposite to the first conductivity type.

[0088] The second conductivity type can be one of P type and N type, and opposite to the first conductivity type. For example, the first conductivity type is P type, and the second conductivity type is N type; or the first conductivity type is N type, and the second conductivity type is P type. For example, in the embodiment, the first conductivity type is N type, and the second conductivity type is P type, i.e., the conductivity type of the drift region 100 is N type, and the conductivity type of the body region 110 is P type.

[0089] The first surface layer of the drift region 100 can be Figure 1 The upper surface layer of the body region 110 in the drift region 100 can be concave to form a channel, as shown in Figure 2

[0090] In step S130, a gate region 120 is formed on the first surface layer of the drift region 100, the gate region 120 covers the channel and extends to cover the surface of the body region 110.

[0091] In step S140, a source region 130 is formed on the first surface layer of the drift region 100, the source region 130 is arranged adjacent to the gate region 120.

[0092] The source region 130 has the first conductivity type opposite to the second conductivity type of the body region 110, so that a PN junction is formed between the source region 130 and the body region 110, and finally forms a field effect tube.

[0093] In step S150, a resistance structure 140 is formed on the first surface layer of the drift region 100, the resistance structure 140 includes a first end and a second end, and the first end is electrically connected to the gate region 120.

[0094] Specifically, the first end can be electrically connected to the gate region 120 through an internal lead.

[0095] In step S160, a drain region 150 is formed on the second surface layer of the drift region 100, and the drain region 150 is electrically connected to the second end.

[0096] The source region is arranged spaced apart from the drift region 100 through the body region 110; and the drain region 150 can be electrically connected to the second end through an internal lead.

[0097] In one embodiment, when the resistance structure 140 is formed on the first surface layer of the drift region 100, the resistance structure 140 can also at least partially cover the body region 110, and the resistance structure 140 is insulated from the body region 110.

[0098] It can be understood that the resistance structure 140 can be at least partially stacked on the upper surface of the body region 110, and the resistance structure 140 is insulated from the body region 110, so that the volume of the semiconductor device can be reduced.

[0099] ​In one embodiment, when the resistance structure 140 is formed in the first surface layer of the drift region 100, the resistance structure 140 is also partially embedded in the source region 130 to improve the compactness of the structure layer and reduce the overall volume of the device, wherein the resistance structure 140 is insulated from the source region 130.

[0100] In one embodiment, forming the resistance structure in the first surface layer of the drift region includes thermally and oxidatively growing a first oxide layer in the first surface layer of the drift region, then depositing a polysilicon layer on the first oxide layer, and implanting P31 ions, N+ ions and P+ ions into the polysilicon layer, respectively, and finally performing photolithography and dry etching on the polysilicon layer to obtain a polysilicon strip, wherein the polysilicon strip includes a plurality of crystal bars arranged in an array, and each crystal bar is connected in series or in parallel with each other.

[0101] In one embodiment, the implantation energy of the P31 ions is 40keV-80keV, the dose is 2E15 / cm2-5E15 / cm2, the width of the crystal bar ranges from 1um to 4um, and the spacing between two adjacent crystal bars ranges from 1um to 3um.

[0102] In one embodiment, the first oxide layer 141 is grown by a thermal oxidation process, and the thickness of the first oxide layer 141 is 100nm-200nm. After the preparation of the first oxide layer 141, a polysilicon layer is deposited, and the thickness of the polysilicon layer is 100nm-200nm.

[0103] In one embodiment, the preparation method further includes forming an insulating layer 143 on the first oxide layer 141 and the polysilicon strip 142 away from the surface of the drift region 100, wherein the insulating layer 143 exposes the second contact.

[0104] It can be understood that the two contacts of the polysilicon strip 142 can be located at the proximal end and the distal end of the first oxide layer 141 relative to the gate region 120, respectively, wherein the first contact is located at the proximal end to shorten the lead length when electrically connected to the gate region 120, and the second contact is located at the distal end to facilitate the lead-out to the drain region 150 through the lead. The insulating layer 143 is used to isolate the polysilicon strip 142 to avoid contact between the polysilicon strip 142 and other conductive layers 144, and at the same time, the polysilicon strip 142 is only exposed to the second contact to facilitate the external connection of the drain region 150.

[0105] In one embodiment, the source region 130 is arranged adjacent to the insulating layer 143 or the insulating layer 143 is at least partially embedded in the source region 130.

[0106] It can be understood that, in order to improve the distribution compactness of each structure layer and reduce the overall volume of the semiconductor device, the source region 130 can be arranged adjacent to the insulating layer 143, or the insulating layer 143 can be at least partially embedded in the source region 130. In this way, due to the insulation of the insulating layer 143, the source region 130 and the polysilicon strip 142 are not short-circuited, and the distribution compactness of each structure layer is improved, thereby reducing the overall volume of the semiconductor device.

[0107] Specifically, if the insulating layer 143 is to be at least partially embedded in the source region 130, the insulating layer 143 can be partially formed in a pre-prepared region of the source region 130 before the source region 130 is prepared, and then the source region 130 is prepared. In another embodiment, a recess can be etched on the sidewall of the source region 130 after the source region 130 is prepared, so that the insulating layer 143 can be formed in the recess of the source region 130.

[0108] In one embodiment, the preparation method further comprises covering the conductive layer 144 on the second contact to facilitate the connection between the polysilicon strip 142 and the drain region 150.

[0109] In one embodiment, the step of forming the body region 110 on the first surface layer of the drift region 100 comprises forming a doped well 111 and a junction termination extension region 112 on the first surface layer of the drift region 100, respectively. The doped well 111 and the junction termination extension region 112 can be formed by ion implantation on the first surface layer of the drift region 100, respectively.

[0110] Specifically, the marking can be performed first to mark the region where the body region is to be formed. The body region includes a doped well 121 and a junction termination extension region 122. The doped well 121 can be a P-well, which can be formed by implanting B11 ions with a dose of 3E13 / cm2-6E13 / cm2.

[0111] The junction termination extension region 122 can be formed by first growing an oxide layer on the drift region with a thickness of 100-200nm. Then, the junction termination extension region 122 is formed by photoetching and ion implantation. After that, a thermal oxide layer is grown on the junction termination extension region 122 with a thickness of 100-200nm. High-temperature diffusion at 1150°C or above for 300-500 minutes. Then, photoetching is performed to expose the region of the first surface layer of the drift region where other material layers are to be prepared, so as to further prepare the other material layers.

[0112] In one embodiment, the gate region 120 is at least partially embedded in the source region 130 in a direction parallel to the drift region 100.

[0113] For example, when the source region 130 is formed, a recess can be formed, so that the gate region 120 can be at least partially embedded in the recess when the gate region 120 is formed.

[0114] In one embodiment, the step of forming the gate region 120 on the first surface layer of the drift region 100 comprises forming a second oxide layer on the first surface layer of the drift region 100, wherein the second oxide layer extends to cover the surface of the body region 110, then forming a polysilicon layer on the surface of the second oxide layer away from the surface of the drift region 100, and finally forming an isolation layer on the upper surface of the polysilicon layer.

[0115] In addition, a contact hole for establishing an electrical connection is prepared by a photolithography and etching process, and a drain is prepared by a back thinning, back implantation and back metal process.

[0116] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0117] The technical features of the above-described embodiments can be combined arbitrarily, and in order to make the description simple, not all possible combinations of the technical features in the above-described embodiments are described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present specification.

[0118] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that, include: The drift region has the first type of conductivity. A body region, located on the first surface layer of the drift region and having channels formed thereon, the body region having a second conductivity type, the second conductivity type being opposite to the first conductivity type; A gate region is located on the first surface layer of the drift region and covers the channel, and extends to cover the surface of the body region; The source region is disposed on the surface of the body region away from the drift region and adjacent to the gate region; A resistor structure is disposed on the first surface layer of the drift region, including a first end and a second end opposite to each other, wherein the first end is electrically connected to the gate region. The drain region is located on the second surface layer of the drift region and is electrically connected to the second terminal. The second surface layer is disposed opposite to the first surface layer. The resistor structure includes a first oxide layer, a polysilicon strip, and a conductive layer. The first oxide layer is located on the first surface of the drift region. The polysilicon strip is located on the surface of the first oxide layer away from the drift region. A first contact and a second contact are provided in the extension direction of the polysilicon strip. The first contact serves as the first end, and the second contact serves as the second end. The conductive layer covers the second contact and is electrically connected to the drain region.

2. The semiconductor device according to claim 1, characterized in that, The polycrystalline silicon strips include multiple strips arranged in an array, and the strips are connected in series or in parallel.

3. The semiconductor device according to claim 2, characterized in that, The second contact is located at the end of the polysilicon strip, and the resistor structure further includes: An insulating layer covers the first oxide layer and the surface of the polysilicon strip away from the drift region, and exposes the second contact.

4. The semiconductor device according to claim 3, characterized in that, The source region is disposed adjacent to the insulating layer or the insulating layer is at least partially embedded in the source region.

5. The semiconductor device according to claim 1, characterized in that, The body region includes: A doped well, located on the first surface layer of the drift region and having a second conductivity type; The junction terminal extension region is located on the first surface layer of the drift region and overlaps with the doped trap.

6. The semiconductor device according to claim 2, characterized in that, The gate region is at least partially embedded within the source region in a direction parallel to the drift region.

7. A method for fabricating a semiconductor device, characterized in that, The method includes: A substrate having a first doping type is provided, and a drift region having a first conductivity type is formed on the substrate; A body region is formed on the first surface layer of the drift region, the body region having a second conductivity type, the second conductivity type being opposite to the first conductivity type; A gate region is formed on the first surface layer of the drift region, the gate region covering the channel and extending to cover the surface of the body region; A source region is formed on the first surface layer of the drift region, and the source region is disposed adjacent to the gate region. A resistive structure is formed on the first surface layer of the drift region. The resistive structure includes a first end and a second end opposite to each other. The first end is electrically connected to the gate region. A drain region is formed on the second surface layer of the drift region, the drain region being electrically connected to the second terminal, and the second surface layer being disposed opposite to the first surface layer; wherein the resistor structure formed on the first surface layer of the drift region includes: A first oxide layer is grown on the first surface of the drift region using thermo-oxidative growth. A polycrystalline silicon layer is deposited on the first oxide layer, and P31 ions, N+ ions and P+ ions are implanted into the polycrystalline silicon layer respectively. The polysilicon layer is subjected to photolithography and dry etching to obtain polysilicon strips, wherein the polysilicon strips include multiple strips arranged in an array, and a first contact and a second contact are provided in the extension direction of the polysilicon strips; A conductive layer is covered at the second contact point to establish a connection between the polysilicon strip and the drain region.

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