Semiconductor device

Abstract

This invention relates to semiconductor devices, with the aim of ensuring the operating region and reducing recovery loss in RC-IGBTs. When viewed from above in an RC-IGBT (100, 101), the n0 per unit area of ​​the boundary region (50) is... + The occupancy rate of the source layer (13) is higher than that of the n-type source layer per unit area of ​​the IGBT region (10). + The occupancy rate of the source layer (13) is small, and the p content per unit area of ​​the boundary region (50) is low. + The occupancy ratio of the contact layer (14) is higher than that of the p-type contact layer per unit area of ​​the IGBT region (20). + The occupancy rate of the contact layer (14) is small.

Description

Technical Field

[0001] This invention relates to a reverse-conduction semiconductor device (RC-IGBT) that simultaneously incorporates a freewheeling diode and an insulated-gate bipolar transistor (IGBT). Background Technology

[0002] RC-IGBTs have the following problem: due to the high hole injection efficiency of IGBT cells, holes are injected from the IGBT region into the diode region, resulting in large recovery losses.

[0003] To address this issue, conventionally, a boundary region has been set between the IGBT region and the diode region, and this boundary region has a structure with a collector layer configured directly below the diode unit (e.g., Patent Document 1).

[0004] Patent Document 1: Japanese Patent Application Publication No. 2018-073911

[0005] However, the boundary region does not function as an IGBT or diode, thus becoming an ineffective region that does not actively participate in the energizing process. Therefore, within the limited component area, the boundary region cannot be adequately secured to ensure the effective operating area required to guarantee sufficient energizing capability, resulting in a failure to reduce recovery losses. Summary of the Invention

[0006] The present invention is proposed to solve the aforementioned problems, and its purpose is to ensure the operating range and reduce recovery loss in RC-IGBT.

[0007] The semiconductor device of the present invention has a semiconductor substrate including a drift layer of a first conductivity type. When viewed from above, the semiconductor device has an IGBT region and a diode region sandwiched between them. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface. The IGBT region and the boundary region have: a base layer of a second conductivity type formed on the first main surface side of the drift layer; a source layer of a first conductivity type formed on the first main surface side of the base layer; and a first contact layer of a second conductivity type formed adjacent to the source layer on the first main surface side of the base layer. The second conductivity type has a high impurity concentration. The diode region has: a second conductivity type anode layer formed on the second main surface side of the drift layer; and a first conductivity type cathode layer formed on the second main surface side of the drift layer. When viewed from above, the occupancy ratio of the source layer per unit area of ​​the boundary region is smaller than the occupancy ratio of the source layer per unit area of ​​the IGBT region, and the occupancy ratio of the first contact layer per unit area of ​​the boundary region is smaller than the occupancy ratio of the first contact layer per unit area of ​​the IGBT region.

[0008] The effects of the invention

[0009] According to the semiconductor device of the present invention, since the occupancy ratio of the first contact layer per unit area of ​​the boundary region is smaller than the occupancy ratio of the first contact layer per unit area of ​​the IGBT region, the operating area of ​​the IGBT can be ensured and the recovery loss can be reduced. Attached Figure Description

[0010] Figure 1 This is a top view of a strip-shaped RC-IGBT.

[0011] Figure 2 This is a top view of an island-type RC-IGBT.

[0012] Figure 3 This is a top view of the IGBT area.

[0013] Figure 4 yes Figure 3 A cross-sectional view of the IGBT region at line AA′.

[0014] Figure 5 yes Figure 3 A cross-sectional view of the IGBT region at the BB′ line.

[0015] Figure 6 This is a top view of the diode region.

[0016] Figure 7 yes Figure 6 A cross-sectional view of the diode region at the CC' line.

[0017] Figure 8 yes Figure 6 A cross-sectional view of the diode region at the DD' line.

[0018] Figure 9 This is a top view of the IGBT region, boundary region, and diode region in the RC-IGBT of Embodiment 1.

[0019] Figure 10 yes Figure 9 A cross-sectional view of the IGBT region at line OO′.

[0020] Figure 11 yes Figure 9 A cross-sectional view of the boundary region of Implementation 1 at the PP′ line.

[0021] Figure 12 yes Figure 9 A cross-sectional view of the diode region at the QQ' line.

[0022] Figure 13 yes Figure 9 A cross-sectional view of the IGBT region, boundary region, and diode region at the GG′ line.

[0023] Figure 14 yes Figure 1 or Figure 2 A cross-sectional view of the IGBT region and end region at the EE′ line.

[0024] Figure 15 yes Figure 1 or Figure 2 A cross-sectional view of the diode region and the end region at the FF′ line.

[0025] Figure 16 This is a top view of the IGBT region, boundary region, and diode region in the RC-IGBT of Embodiment 2.

[0026] Figure 17 This is a top view of the IGBT region, boundary region, and diode region in the RC-IGBT of Embodiment 3.

[0027] Figure 18 yes Figure 17 A cross-sectional view of the boundary region of Implementation 3 at the PP′ line.

[0028] Figure 19 This is a top view of the IGBT region, boundary region, and diode region in the RC-IGBT of embodiment 4.

[0029] Figure 20 is Figure 19 A cross-sectional view of the boundary region of Embodiment 4 at the P-P' line of

[0030] Figure 21 A top view of the IGBT region, boundary region, and diode region in the RC-IGBT of Embodiment 5.

[0031] Figure 22 is Figure 21 A cross-sectional view of the boundary region of Embodiment 5 at the P-P' line of

[0032] Figure 23 A top view of the IGBT region, boundary region, and diode region in the RC-IGBT of Embodiment 6.

[0033] Figure 24 is Figure 23 A cross-sectional view of the boundary region of Embodiment 6 at the Q-Q' line of Specific Embodiments

[0034] <A. Embodiment 1>

[0035] <A-1. Planar Structure of RC-IGBT>

[0036] Figure 1 A top view of the semiconductor device of Embodiment 1, i.e., RC-IGBT (Reverse Conducting IGBT) 100. Additionally, Figure 2 A top view of the semiconductor device of Embodiment 1, i.e., RC-IGBT 101, which has a structure different from that of RC-IGBT 100.

[0037] Since RC-IGBT 100 has IGBT regions 10 and diode regions 20 arranged in stripes, it is also called "strip type". Since RC-IGBT 101 has a structure in which the IGBT region 10 surrounds the peripheries of multiple diode regions 20, it is also called "island type".

[0038] <A-2. Planar Structure of Strip Type>

[0039] Refer to Figure 1The planar structure of the strip-shaped RC-IGBT 100 will be described below. The RC-IGBT 100 has an IGBT region 10, a diode region 20, an end region 30, a pad region 40, and a boundary region 50. In the case of the RC-IGBT 100, when viewed from above, the IGBT region 10 and the diode region 20 are arranged with the boundary region 50 sandwiched between them, which is also the case in the RC-IGBT 101 described later. The IGBT region 10, the diode region 20, and the boundary region 50 extend from one end of the RC-IGBT 100 to the other end. The IGBT region 10 and the diode region 20 are arranged in a strip shape, sandwiching the boundary region 50, in a direction orthogonal to their extension direction.

[0040] exist Figure 1 The diagram shows three IGBT regions 10 and two diode regions 20, each diode region 20 being sandwiched between IGBT regions 10 by a boundary region 50. However, the number of IGBT regions 10 and diode regions 20 is not limited to this. The number of IGBT regions 10 can be greater than or equal to three or less than or equal to three, and the number of diode regions 20 can be greater than or equal to two or less than or equal to two. Alternatively, it could be... Figure 1 The configurations of IGBT region 10 and diode region 20 are interchanged, resulting in a structure where all IGBT regions 10 are sandwiched between diode regions 20 across a boundary region 50. Alternatively, the RC-IGBT 100 can also be a structure in which one IGBT region 10 and one diode region 20 are arranged adjacent to each other across a boundary region 50.

[0041] exist Figure 1 In this configuration, a boundary region 50 is provided throughout the entire area between the IGBT region 10 and the diode region 20. However, the boundary region 50 may be provided only for a portion of the area between the IGBT region 10 and the diode region 20. Alternatively, the boundary region 50 may be provided between the diode region 20 and the end region 30.

[0042] like Figure 1As shown, a pad region 40 is provided adjacent to the lower side in the paper plane of the lowermost IGBT region 10 in the paper plane. The pad region 40 is a region where a control pad 41 for controlling the RC-IGBT 100 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. In order to maintain the breakdown voltage of the RC-IGBT 100, an end region 30 is provided around the region where the cell region and the pad region 40 are combined. A known breakdown voltage maintaining structure can be appropriately and selectively provided in the end region 30. The breakdown voltage maintaining structure is provided on the surface side, i.e., the first main surface side, of the RC-IGBT 100. The breakdown voltage maintaining structure can be an FLR that surrounds the cell region with a p-type end well layer of a p-type semiconductor, or a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type well layer having a concentration gradient. The number of annular p-type end well layers for the FLR or the concentration distribution for the VLD can be appropriately selected corresponding to the breakdown voltage design of the RC-IGBT 100. In addition, a p-type end well layer can be provided over substantially the entire region of the pad region 40. IGBT cells or diode cells can also be provided in the pad region 40.

[0043] The control pad 41 is, for example, a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sensing diode pads 41d, 41e. The current sensing pad 41a is a control pad for detecting the current flowing in the cell region of the RC-IGBT 100, and is a control pad electrically connected to a part of the IGBT cells or diode cells in the cell region. When a current flows in the cell region of the RC-IGBT 100, a current of one fraction to one ten-thousandth of the current flowing in the entire cell region flows through this control pad.

[0044] The Kelvin emitter pad 41b and the gate pad 41c are control pads for applying a gate drive voltage for on / off control of the RC-IGBT 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer 15 of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode 11a of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer 15 can also be electrically connected via a p + type contact layer 14. The temperature sensing diode pads 41d, 41e are control pads electrically connected to the anode and cathode of the temperature sensing diode provided in the RC-IGBT 100. The temperature sensing diode pads 41d, 41e measure the voltage between the anode and cathode of an unillustrated temperature sensing diode provided in the cell region, thereby measuring the temperature of the RC-IGBT 100.

[0045] <A-3. Island-shaped planar structure>

[0046] Reference Figure 2 , the planar structure of the island-type RC-IGBT 101 will be described.

[0047] The RC-IGBT 101 has an IGBT region 10, a diode region 20, an end region 30, a pad region 40, and a boundary region 50. The diode regions 20 are arranged in multiple rows and columns longitudinally ( Figure 2 the up-and-down direction in the plane of the paper) and transversely ( Figure 2 the left-and-right direction in the plane of the paper) within the RC-IGBT 101. The diode regions 20 are surrounded by the IGBT region 1 surrounding the diode regions 20 through the boundary region 50. That is, multiple diode regions 20 are arranged in an island shape within the IGBT region 10.

[0048] In Figure 2 , eight diode regions 20 arranged in a matrix with 4 columns longitudinally and 2 rows transversely are shown. However, the number and arrangement of the diode regions 20 are not limited to this. As long as at least one diode region 20 is scattered and arranged within the IGBT region 10 and each diode region 20 is surrounded by the IGBT region 10.

[0049] In Figure 2 , the boundary region 50 is provided in all regions between the IGBT region 10 and the diode region 20. However, it is sufficient that the boundary region 50 is provided in at least a part of the region between the IGBT region 10 and the diode region 20.

[0050] As Figure 2 shown, the pad region 40 is provided adjacent to the lower side in the plane of the paper of the IGBT region 10. The pad region 40 has the same structure as the pad region 40 in the strip-type RC-IGBT, so the description thereof is omitted here.

[0051] <A-4. Normal Structure of IGBT Region>

[0052] Figure 3 is the enlarged top view of the IGBT region 10 of the RC-IGBTs 100 and 101 surrounded by the dashed line 82 in Figure 1 or Figure 2 .

[0053] As Figure 3 shown, the IGBT region 10 has an active trench gate 11, a dummy trench gate 12, an n + -type source layer 13, and a p + -type contact layer 14.

[0054] The active trench gate 11 and the dummy trench gate 12 penetrate through the p-type base layer 15 from the first main surface of the semiconductor substrate to reach the n -Type drift layer 1. The active trench gate 11 and the dumb trench gate 12 are also collectively referred to as the trench gate. The active trench gate 11 and the dumb trench gate 12 are arranged in a strip shape. In the RC-IGBT 100, the active trench gate 11 and the dumb trench gate 12 are positioned along the length of the IGBT region 10 ( Figure 3 Extending along the left-right direction of the paper (as shown in the image), the length direction of the IGBT region 10 becomes the length direction of the active trench gate 11 and the dumb trench gate 12. On the other hand, in the RC-IGBT 101, the distinction between the length and width directions at the IGBT region 10 is not particularly limited, and can be... Figure 2 The left and right directions of the paper plane are set as the length directions of the active trench gate 11 and the dumb trench gate 12. Alternatively, the following can be used: Figure 2 The vertical direction of the paper is set as the length direction of the active trench gate 11 and the dumb trench gate 12.

[0055] The extending direction of the active trench gate 11 and the dumb trench gate 12 is also referred to as the first direction. In other words, the active trench gate 11 and the dumb trench gate 12 extend in the first direction. Moreover, the active trench gate 11 and the dumb trench gate 12 are arranged in a second direction orthogonal to the first direction.

[0056] The active trench gate 11 includes: a gate trench insulating film 11b formed on the inner wall surface of a trench formed in the semiconductor substrate of the IGBT region 10; and a gate trench electrode 11a disposed in the trench through the gate trench insulating film 11b. The dumb trench gate 12 includes: a dumb trench insulating film 12b formed on the inner wall surface of a trench formed in the semiconductor substrate; and a dumb trench electrode 12a disposed in the trench through the dumb trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dumb trench electrode 12a of the dumb trench gate 12 is electrically connected to the emitter electrode 6 disposed on the first main surface of the RC-IGBT 100, 101.

[0057] n + The source layer 13 is configured to contact the gate trench insulating film 11b on both sides of the active trench gate 11 in the width direction. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration greater than or equal to 1.0 × 10⁻⁶. 17 / cm 3 And less than or equal to 1.0 × 10 20 / cm 3 n + The source layer 13 is along the extension direction of the active trench gate 11 and p + The contact layers 14 are alternately arranged. +The contact layer 14 is not only disposed on both sides of the active trench gate 11, but also between two adjacent dumb trench gates 12. + The p-type contact layer 14 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration greater than or equal to 1.0 × 10⁻⁶. 15 / cm 3 And less than or equal to 1.0 × 10 20 / cm 3 .

[0058] like Figure 3 As shown, in the IGBT region 10, groups consisting of three active trench gates 11 and groups consisting of three dumb trench gates 12 are arranged alternately. The number of active trench gates 11 included in a group of one active trench gate 11 is not limited to three; it can be one or more. Similarly, the number of dumb trench gates 12 included in a group of one dumb trench gate 12 is not limited to three; it can be one or more. Furthermore, the number of dumb trench gates 12 can also be zero. That is, all trenches in the IGBT region 10 can be configured as active trench gates 11.

[0059] Figure 4 yes Figure 3 A cross-sectional view of the IGBT region 10 at line AA′. (See figure) Figure 4 As shown, the IGBT region 10 of RC-IGBTs 100 and 101 has an n-shaped structure formed by a semiconductor substrate. - Type 1 drift layer. - The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration greater than or equal to 1.0 × 10⁻⁶. 12 / cm 3 And less than or equal to 1.0 × 10 15 / cm 3 .

[0060] Semiconductor substrate in Figure 4 The middle is from n + Type source layer 13 and p + The range extends from the p-type contact layer 14 to the p-type collector layer 16. That is, the semiconductor substrate forms an n-type collector layer within the IGBT region 10. - Type 1 drift layer, n-type carrier accumulation layer, p-type base layer, n + Type source layer 13, p + The n-type contact layer 14, the n-type buffer layer 3, and the p-type collector layer 16 are then used. + Type source layer 13 and p + Type contact layer 14 Figure 4 The upper side of the paper surface is called the first main surface of the semiconductor substrate, where the p-type collector layer 16 is located. Figure 4 The end face on the lower side of the paper in the semiconductor substrate is called the second main surface.

[0061] The first main surface of the semiconductor substrate is the surface side of the RC-IGBTs 100 and 101, and the second main surface of the semiconductor substrate is the back side of the RC-IGBTs 100 and 101. Within the cell region, i.e., the IGBT region 10, the RC-IGBTs 100 and 101 have an n-fold distance between the first main surface and the second main surface opposite to the first main surface. - Type 1 drift layer.

[0062] like Figure 4 As shown, in IGBT region 10, at n - The first principal surface of the drift layer 1 is provided with a concentration ratio of n-type impurities to n - The n-type carrier accumulation layer 2 has a high n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration greater than or equal to 1.0 × 10⁻⁶. 13 / cm 3 And less than or equal to 1.0 × 10 17 / cm 3 The n-type carrier accumulation layer 2 is constructed by implanting n-type impurity ions into the n-type carrier accumulation layer. - The semiconductor substrate with the n-type drift layer 1 is then annealed to diffuse the implanted n-type impurities to the n-type layer. - The n-type drift layer 1 is formed within the semiconductor substrate. The n-type carrier accumulation layer 2 reduces current loss when current flows in the IGBT region 10. Alternatively, the n-type carrier accumulation layer 2 and the n... - The drift layers 1 and 2 are collectively referred to as the drift layers.

[0063] Furthermore, RC-IGBTs 100 and 101 may also lack an n-type carrier storage layer 2 in the IGBT region 10. In this case, it becomes... Figure 4 The region of the n-type carrier accumulation layer 2 is also provided with n - The structure of drift layer 1.

[0064] A p-type base layer 15 is disposed on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is greater than or equal to 1.0 × 10⁻⁶. 12 / cm 3 And less than or equal to 1.0 × 10 19 / cm 3The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11 and the dumb trench insulating film 12b of the dumb trench gate 12. On the first main surface side of the p-type base layer 15, an n-type base layer is disposed in contact with the gate trench insulating film 11b of the active trench gate 11. + Type source layer 13, in the remaining region, with n + p-type source layer 13 is disposed adjacent to it. + Type contact layer 14. + Type source layer 13 and p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. Furthermore, p... + The p-type contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15. When it is not necessary to target the p-type impurities... + When the p-type contact layer 14 and the p-type base layer 15 are distinguished, they can also be referred to together as the p-type base layer.

[0065] In n - The second main surface of the drift layer 1 is provided with a concentration ratio of n-type impurities to n - The n-type buffer layer 3 is a high-density n-type drift layer 1. The n-type buffer layer 3 is provided to suppress depletion layer breakdown extending from the p-type base layer 15 towards the second main face when the RC-IGBT 100, 101 is in an off state. The n-type buffer layer 3 is, for example, formed by using phosphorus (P) or proton (H) atoms. + Any one of the following, or both, is injected into the constituent n. - The n-type drift layer 1 is formed on a semiconductor substrate. The concentration of n-type impurities in the n-type buffer layer 3 is greater than or equal to 1.0 × 10⁻⁶. 12 / cm 3 And less than or equal to 1.0 × 10 18 / cm 3 Alternatively, n-type buffer layer 3 and n - The drift layers 1 and 2 are collectively referred to as the drift layers.

[0066] Furthermore, RC-IGBTs 100 and 101 may also not have an n-type buffer layer 3 in the IGBT region 10. In this case, it becomes... Figure 4 The n-type buffer layer 3 area is also provided with n - The structure of drift layer 1.

[0067] A p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. That is, on the n-type buffer layer 3... - A p-type collector layer 16 is disposed between the p-type drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is greater than or equal to 1.0 × 10⁻⁶. 16 / cm 3 And less than or equal to 1.0 × 1020 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is disposed not only in the IGBT region 10 but also in the terminal region 30, and the portion of the p-type collector layer 16 disposed in the terminal region 30 constitutes the p-type terminal collector layer 16a. Alternatively, a portion of the p-type collector layer 16 may extend from the IGBT region 10 into the diode region 20.

[0068] like Figure 4 As shown, in the IGBT region 10, a layer is formed that extends from the first main surface of the semiconductor substrate through the p-type base layer 15 to the n-type base layer 15. - Multiple trenches are formed in the drift layer 1. An active trench gate 11 is constructed by forming a gate trench electrode 11a within a portion of these trenches, separated by a gate trench insulating film 11b. The gate trench electrode 11a is connected to the n-type drift layer 1 through the gate trench insulating film 11b. - The drift layer 1 is opposite to the type. Additionally, a dumb trench electrode 12a is formed by providing a dumb trench electrode 12a in another portion of the trench, separated by a dumb trench insulating film 12b. The dumb trench electrode 12a is separated from the n-type drift layer by the dumb trench insulating film 12b. - The drift layer 1 is opposite to the active trench gate 11. The gate trench insulating film 11b of the active trench gate 11 is opposite to the p-type base layer 15 and the n-type base layer 15. + The p-type source layer 13 is in contact. If a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0069] like Figure 4 As shown, an interlayer insulating film 4 is disposed on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not disposed, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi alloyed from titanium and silicon (Si). Figure 4 As shown, the blocking metal 5 and n + Type source layer 13, p + The contact layer 14 and the dummy trench electrode 12a make ohmic contact with n. + Type source layer 13, p + The contact layer 14 and the dumb groove electrode 12a are electrically connected.

[0070] In the IGBT region 10, an emitter electrode 6 is disposed on top of the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy, such as an aluminum-silicon alloy (Al-Si alloy). The emitter electrode 6 may also be a multilayer structure consisting of an electrode formed of an aluminum alloy and a coating formed on the electrode by chemical plating or electroplating. The coating formed by chemical plating or electroplating may be, for example, a nickel (Ni) coating. In addition, in small areas such as between adjacent interlayer insulating films 4, or in areas where the emitter electrode 6 cannot be well embedded, tungsten, which has better embedding properties than the emitter electrode 6, may be disposed, and the emitter electrode 6 may be disposed on top of the tungsten.

[0071] Furthermore, RC-IGBT 100 and 101 can also be in the IGBT region 10 without the blocking metal 5, in n + Type source layer 13, p + The emitter electrode 6 is directly disposed on the contact layer 14 and the dummy trench electrode 12a. Alternatively, the blocking metal 5 may be disposed only on n. + Above the n-type semiconductor layer such as source layer 13. The blocking metal 5 and the emitter electrode 6 can be combined and called the emitter electrode.

[0072] In addition, Figure 4 In this case, the interlayer insulating film 4 is not formed on the dumb trench electrode 12a of the dumb trench gate 12, but the interlayer insulating film 4 can also be formed on the dumb trench electrode 12a of the dumb trench gate 12. When the interlayer insulating film 4 is formed on the dumb trench electrode 12a of the dumb trench gate 12, in... Figure 4 The emitter electrode 6 and the dumb trench electrode 12a can be electrically connected at the section outside the AA section shown.

[0073] A collector electrode 7 is disposed on the second main surface side of the p-type collector layer 16. Similar to the emitter electrode 6, the collector electrode 7 can be formed of aluminum alloy, or it can be a multilayer structure composed of aluminum alloy and a coating. Alternatively, the collector electrode 7 can have a different structure than the emitter electrode 6. The collector electrode 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to it.

[0074] Figure 5 yes Figure 3 A cross-sectional view of the IGBT region 10 at the BB′ line. Figure 5 The cross-sectional structure shown is similar to Figure 4 shown Figure 3 The difference in the cross-sectional structure of the IGBT region 10 at the AA′ line is that, on the first main surface side of the semiconductor substrate, the part in contact with the gate trench insulating film 11b of the active trench gate 11 is p. + Type 14 contact layer instead of n + Type source layer 13. That is, as shown in Figure 13. Figure 4 As shown, n + type source layer 13 is selectively provided on the first main surface side of the p-type base layer. In addition, the p-type base layer mentioned here refers to the p-type base layer formed by combining the p-type base layer 15 and the p + type contact layer 14, which is collectively referred to as the p-type base layer.

[0075] <A-5. Normal Structure of Diode Region>

[0076] Figure 6 It is a top view of the diode region 20 obtained by magnifying the region surrounded by the dashed line 83 of the RC-IGBTs 100 and 101 in Figure 1 or Figure 2 . As shown in Figure 6 , the diode region 20 has a first dummy trench gate, i.e., a diode trench gate 21, a p + type contact layer 24, and a p-type anode layer 25.

[0077] The diode trench gate 21 extends along the first main surface of the RC-IGBTs 100 and 101 from one end side of the unit region, i.e., the diode region 20, to the opposite end side. The diode trench gate 21 has: a diode trench insulating film 21b formed on the inner wall surface of the trench formed in the semiconductor substrate of the diode region 20; and a diode trench electrode 21a provided in the trench隔着 the diode trench insulating film 21b. The diode trench gate 21 penetrates the p-type anode layer 25 from the first main surface of the semiconductor substrate and reaches the n - type drift layer 1. In addition, the diode trench gate 21 extends in the same first direction as the active trench gate 11 and the dummy trench gate 12 in the IGBT region 10 and the boundary region 50, and is arranged in the second direction.

[0078] The diode trench electrode 21a is opposite to the n - type drift layer 1隔着 the diode trench insulating film 21b. Between two adjacent diode trench gates 21, a p + type contact layer 24 and a p-type anode layer 25 are alternately provided in the length direction of the diode trench gate 21. The p + type contact layer 24 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is greater than or equal to 1.0×10 15 / cm 3 and less than or equal to 1.0×10 20 / cm 3 . The p-type anode layer 25 is formed on the first main surface side of the n - type drift layer 1. The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is greater than or equal to 1.0×10 12 / cm3 And less than or equal to 1.0 × 10 19 / cm 3 .

[0079] Figure 7 yes Figure 6 A cross-sectional view of diode region 20 at the CC' line. RC-IGBTs 100 and 101, like IGBT region 10, also have an n-shaped structure made of a semiconductor substrate in diode region 20. - Type drift layer 1. Diode region 20 n - n-type drift layer 1 and IGBT region 10 - The drift layer 1 is continuously formed as a single unit, constructed through the same semiconductor substrate.

[0080] exist Figure 7 The semiconductor substrate is from p + Type contact layer 24 to n + The area up to the cathode layer 26. That is, the semiconductor substrate forms an n-type cathode layer in the diode region 20. - Type 1 drift layer, type 2 n-type carrier accumulation layer, type 2 p-type anode layer, type 25 p + Type 24 contact layer, type n buffer layer 3 and n + Type 26 cathode layer. p + Type contact layer 24 Figure 7 The upper side of the paper surface is called the first principal surface of the semiconductor substrate, and n + Type 26 cathode layer Figure 7 The underside of the paper in the image is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate in diode region 20 and the first main surface of the semiconductor substrate in IGBT region 10 are the same surface, and the second main surface of the semiconductor substrate in diode region 20 and the second main surface of the semiconductor substrate in IGBT region 10 are the same surface.

[0081] like Figure 7 As shown, in diode region 20, similarly to IGBT region 10, in n - An n-type carrier accumulation layer 2 is disposed on the first principal surface side of the n-type drift layer 1. - An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier storage layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same structure as those provided in the IGBT region 10. Furthermore, the RC-IGBTs 100 and 101 may also have a structure in which the n-type carrier storage layer 2 is not present in the diode region 20, regardless of the presence or absence of the n-type carrier storage layer 2 in the IGBT region 10. Additionally, similar to the IGBT region 10, the n-type buffer layer 3 may also be provided in the diode region 20. -The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 are collectively referred to as the drift layer.

[0082] In diode region 20, a p-type anode layer 25 is disposed on the first main surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is disposed on the n-type carrier accumulation layer 2. - Between the p-type drift layer 1 and the first main surface. The concentration of p-type impurities in the p-type anode layer 25 can also be the same as the concentration of p-type impurities in the p-type base layer 15 of the IGBT region 10. In this case, both the p-type anode layer 25 and the p-type base layer 15 can be formed simultaneously. Alternatively, the concentration of p-type impurities in the p-type anode layer 25 can be lower than the concentration of p-type impurities in the p-type base layer 15 of the IGBT region 10. In this case, since the amount of holes injected into the diode region 20 during diode operation is reduced, the recovery loss during diode operation is reduced.

[0083] A p-type anode layer 25 is provided on the first main surface side. + Type contact layer 24. p + The concentration of p-type impurities in the p-type contact layer 24 can be related to the concentration of p-type impurities in the IGBT region 10. + The concentration of p-type impurities in the contact layer 14 can be the same or different. + The contact layer 24 forms the first main surface of the semiconductor substrate. + The concentration of p-type impurities in the p-type contact layer 24 is higher than the concentration of p-type impurities in the p-type anode layer 25. When it is not necessary to [address p-type impurities]... + When the p-type contact layer 24 and the p-type anode layer 25 are distinguished, they can also be referred to together as the p-type anode layer.

[0084] In diode region 20, an n-type buffer layer 3 is provided on the second main surface side. + Type 26 cathode layer. + Type 26 cathode layer is disposed in n - Between drift layer 1 and the second principal surface. + The n-type cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 / cm 3 And less than or equal to 1.0 × 10 21 / cm 3 n + The cathode layer 26 is disposed in part or all of the diode region 20. + The p-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. Furthermore, although not shown, it is also possible to selectively implant p-type impurities into the formed n-type cathode layer. + The region of the cathode layer 26 thus forms an n +A portion of the region of the p-type cathode layer 26 is designated as a p-type cathode layer.

[0085] like Figure 7 As shown, in diode region 20, a p-type anode layer is formed that extends from the first main surface of the semiconductor substrate through the p-type anode layer 25 to the n-type anode layer. - Multiple trenches are formed in the drift layer 1. Diode trench electrodes 21a are disposed within these multiple trenches, separated by a diode trench insulating film 21b, thereby forming the diode trench gate 21. The diode trench electrodes 21a are connected to the diode trench gate 21 through the diode trench insulating film 21b. - Type drift layer 1 relative.

[0086] like Figure 7 As shown, in the diode trench electrode 21a and p + A barrier metal 5 is disposed above the contact layer 24. The barrier metal 5 is connected to the diode trench electrode 21a and p. + The contact layer 24 forms an ohmic contact with the diode trench electrode 21a and p. + The contact layer 24 is electrically connected. The barrier metal 5 in the diode region 20 can have the same structure as the barrier metal 5 in the IGBT region 10.

[0087] In diode region 20, emitter electrode 6 is disposed above blocking metal 5. Emitter electrode 6 in diode region 20 is continuously formed with emitter electrode 6 in IGBT region 10. Alternatively, RC-IGBTs 100 and 101 may not have blocking metal 5 in diode region 20, allowing the diode trench electrodes 21a and p... + The contact layer 24 and the emitter electrode 6 make ohmic contact.

[0088] In addition, Figure 7 In this case, no interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, but an interlayer insulating film 4 can also be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the dumb trench electrode 12a of the dumb trench gate 12, in Figure 7 The emitter electrode 6 and the diode trench electrode 21a can be electrically connected at the section outside the CC′ section shown.

[0089] In n + A collector electrode 7 is disposed on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 and the collector electrode 7 of the IGBT region 10 are continuously formed. The collector electrode 7 and the n... + The cathode layer 26 makes an ohmic contact with n. + Type 26 cathode layer is electrically connected.

[0090] Figure 8 is Figure 6 A cross-sectional view of the diode region 20 at the D-D' line of Figure 8 The cross-sectional structure shown is different from that of the cross-sectional structure of the diode region 20 at the C-C' line of Figure 7 shown in that a p Figure 6 type contact layer 24 is not provided between the p-type anode layer 25 and the barrier metal 5, and the p-type anode layer 25 forms the first main surface of the semiconductor substrate. That is, + the p-type contact layer 24 shown is selectively provided on the first main surface side of the p-type anode layer 25. Figure 7 p shown + type contact layer 24 is selectively provided on the first main surface side of the p-type anode layer 25.

[0091] <A-6. Boundary Region between IGBT Region and Diode Region>

[0092] Figure 9 is a top view of the region including the IGBT regions 10, the boundary region 50, and the diode region 20 of the RC-IGBTs 101 and 102, enlarged. Figure 9 The G-G' line shown in Figure 1 or Figure 2 is the same as the G-G' line in Figure 10 is a cross-sectional view of the IGBT region 10 along the O-O' line in Figure 9 Figure 11 is a cross-sectional view of the boundary region 50 along the P-P' line in Figure 9 Figure 12 is a cross-sectional view of the diode region 20 along the Q-Q' line in Figure 9

[0093] In Figure 9 the structure of the IGBT region 10 and the diode region 20 is the same as that shown in Figure 3 and Figure 6 The basic structure of the boundary region 50 existing between the IGBT region 10 and the diode region 20 is the same as that of the IGBT region 10. However, when viewed from above, the ratio of the n + type source layer 13 in the unit area of the boundary region 50 (hereinafter, referred to as "the occupancy ratio of the n + type source layer 13") is smaller than the occupancy ratio of the n + type source layer 13 in the IGBT region 10.

[0094] To ensure the latching tolerance of the IGBT, the p + [ + ]] type contact layer 14 is provided adjacent to the n + type source layer 13. In the boundary region 50, since the n + ​​​The occupancy rate of the source layer 13 is small, therefore, similarly, when viewed from above, the p0 content per unit area of ​​the boundary region 50 is significantly higher. + The percentage of type contact layer 14 (hereinafter referred to as "p") + The occupancy ratio of the contact layer 14 is also set small. According to the structure of the RC-IGBT 100 and 101 of this embodiment, by using highly efficient hole injection p in the boundary region 50... + The occupancy ratio of the contact layer 14 is set to be small, thereby reducing the hole injection efficiency in the boundary region 50. Therefore, the inflow of holes from the boundary region 50 to the diode region 20 during diode forward operation is suppressed.

[0095] Additionally, p in boundary region 50 + The occupancy ratio of the contact layer 14 can also be higher than that of the p-type contact layer in the diode region 20. + The occupancy rate of the contact layer 24 is small. In other words, the p-type contact layer in the diode region 20 has a small occupancy rate. + The occupancy ratio of the contact layer 24 can also be higher than that of the p in the boundary region 50. + The contact layer 14 has a large occupancy rate. As a result, the forward voltage of the diode region 20 is lower, and current flows more easily. Consequently, less current flows into the boundary region 50, which suppresses the recovery current generated at the boundary region 50 and thus reduces recovery losses.

[0096] p disposed between the dumb trench gates 12 in the boundary region 50 + The contact layer 14 can be configured similarly to that in the IGBT region 10, covering the entire area between the dumb trench gates 12, but preferably as shown in the image. Figure 9 As shown, reduce the interaction between the boundary region 50 and n. + p-type source layer 13 is adjacent to the p-type source layer 13 + The configuration area of ​​the contact layer 14. Additionally, p-type contact layers may not be configured between the dumb trench gates 12 in the boundary region 50. + Type 14 contact layer.

[0097] like Figure 11 As shown, in the boundary region 50, the emitter electrode 6 contacts the semiconductor substrate via the barrier metal 5. The emitter electrode 6, via the barrier metal 5, not only contacts the n... + Type source layer 13 and p + The n-type contact layer 14 is in contact with the p-type base layer 15. During forward operation of the diode region 20, the n-type base layer 15 is contacted from the back side. + A portion of the electrons injected into the cathode layer 26 flows toward the emitter electrode 6 of the boundary region 50. At this time, if electrons flow through the p-type cathode layer 26, which is configured to achieve good contact resistance through ohmic contact with the barrier metal 5, then... +type contact layer 14, then due to p + type contact layer 14 having a high hole injection efficiency, a large number of holes are injected into the n - type drift layer 1, resulting in an increase in recovery loss.

[0098] In the RC-IGBTs 100, 101, by reducing the occupancy ratio of the n + type source layer 13 and the p + type contact layer 14 in the boundary region 50, the exposed area of the p-type base layer 15 on the first main surface of the semiconductor substrate is increased. Moreover, since the exposed portion of the p-type base layer 15 contacts the emitter electrode 6 via the barrier metal 5 in the contact hole of the interlayer insulating film 4, electrons are also discharged from the exposed portion to the emitter electrode 6 side. Since the p-type base layer 15 has a lower p-type impurity concentration than the p + type contact layer 14 and a lower hole injection efficiency, the recovery loss is reduced. The more the region where the p-type base layer 15 contacts the emitter electrode 6 via the barrier metal 5, the more the recovery loss can be reduced, but it can be designed to match the required loss.

[0099] Figure 13 is along Figure 9 the G-G' line of the RC-IGBTs 100, 101. As Figure 13 shown, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 and the boundary region 50 is set to extend a distance U1 from the boundary between the boundary region 50 and the diode region 20 toward the diode region 20. Thus, by setting the p-type collector layer 16 to extend into the diode region 20, the distance between the n + type cathode layer 26 and the active trench gate 11 in the diode region 20 can be increased. Thereby, when the diode region 20 operates as a freewheeling diode and a gate drive voltage is applied to the gate trench electrode 11a, the current flowing from the channel formed adjacent to the active trench gate 11 in the IGBT region 10 to the n + type cathode layer 26 can be suppressed. The distance U1 is, for example, 100 μm. In addition, depending on the use of the RC-IGBTs 100, 101, the distance U1 can be smaller than 100 μm or can be 0.

[0100] <A-7. Normal Structure of the Terminal Region>

[0101] Next, the structure of the terminal region 30 of the RC-IGBTs 100, 101 will be described. Figure 14 is Figure 1 or Figure 2 a cross-sectional view of the RC-IGBTs 100, 101 at the E-E' line, showing the structure from the IGBT region 10 to the terminal region 30. Figure 15 is Figure 1 or Figure 2 The cross-sectional view of RC-IGBT 100, 101 at the FF′ line shows the structure from diode region 20 to end region 30.

[0102] like Figure 14 and Figure 15 As shown, the end region 30 has n between the first main surface and the second main surface of the semiconductor substrate. - Type 1 drift layer. The first and second main surfaces of the end region 30 are the same as the first and second main surfaces of the IGBT region 10 and the diode region 20, respectively. Additionally, the n-type drift layer of the end region 30... - Type-type drift layer 1 is respectively connected to the n-type IGBT region 10 and diode region 20. - The drift layer 1 has the same structure and is integrated with the continuous terrain.

[0103] In n - The first main surface side of the drift layer 1, i.e., the first main surface of the semiconductor substrate and n - A p-type end-well layer 31 is disposed between the p-type drift layers 1. The p-type end-well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is greater than or equal to 1.0 × 10⁻⁶. 14 / cm 3 And less than or equal to 1.0 × 10 19 / cm 3 The p-type end-well layer 31 is configured to surround the cell region containing the IGBT region 10 and the diode region 20. The p-type end-well layer 31 consists of multiple rings, the number of which is appropriately selected corresponding to the voltage withstand design of the RC-IGBTs 100 and 101. Additionally, an n-ring surround is provided on the outer edge of the p-type end-well layer 31 to enclose it. + Type 32 channel cutoff layer.

[0104] In n - A p-type terminal collector layer 16a is provided between the p-type drift layer 1 and the second main surface of the semiconductor substrate. The p-type terminal collector layer 16a is integrally formed with the p-type collector layer 16 provided in the cell region. Therefore, it may also include the p-type terminal collector layer 16a and be referred to as the p-type collector layer 16. In addition, in such Figure 1 In the structure shown in the RC-IGBT 100, where the diode region 20 and the end region 30 are arranged adjacently, as in... Figure 15 As shown, the p-type terminal collector layer 16a is configured to extend a distance U2 into the diode region 20. Thus, by extending the p-type terminal collector layer 16a into the diode region 20, the n-type terminal collector layer of the diode region 20 is... +The distance between the p-type cathode layer 26 and the p-type end well layer 31 is set large, which can suppress the p-type end well layer 31 from acting as the anode of the diode. The distance U2 is, for example, 100 μm.

[0105] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is continuously formed integrally from the cell region including the IGBT region 10 and the diode region 20 to the end region 30. On the other hand, an emitter electrode 6 continuous from the cell region and an end electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the end region 30.

[0106] The emitter electrode 6 and the end electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 is, for example, sinSiN (semi-insulating Silicon Nitride). The end electrode 6a and the p-type end well layer 31 and n + type channel cut-off layer 32 are electrically connected via a contact hole formed in an interlayer insulating film 4 provided on the first main surface of the end region 30. In addition, an end protective film 34 is provided in the end region 30 so as to cover the emitter electrode 6, the end electrode 6a, and the semi-insulating film 33. The end protective film 34 is formed of, for example, polyimide.

[0107] <A-8. Effect>

[0108] The boundary region 50 has the same structure as the IGBT region 10 (p-type collector layer 16, n - type drift layer 1, p-type base layer 15, n + type source layer 13, p + type contact layer 14, p-type base layer 15, barrier metal 5, emitter electrode 6). When viewed from above in the boundary region 50, the ratio of the n + type source layer 13 and p + type contact layer 14 (hereinafter, also referred to as "occupation ratio") in the unit area is smaller than the occupation ratio of the n + type source layer 13 and p + type contact layer 14 in the IGBT region 10. Therefore, the current-carrying capacity of the boundary region 50 is worse than that of the IGBT region 10, but since it operates as an IGBT region, the RC-IGBTs 100 and 101 can ensure sufficient current-carrying capacity. In addition, through the boundary region 50, the holes flowing in from the IGBT region 10 during the forward operation of the diode region 20 can be reduced, so that the recovery loss can be reduced.

[0109] The occupation ratio of the p + type contact layer 14 in the boundary region 50 is smaller than the p +The occupancy ratio of the p-type contact layer 14 is small. Therefore, the on-voltage when the diode region 20 operates forward is lowered, and current can flow more easily. As a result, relatively less current flows into the boundary region 50, and the recovery current generated at the boundary region 50 can be suppressed, thus reducing the recovery loss.

[0110] In the boundary region 50, the emitter electrode 6 is in contact with the n + -type source layer 13, p + -type contact layer 14, and p-type base layer 15 via the barrier metal 5. When the diode region 20 operates forward, electrons are injected from the n + -type cathode layer 26 on the back side, and a part of the injected electrons flows to the emitter electrode 6 in the boundary region 50. At this time, if electrons flow through the p + -type contact layer 14 arranged to obtain a good contact resistance through ohmic contact with the barrier metal 5, then due to the high hole injection efficiency of the p + -type contact layer 14, a large amount of holes are injected into the n - -type drift layer 1, resulting in an increase in the recovery loss. In the RC-IGBTs 100 and 101, by reducing the n + -type source layer 13 and p + -type contact layer 14 in the boundary region 50, the area of the p-type base layer 15 exposed to the first main surface of the semiconductor substrate is increased. Moreover, since the exposed portion of the p-type base layer 15 is actively in contact with the emitter electrode 6 via the barrier metal 5, electrons are also discharged from this exposed portion to the emitter electrode 6. Since the p-type base layer 15 has a lower p-type impurity concentration and a lower hole injection efficiency compared to the p + -type contact layer 14, the recovery loss can be reduced.

[0111] The p-type impurity concentration of the p-type anode layer 25 in the diode region 20 can also be lower than the p-type impurity concentration of the p-type base layer 15 in the IGBT region 10 and the boundary region 50. By making the p-type anode layer 25 in the diode region 20 a low concentration, the hole injection efficiency can be further suppressed, and the recovery loss can be reduced.

[0112] The width of the boundary region 50 can also be larger than the thickness of the semiconductor substrate. By making the width of the boundary region 50 larger than the thickness of the semiconductor substrate, the hole injection from the IGBT region 10 to the diode region 20 can be reliably suppressed, and the recovery loss can be reduced.

[0113] <B. Embodiment 2>

[0114] <B-1. Structure>

[0115] The RC-IGBT 102 of Embodiment 2 is a strip-type or island-type RC-IGBT. Since the top view of the RC-IGBT 102 is the same as that of the RC-IGBTs 100 and 101 of Embodiment 1 shown in Figure 1 or Figure 2 , in this embodiment, the top views shown in Figure 1 or Figure 2 are cited as the top view of the RC-IGBT 102.

[0116] Figure 16 is the enlarged top view of the region of the RC-IGBT 102 including the IGBT region 10, the boundary region 50, and the diode region 20. Figure 16 The G-G′ line shown in Figure 1 or Figure 2 is consistent with the G-G′ line in Figure 16 . The cross-sectional structure of the IGBT region 10 along the O-O′ line in Figure 10 is the same as that shown in Figure 16 . The cross-sectional structure of the boundary region 50 along the P-P′ line in Figure 11 is the same as that shown in Figure 16 . The cross-sectional structure of the diode region 20 along the Q-Q′ line in Figure 12 is the same as that shown in

[0117] As shown in Figure 16 , in the top view of the RC-IGBT 102, the occupancy ratio of the n + -type source layer 13 formed between the active trench gates 11 in the boundary region 50 gradually decreases from the IGBT region 10 side toward the diode region 20 side.

[0118] <B-2. Effect>

[0119] In the RC-IGBT 102 of Embodiment 2, the occupancy ratio of the n + -type source layer 13 per unit area in the boundary region 50 gradually decreases from the IGBT region 10 side toward the diode region 20 side. Thus, in the boundary region 50, the injection efficiency of holes is particularly suppressed in the region close to the diode region 20. Therefore, the injection of holes from the boundary region 5 into the diode region 20 is further suppressed, and the recovery loss is further reduced.

[0120] <C. Embodiment 3>

[0121] <C-1. Structure>

[0122] The RC-IGBT 103 of Embodiment 3 is a strip-type or island-type RC-IGBT. Since the top view of the RC-IGBT 103 is the same as that of Figure 1 or Figure 2 The top views of the RC-IGBTs 100 and 101 of Embodiment 1 shown are the same. Therefore, in this embodiment, it is cited as the top view of the RC-IGBT 103 Figure 1 Or Figure 2 .

[0123] Figure 17 is an enlarged top view of the region of the RC-IGBT 103 including the IGBT region 10, the boundary region 50, and the diode region 20. Figure 17 The G-G' line shown coincides with the Figure 1 Or Figure 2 G-G' line in. Along the Figure 17 The cross-sectional structure of the IGBT region 10 along the O-O' line in is the same as that shown in Figure 10 . Along the Figure 17 The cross-sectional structure of the diode region 20 along the Q-Q' line in is the same as that shown in Figure 12 .

[0124] Figure 18 Is a cross-sectional view of the boundary region 50 along the Figure 17 P-P' line. As shown in Figure 18 , the p-type base layer 15 in the boundary region 50 of the RC-IGBT 103 surrounds the p + type contact layer 14, but is not formed over the entire boundary region 50, and is only formed in a partial region. In other words, in the boundary region 50, in at least a part of the region on the first main surface where the n + type source layer 13 or the p + type contact layer 14 is not formed, the p-type base layer 15 is not formed. In the region where the p-type base layer 15 is not formed, as shown in Figure 18 , the n - type drift layer 1 is exposed and can be in contact with the emitter electrode 6 via the barrier metal 5, or may not be in contact.

[0125] <C - 2. Effect>

[0126] In the RC-IGBT 103 of Embodiment 3, in the boundary region 50, in at least a part of the region on the first main surface where the n + type source layer 13 or the p + type contact layer 14 is not formed, the p-type base layer 15 is not formed. Thereby, the injection efficiency of holes from the boundary region 50 to the diode region 20 is further suppressed, and the recovery loss is further reduced.

[0127] <D. Embodiment 4>

[0128] <D - 1. Structure>

[0129] The RC-IGBT 104 of Embodiment 4 is a strip-shaped or island-shaped RC-IGBT. Since the top view of the RC-IGBT 104 is the same as that of the RC-IGBTs 100 and 101 of Embodiment 1 shown in Figure 1 or Figure 2 , in this embodiment, the top views shown in Figure 1 or Figure 2 are cited as the top view of the RC-IGBT 104.

[0130] Figure 19 is an enlarged top view of the region of the RC-IGBT 104 including the IGBT region 10, the boundary region 50, and the diode region 20. Figure 19 The G-G' line shown in Figure 1 or Figure 2 is consistent with the G-G' line in Figure 19 . The cross-sectional structure of the IGBT region 10 along the O-O' line in Figure 10 is the same as that shown in Figure 19 . The cross-sectional structure of the diode region 20 along the Q-Q' line in Figure 12 is the same as that shown in

[0131] Figure 20 is a cross-sectional view of the boundary region 50 along the P-P' line in Figure 19 . As shown in Figure 20 , the p-type base layer 15 in the boundary region 50 of the RC-IGBT 104 surrounds the p + -type contact layer 14, but is not formed over the entire surface of the boundary region 50, and is only formed in a partial region. Moreover, in the region of the first main surface of the semiconductor substrate where the p-type base layer 15 is not formed, a p-type anode layer 25 is formed and is in contact with the emitter electrode 6 via the barrier metal 5. In the RC-IGBT 104, the concentration of the p-type impurity in the p-type anode layer 25 is lower than the concentration of the p-type impurity in the p-type base layer 15 of the IGBT region 10.

[0132] <D - Effect>

[0133] In the RC-IGBT 104 of Embodiment 4, the p-type anode layer 25 is formed on the first main surface of the semiconductor substrate in the boundary region 50 where the p-type base layer 15 is not formed. Thereby, the breakdown voltage performance of the boundary region 50 can be maintained high. In addition, by setting the concentration of the p-type impurity in the p-type anode layer 25 to be smaller than the concentration of the p-type impurity in the p-type base layer 15, the injection efficiency of holes from the boundary region 50 into the diode region 20 can be further suppressed, and the reverse recovery loss can be further reduced.

[0134] <E. Embodiment 5>

[0135] <E-1. Structure>

[0136] The RC-IGBT 105 of Embodiment 5 is a strip-shaped or island-shaped RC-IGBT. Since the top view of the RC-IGBT 105 is the same as the top views of the RC-IGBTs 100 and 101 of Embodiment 1 shown in Figure 1 or Figure 2 , in this embodiment, the top views shown in Figure 1 or Figure 2 are cited as the top view of the RC-IGBT 105.

[0137] Figure 21 is an enlarged top view of the region of the RC-IGBT 105 including the IGBT region 10, the boundary region 50, and the diode region 20. Figure 21 The G-G' line shown in Figure 1 or Figure 2 is consistent with the G-G' line in Figure 21 . The cross-sectional structure of the IGBT region 10 along the O-O' line in Figure 10 is the same as that shown in Figure 21 . The cross-sectional structure of the diode region 20 along the Q-Q' line in Figure 12 is the same as that shown in

[0138] Figure 22 is a cross-sectional view of the boundary region 50 along the P-P' line in Figure 21 . As shown in Figure 21 , in the upper half region of the paper surface of Figure 21 of the boundary region 50 of the RC-IGBT 105, the n + -type source layer 13 is not formed, which is a region where IGBT operation is not performed. This region is called the IGBT non-operation region. In addition, in the lower half region of the paper surface of Figure 21 of the boundary region 50 of the RC-IGBT 105, the n + -type source layer 13 is formed, which is a region where IGBT operation is performed. This region is called the IGBT operation region. In other words, the boundary region 50 is divided into an IGBT operation region and an IGBT non-operation region.

[0139] Moreover, the trench gate extending in the up-down direction of the paper surface in Figure 21 is divided by the IGBT operation region and the IGBT non-operation region. The trench formed in the IGBT non-operation region is formed by Figure 21The second dummy trench gate formed in the left - right direction of the paper surface, i.e., trench gate 17, is connected to the diode trench gate 21 of the diode region 20 and functions as the dummy trench gate 12. In other words, the boundary region 50 of the RC - IGBT 105 has a trench gate 17 in the IGBT non - operating region. This trench gate 17 is formed in at least a part of the region on the first main surface where the p - type base layer 15 is not formed, and it is the second dummy trench gate that reaches the n - - type drift layer 1. Moreover, the second dummy trench gate 17 contacts at least a part of the diode trench gate 21 of the diode region 20 and multiple trench gates disposed in the IGBT non - operating region.

[0140] In addition, the trench gate formed in the IGBT non - operating region is connected to the active trench gate 11 of the IGBT region 10 through a trench gate 18 formed in the left - right direction of the paper surface and functions as the active trench gate 11. Figure 21

[0141] <E - 2. Effect>

[0142] [[ID=1३]]In the RC - IGBT 105 of Embodiment 5, the boundary region 50 is divided into an IGBT operating region where the n + - type source layer 13 is disposed for IGBT operation and an IGBT non - operating region where the n + - type source layer 13 is not disposed and IGBT operation does not occur. In the IGBT non - operating region, there is also a second dummy trench gate, i.e., trench gate 17, formed in at least a part of the region on the first main surface where the p - type base layer 15 is not formed, and this trench gate 17 reaches the n - - type drift layer 1 from the first main surface. The trench gate 17 contacts at least a part of the first dummy trench gate, i.e., the diode trench gate 21, of the diode region 20 and multiple trench gates disposed in the IGBT non - operating region. Thus, the trench gate in the IGBT non - operating region of the boundary region 50 becomes a dummy trench gate, so that an increase in the gate capacitance in the boundary region 50 can be suppressed, and the recovery loss can be reduced.

[0143] <F. Embodiment 6>

[0144] <F - 1. Structure>

[0145] The RC - IGBT 10६ of Embodiment 6 is a strip - type or island - type RC - IGBT. The RC - IGBT 10६ is only related to the arrangement of the p + - type contact layer 24 in the diode region 20 and is different from the RC - IGBTs 101 and 102 of Embodiment 1. Since the top view of the RC - IGBT 10६ is the same as Figure 1 or Figure 2The top views of the RC-IGBTs 100 and 101 of Embodiment 1 shown are the same. Therefore, in this embodiment, it is cited as the top view of the RC-IGBT 106 Figure 1 or Figure 2 .

[0146] Figure 23 is a magnified top view of the region of the RC-IGBT 106 including the IGBT region 10, the boundary region 50, and the diode region 20 Figure 23 The G-G' line shown in is consistent with the G-G' line in Figure 1 or Figure 2 . Along the O-O' line in, the cross-sectional structure of the IGBT region 10 is the same as that shown in Figure 23 . Along the P-P' line in, the cross-sectional structure of the boundary region 50 is the same as that shown in Figure 10 . Along the P-P' line in, the cross-sectional structure of the boundary region 50 is the same as that shown in Figure 23 . Along the P-P' line in, the cross-sectional structure of the boundary region 50 is the same as that shown in Figure 11

[0147] Figure 24 is a cross-sectional view of the diode region 20 along the Q-Q' line in Figure 23 . As shown in Figure 23 , the p + -type contact layer 24 of the diode region 20 is arranged avoiding the front side of the n + -type source layer 13 of the boundary region 50. Here, the front side of the n + -type source layer 13 means that the positions in the up-down direction of the paper surface of Figure 23 are the same. In other words, the p + -type contact layer 24 of the diode region 20 is arranged avoiding the diode region 20 on the line along the second direction orthogonal to the extending direction of the active trench gate 11 starting from the arrangement region of the n + -type source layer 13 of the boundary region 50

[0148] <F-2. Effect>

[0149] In the RC-IGBT 106 of Embodiment 6, the p + -type contact layer 24 of the diode region 20 is arranged avoiding the diode region 20 on the line along the second direction orthogonal to the extending direction of the active trench gate 11 starting from the arrangement region of the n + -type source layer 13 of the boundary region 50. Since the hole injection efficiency of the p + -type contact layer 24 provided adjacent to the n + -type source layer 13 is high, by setting it to the above arrangement, it is possible to suppress the part where the hole density becomes high and reduce the recovery loss

[0150] In addition, the respective embodiments can be freely combined, and the respective embodiments can be appropriately deformed and omitted​

[0151] Explanation of the label

[0152] 1n - Type drift layer, 10 IGBT region, 11 active trench gate, 11a gate trench electrode, 11b gate trench insulating film, 12 dumb trench gate, 12a dumb trench electrode, 12b dumb trench insulating film, 13n + Type source pole layer, 14p + Type 15p contact layer, 15p base layer, 16p collector layer, 16a p-type terminal collector layer, 20 diode region, 21 diode trench gate, 21a diode trench electrode, 21b diode trench insulating film, 25p anode layer, 26n + Type 30 cathode layer, 30 end region, 31p type end well layer, 40 pad region, 41 control pad, 41a current sensing pad, 41b Kelvin emitter pad, 41c gate pad, 41d, 41e temperature sensing diode pad, 50 boundary region, 100-106RC-IGBT.

Claims

1. A semiconductor device having a semiconductor substrate including a drift layer of a first conductivity type, wherein, when viewed from above, an IGBT region and a diode region are arranged to sandwich a boundary region therebetween. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface. The IGBT region and the boundary region have: A base layer of the second conductivity type is formed on the first main surface side of the drift layer; A source layer of the first conductivity type is formed on the first main surface side of the base layer; A first contact layer of a second conductivity type is formed adjacent to the source layer on the first main surface side of the base layer, and the impurity concentration of the second conductivity type is higher than that of the base layer; and A collector layer of the second conductivity type is formed on the second main surface side of the drift layer. The diode region has: A second conductivity type anode layer is formed on the first main surface side of the drift layer; and A cathode layer of the first conductivity type is formed on the second main surface side of the drift layer. When viewed from above, the occupancy rate of the source layer per unit area in the boundary region is smaller than that in the IGBT region, and the occupancy rate of the first contact layer per unit area in the boundary region is also smaller than that in the IGBT region. In the boundary region, at least a portion of the region on the first main surface where the source layer or the first contact layer is not formed, the base layer is not formed.

2. The semiconductor device according to claim 1, wherein, The diode region has a second contact layer of a second conductivity type on the first main surface side of the anode layer. This second contact layer of the second conductivity type has a higher impurity concentration compared to the anode layer. When viewed from above, the percentage of the first contact layer per unit area of ​​the boundary region is smaller than the percentage of the second contact layer per unit area of ​​the diode region.

3. The semiconductor device according to claim 1, wherein, The IGBT region, the diode region, and the boundary region further have: An interlayer insulating film formed on the first main surface of the semiconductor substrate, having contact holes exposing the first main surface; and An emitter electrode is formed on the first main surface of the semiconductor substrate, separated by the interlayer insulating film. In the boundary region, the base layer is exposed in the area of ​​the first main surface where the source layer or the first contact layer is not formed, and the exposed base layer is in electrical contact with the emitter electrode via the contact hole.

4. The semiconductor device according to claim 2, wherein, The IGBT region, the diode region, and the boundary region further have: An interlayer insulating film formed on the first main surface of the semiconductor substrate, having contact holes exposing the first main surface; and An emitter electrode is formed on the first main surface of the semiconductor substrate, separated by the interlayer insulating film. In the boundary region, the base layer is exposed in the area of ​​the first main surface where the source layer or the first contact layer is not formed, and the exposed base layer is in electrical contact with the emitter electrode via the contact hole.

5. The semiconductor device according to any one of claims 1 to 4, wherein, When viewed from above, the occupancy ratio of the source layer per unit area of ​​the boundary region gradually decreases from the IGBT region side toward the diode region side.

6. The semiconductor device according to claim 1, wherein, The concentration of the second conductivity type impurity in the anode layer is lower than the concentration of the second conductivity type impurity in the base layer.

7. The semiconductor device according to claim 6, wherein, In the boundary region, in the region on the first main surface where the source layer or the first contact layer is not formed, the base layer is formed in the region where the base layer is not formed.

8. The semiconductor device according to claim 2, wherein, The IGBT region and the boundary region have multiple trench gates that extend from the first main surface through the base layer to the drift layer, extend in a first direction, and are arranged in a second direction orthogonal to the first direction. The diode region has a plurality of first dumb trench gates that extend from the first main surface through the anode layer to the drift layer, extend in the first direction, and are arranged in the second direction.

9. The semiconductor device according to claim 8, wherein, The boundary region is divided into: The IGBT operating region, which is configured with the source layer, enables IGBT operation; and The non-operating region of the IGBT does not have the aforementioned source layer and therefore does not perform IGBT operations. The IGBT non-operating region also has a second dumb trench gate, which is formed in at least a portion of the region on the first main surface where the base layer is not formed, extending from the first main surface to the drift layer. The second dumb trench gate is in contact with the first dumb trench gate in the diode region and at least a portion of the plurality of trench gates disposed in the non-operating region of the IGBT.

10. The semiconductor device according to claim 8 or 9, wherein, The second contact layer of the diode region is disposed away from the diode region along the second direction starting from the region of the boundary region where the source layer is disposed.

11. The semiconductor device according to any one of claims 1 to 4, wherein, The width of the boundary region is greater than the thickness of the semiconductor substrate.

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