Semiconductor device

Abstract

A semiconductor device of an embodiment includes a semiconductor portion having a tip, a first region, and a second region between the first region and the tip. The semiconductor portion includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of the second conductivity type provided on the second semiconductor layer and having a higher impurity concentration of the second conductivity type than the second semiconductor layer. The semiconductor device includes a gate electrode provided in the semiconductor portion and having a side surface facing the second semiconductor layer, an insulating film provided between the side surface of the gate electrode and the semiconductor portion, and an upper electrode provided on the semiconductor portion and in contact with the third semiconductor layer and the fourth semiconductor layer. The ratio of the area of the fourth semiconductor layer to the area of the third semiconductor layer in the second region is larger than the ratio of the area of the fourth semiconductor layer to the area of the third semiconductor layer in the first region.

Description

[0001] Related applications

[0002] This application enjoys priority to Japanese Patent Application No. 2020-155203 (filed on September 16, 2020) and Japanese Patent Application No. 2021-118602 (filed on July 19, 2021). This application includes all contents of the basic applications by reference to these basic applications. Technical Field

[0003] The implementation methods mainly involve semiconductor devices. Background Technology

[0004] In vertically oriented semiconductor devices where on / off operation is controlled by a trench gate, current tends to concentrate in regions near the device's ends (including corners) due to the operation of parasitic transistors during turn-off, leading to a decrease in withstand capability. One effective method to suppress parasitic transistor operation is to provide a layer that reduces carrier extraction resistance by setting a high-concentration contact layer with the same polarity as the transistor's base layer (hereinafter defined as a carrier extraction layer). However, if the ratio of the carrier extraction region is too high, it will increase the on-resistance. Summary of the Invention

[0005] The implementation provides a semiconductor device capable of suppressing the increase in on-resistance while suppressing the operation of parasitic transistors.

[0006] According to an embodiment, a semiconductor device includes: a semiconductor portion having an end, a first region, and a second region located between the first region and the end; the semiconductor portion having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer, a third semiconductor layer of a first conductivity type disposed on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type disposed on the second semiconductor layer and having a second conductivity type impurity concentration higher than that of the second semiconductor layer; a gate electrode disposed within the semiconductor portion and having a side surface opposite to the second semiconductor layer; an insulating film disposed between the side surface of the gate electrode and the semiconductor portion; and a top electrode disposed on the semiconductor portion and in contact with the third semiconductor layer and the fourth semiconductor layer. The area ratio of the fourth semiconductor layer in the second region to the area of ​​the third semiconductor layer is greater than the area ratio of the fourth semiconductor layer in the first region to the area of ​​the third semiconductor layer.

[0007] In addition, according to an embodiment, a semiconductor device includes: an upper electrode; a lower electrode; a first semiconductor layer of a first conductivity type, provided at a tip, a first region, and a second region between the first region and the tip, and between the upper electrode and the lower electrode; a second semiconductor layer of a second conductivity type provided between the upper electrode and the first semiconductor layer; a third semiconductor layer of the first conductivity type, provided between the upper electrode and the second semiconductor layer so as to be in contact with the upper electrode, and provided with a plurality of portions in a second direction intersecting a first direction from the lower electrode toward the upper electrode; a fourth semiconductor layer of the second conductivity type, provided between the upper electrode and the second semiconductor layer so as to be in contact with the upper electrode, and provided with a plurality of portions in the second direction, and the fourth semiconductor layer is configured so that a width of the second direction in the second region is greater than a width of the second direction in the first region; a gate electrode having a side surface opposite the second semiconductor layer; and an insulating film provided between the side surface of the gate electrode and the second semiconductor layer, between the side surface of the gate electrode and the third semiconductor layer, and between the side surface of the gate electrode and the fourth semiconductor layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a schematic plan view showing one configuration example of a semiconductor device of an embodiment.

[0009] Figure 2 is a schematic cross-sectional perspective view of a semiconductor device of an embodiment.

[0010] Figure 3 is a schematic plan view showing one configuration example of a semiconductor device of an embodiment.

[0011] Figure 4 is a schematic plan view showing one configuration example of a corner portion of a semiconductor device of an embodiment.

[0012] Figure 5 is a schematic plan view showing one configuration example of a corner portion of a semiconductor device of an embodiment.

[0013] Figure 6 is a schematic cross-sectional view of a semiconductor device of an embodiment mounted on a wiring substrate.

[0014] Figure 7 is a graph showing measurement results of on-resistance and secondary breakdown resistance of a semiconductor device.

[0015] Figure 8 is a schematic plan view showing a configuration example of a first region and a second region in a semiconductor device of an embodiment. DETAILED DESCRIPTION

[0016] Embodiments will be described below with reference to the accompanying drawings. Note that the same portions in each drawing are denoted with the same reference numerals.

[0017] Figure 1 is a schematic top view that shows one example of a configuration of a semiconductor device 1.

[0018] Figure 2 is a schematic cross-sectional view of the semiconductor device 1.

[0019] The semiconductor device 1 includes a semiconductor portion 10, an upper electrode 62 provided on an upper surface of the semiconductor portion 10, and a common electrode (or lower electrode) 61 provided on a lower surface of the semiconductor portion 10.

[0020] Two directions that are orthogonal to each other in a plane parallel to the upper surface or the lower surface of the semiconductor portion 10 are referred to as an X direction and a Y direction. A direction orthogonal to the X direction and the Y direction is referred to as a Z direction.

[0021] The semiconductor device 1 is a vertical semiconductor device in which current flows in a vertical direction (Z direction) in which the upper electrode 62 and the common electrode 61 in the semiconductor portion 10 are connected. The semiconductor device 1 has a gate electrode 20 of a trench gate structure for controlling on-off operation of current.

[0022] The semiconductor device 1 includes a first transistor Q1 and a second transistor Q2 that share the common electrode 61. The first transistor Q1 and the second transistor Q2 are adjacent to each other in the X direction. The first transistor Q1 and the second transistor Q2 have the same configuration, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Figure 2 The configuration shown in the drawing is a configuration common to the first transistor Q1 and the second transistor Q2.

[0023] As shown in Figure 1 The semiconductor portion 10 includes a tip 100, a first region 101, and a second region 102 between the first region 101 and the tip 100. The tip 100 includes an outermost peripheral side surface and a corner portion of the semiconductor portion 10. The boundary between the first region 101 and the second region 102 is schematically shown by a double-dotted line. The second region 102 is formed along the tip 100. Further, the second region 102 is also provided between a first transistor region in which the first transistor Q1 is formed and a second transistor region in which the second transistor Q2 is formed. In one semiconductor device 1, the first region 101 is wider than the second region 102.

[0024] The material of the semiconductor section 10 is, for example, silicon. Alternatively, the material of the semiconductor section 10 may also be, for example, silicon carbide, gallium nitride, etc.

[0025] In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible to use the first conductivity type as p-type and the second conductivity type as n-type.

[0026] like Figure 2 As shown, the semiconductor section 10 has an n-type drain layer (or semiconductor substrate) 11, an n-type drift layer (first semiconductor layer) 12 disposed on the drain layer 11, a p-type base layer (second semiconductor layer) 13 disposed on the drift layer 12, an n-type source layer (third semiconductor layer) 14 disposed on the base layer 13, and a p-type carrier extraction layer (fourth semiconductor layer) 15 disposed on the base layer 13.

[0027] The n-type impurity concentration in drift layer 12 is lower than that in drain layer 11 and source layer 14. The p-type impurity concentration in carrier extraction layer 15 is higher than that in substrate layer 13.

[0028] A plurality of gate electrodes 20 are provided within the semiconductor section 10. The gate electrodes 20 extend along the X direction within the semiconductor section 10. An insulating film 31 is provided between the gate electrodes 20 and the semiconductor section 10. An insulating film 31 is provided between the side surface of the gate electrode 20 and the substrate layer 13. The side surface of the gate electrode 20 faces the substrate layer 13 through the insulating film 31.

[0029] The semiconductor section 10 has a mesa 70 that is interrupted by the gate electrode 20 in the Y direction and extends in the X direction. A substrate layer 13, a source layer 14, and a carrier extraction layer 15 are provided on this mesa 70. In other words, the substrate layer 13, the source layer 14, and the carrier extraction layer 15 are disposed between adjacent gate electrodes 20 in the Y direction. The source layer 14 and the carrier extraction layer 15 are alternately arranged in the X direction.

[0030] An upper electrode (source electrode) 62 is provided on the upper surface of the semiconductor section 10. The upper electrode 62 is connected to the source layer 14 and the carrier extraction layer 15. An insulating film 32 is provided between the upper electrode 62 and the gate electrode 20. A common electrode (drain electrode) 61 is provided on the lower surface of the semiconductor section 10.

[0031] The upper electrode 62 is separated into two on the semiconductor section 10. For example... Figure 1 As shown by the dashed line, a first source electrode 62a is formed in the first transistor region where the first transistor Q1 is formed, and a second source electrode 62b is formed in the second transistor region where the second transistor Q2 is formed.

[0032] Two first source pads S1 are provided on the first source electrode 62a, for example. The first source pads S1 are electrically connected to the first source electrode 62a. Two second source pads S2 are provided on the second source electrode 62b, for example. The second source pads S2 are electrically connected to the second source electrode 62b.

[0033] The common electrode 61 is not separated within the semiconductor device 1, and is provided commonly to the first transistor Ql and the second transistor Q2.

[0034] One first gate pad G1 is provided on the semiconductor portion 10 of the first transistor region, for example. One second gate pad G2 is provided on the semiconductor portion 10 of the second transistor region, for example.

[0035] Figure 3 is a schematic plan view showing the arrangement relationship of the gate electrodes 20, the gate wires 21a, 21b, the gate pads G1, G2, the source layer 14, and the carrier extraction layer 15 in the semiconductor device 1.

[0036] The plurality of gate electrodes 20 of the first transistor Ql extend in the X direction. The plurality of gate electrodes 20 of the first transistor Ql are electrically connected to the first gate wire 21a formed in a manner of surrounding the region in which the gate electrodes 20 are provided. The first gate wire 21a is electrically connected to the first gate pad G1. The first gate wire 21a is provided in the second region 102 on the side of the terminal end 100.

[0037] The plurality of gate electrodes 20 of the second transistor Q2 extend in the X direction. The plurality of gate electrodes 20 of the second transistor Q2 are electrically connected to the second gate wire 21b formed in a manner of surrounding the region in which the gate electrodes 20 are provided. The second gate wire 21b is electrically connected to the second gate pad G2. The second gate wire 21b is provided in the second region 102 on the side of the terminal end 100.

[0038] If a voltage of the threshold voltage or more is applied to the gate electrode 20, a channel is formed in the region of the base layer 13 opposite to the gate electrode 20. The gate electrodes 20 of the first transistor Ql and the gate electrodes 20 of the second transistor Q2 can be controlled independently of each other.

[0039] Figure 6 is a schematic sectional view showing the state in which the semiconductor device 1 is mounted on the wiring substrate 200.

[0040] The semiconductor device 1 is mounted on the wiring substrate 200 in a state in which the common electrode 61 faces upward. The first source pad S1, the second source pad S2, the first gate pad G1, and the second gate pad G2 of the semiconductor device 1 are joined to the conductor portion 201 of the wiring substrate 200 via a joining member (e.g., solder) 90.

[0041] The semiconductor device 1 of the embodiment can be assembled in a charge / discharge circuit, for example, and used as a switch that controls the conduction of a bidirectional current of charge / discharge. The first transistor Q1 and the second transistor Q2 share the drain portion (the drain layer 11 and the common electrode 61), and the first source electrode 62a of the first transistor Q1 and the second source electrode 62b of the second transistor Q2 are connected to terminals that are electrically independent (to which different potentials are applied), respectively. A current flows between the first transistor Q1 and the second transistor Q2 via the common electrode 61.

[0042] At the time of turn-off in which the application of a voltage above the threshold voltage to the gate electrode 20 is stopped, there is Figure 2 the case in which the parasitic transistor Tr shown in the drawing operates. The parasitic transistor Tr is an npn-type transistor in which the drift layer 12 is the collector, the source layer 14 is the emitter, and the base layer 13 is the base.

[0043] At the time of turn-off, a sharp voltage change (dv / dt) between the drain and the source occurs, the base current IB of the parasitic transistor Tr flows via the capacitance between the base layer 13 and the drift layer 12, a base-emitter voltage VBE is generated, and the parasitic transistor Tr is turned on. If the parasitic transistor Tr is turned on, a current path different from the original current path of the MOSFET controlled by the gate electrode 20 is formed, and this can become a cause of destruction.

[0044] If it is difficult to extract the holes accumulated in the base layer 13 to the upper electrode (the source electrode) 62 by the carrier extraction layer 15 at the time of turn-off, even a small base current IB can generate a base-emitter voltage VBE sufficient to turn on the parasitic transistor Tr.

[0045] To suppress the generation of the base-emitter voltage VBE that turns on the parasitic transistor Tr, one of the countermeasures can be to increase the area of the carrier extraction layer 15. However, if the area of the carrier extraction layer 15 is increased, there is a trade-off relationship in which the area of the source layer 14 becomes relatively small and the on-resistance rises.

[0046] In the semiconductor portion 10, there is also a tendency that a larger electric field is applied to a region close to the tip 100 that also includes a corner, and the current is easily concentrated, and particularly, the region close to the tip 100 is easily destroyed.

[0047] Therefore, in the present embodiment, the ratio M of the area of the carrier extraction layer 15 to the area of the source layer 14 in the second region 102 close to the tip 100 is larger than the ratio N of the area of the carrier extraction layer 15 to the area of the source layer 14 in the first region 101 inside the second region 102. The ratio M per unit area in the second region 102 is larger than the ratio N per unit area in the first region 101.

[0048] For example, Figure 3 As shown, the carrier extraction layer 15 has a first portion 51 disposed in a first region 101 and a second portion 52 disposed in a second region 102. The second portion 52 is formed near the gate wirings 21a and 21b along the gate wirings 21a and 21b. The gate wirings 21a and 21b are disposed between the second portion 52 and the end 100. Additionally, the first portion 51... Figure 3 The width along the Y direction is shown by the thick solid line. That is, the width of the first part 51 in the X direction is the width of the thick solid line.

[0049] In the first region 101, a first portion 51 extends (arranged) along the Y direction in a dashed line shape interrupted by the gate electrode 20. A second portion 52 also extends (arranged) along the Y direction in a dashed line shape interrupted by the gate electrode 20. In the second portion 52, the width in the X direction of the portion extending along the Y direction is greater than the width in the X direction of the first portion 51. In the second portion 52, the portion extending in the X direction (the direction in which the gate electrode 20 extends) is continuous rather than discontinuous. The width in the Y direction of the continuously extending portion of the second portion 52 along the X direction is greater than the width in the X direction of the first portion 51.

[0050] By making the width of the second portion 52 disposed in the second region 102 greater than the width of the first portion 51 disposed in the first region 101, holes in the base layer 13 in the second region 102 can be easily extracted to the upper electrode 62 through the carrier extraction layer 15. Therefore, during turn-off, the operation of parasitic transistors Tr, which are prone to occur in the region close to the end 100, can be suppressed, improving damage resistance. By making the width of the first portion 51 smaller than the width of the second portion 52, the ratio of the source layer 14 per unit area in the first region 101 can be relatively higher than that in the second region 102, suppressing the rise in on-resistance. The first portion 51 is disposed in the first region 101, which is wider than the second region 102 and occupies most of the channel-forming region in the semiconductor device 1.

[0051] Figure 4 This is a schematic top view showing a configuration example near the corner 110 of the semiconductor section 10.

[0052] In addition to the aforementioned first portion 51 disposed in the first region 101 and the aforementioned second portion 52 disposed in the second region 102, the carrier extraction layer 15 also has a third portion 53 disposed near the corner 110 in the second region 102 and connecting the first portion 51 and the second portion 52. A plurality of gate electrodes 20 and a plurality of third portions 53 are arranged alternately along a Y direction that intersects (e.g., is orthogonal) the X direction extending from the gate electrodes 20.

[0053] The width of the second portion 52 in the X direction and the width of the third portion 53 in the X direction are larger than the width of the first portion 51 in the X direction. The length of the region 55 in the Y direction in which the plurality of third portions 53 are arranged in the Y direction via the gate electrode 20 is longer as it is closer to the corner portion 110. The length of the region 55 in the Y direction increases stepwise as it is closer to the corner portion 110 in the X direction.

[0054] With this configuration, the operation of the parasitic transistor Tr that is likely to occur particularly in the region close to the corner portion 110 can be suppressed, and the breakdown resistance can be improved.

[0055] In addition, as shown in Figure 5 , the length of the region 55 in the Y direction arranged near the corner portion 110 can also be made the same.

[0056] Figure 7 is a graph showing the results of measurement of the on-resistance and the secondary breakdown resistance of the semiconductor device.

[0057] In the graph of Figure 7 , the white circles represent the measured values in the semiconductor device of the comparative example. The ratio of the area N of the source layer 14 to the area P of the carrier extraction layer 15 is set to N:P. In the semiconductor device of the comparative example, the ratio N:P in the second region 102 is made the same as the ratio N:P in the first region 101. In the comparative example, the measured values when the ratio N:P is 5:1, the measured values when the ratio N:P is 4:1, and the measured values when the ratio N:P is 3:1 are measured.

[0058] The measured value of the secondary breakdown resistance when the ratio N:P is 5:1 in the comparative example is set to a reference value (1.00), Figure 7 the secondary breakdown resistance on the horizontal axis of the graph of Figure 7 represents the ratio with respect to the reference value. In addition, the measured value of the on-resistance when the ratio N:P is 5:1 in the comparative example is set to a reference value (1.00),

[0059] In the comparative example, the on-resistance and the secondary breakdown resistance change in a manner along the broken line shown in Figure 7 as the ratio of the area N of the source layer 14 to the area P of the carrier extraction layer 15 increases or decreases. That is, in the comparative example, if the ratio of the area N of the source layer 14 to the area P of the carrier extraction layer 15 decreases, the secondary breakdown resistance becomes higher, but the on-resistance also becomes higher. In the comparative example, if the ratio of the area N of the source layer 14 to the area P of the carrier extraction layer 15 becomes higher, the on-resistance becomes lower, but the secondary breakdown resistance also becomes lower.

[0060] In the graph of Figure 7In the graph, the black circles indicate measured values of the on-resistance and the secondary breakdown resistance in the semiconductor device of the embodiment. The configuration of the first region 101 and the second region 102 in the semiconductor device in which the measured values are measured is indicated in Figure 8

[0061] The first transistor Q1 and the second transistor Q2 are arranged in the X direction. The first transistor Q1 is divided into three regions (the first region 101, the second region 102a on the side of the terminal 100, and the second region 102b on the side of the boundary of the first transistor Q1 and the second transistor Q2) in the X direction. The second transistor Q2 is also divided into three regions (the first region 101, the second region 102a on the side of the terminal 100, and the second region 102b on the side of the boundary of the first transistor Q1 and the second transistor Q2) in the X direction.

[0062] In each of the first transistor Q1 and the second transistor Q2, the ratio of the length a of the second region 102a in the X direction, the length b of the second region 102b in the X direction, and the length c of the first region 101 in the X direction is 1:1:7. In addition, the area of the first region 101 is 5.5 times the area of the second region 102a, and is 5.5 times the area of the second region 102b.

[0063] In the semiconductor device of the embodiment, the ratio N:P is 5:1 in the first region 101, and the ratio N:P is 2.5:1 in the second region 102a and the second region 102b. That is, in the semiconductor device of the embodiment, the ratio of the area P of the carrier extraction layer 15 to the area N of the source layer 14 is made larger in the second region 102 than in the first region 101.

[0064] According to the results of Figure 7 In the semiconductor device of the embodiment, compared with the comparative example in which the ratio N:P is made the same in the first region 101 and the second region 102, reduction of the on-resistance and improvement of the secondary breakdown resistance can be achieved at the same time.

[0065] Although several embodiments of the present application have been described, these embodiments are presented by way of example and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and modifications thereof are included in the scope, spirit of the application, and are included in the scope of the application and equivalents thereof recited in the claims.​

Claims

1. A semiconductor device comprising: A semiconductor section has an end, a first region, and a second region located between the first region and the end. The semiconductor section has: an n-type first semiconductor layer; a p-type second semiconductor layer disposed on the first semiconductor layer; an n-type third semiconductor layer disposed on the second semiconductor layer; and a p-type fourth semiconductor layer disposed on the second semiconductor layer, wherein the p-type impurity concentration is higher than that of the second semiconductor layer. In the semiconductor section, the ratio of the area of ​​the fourth semiconductor layer in the second region to the area of ​​the third semiconductor layer is greater than the ratio of the area of ​​the fourth semiconductor layer in the first region to the area of ​​the third semiconductor layer. A gate electrode is disposed within the semiconductor portion and has a side surface opposite to the second semiconductor layer; An insulating film is disposed between the side surface of the gate electrode and the semiconductor portion; as well as The upper electrode is disposed on the semiconductor portion and is connected to the third semiconductor layer and the fourth semiconductor layer. The fourth semiconductor layer has a first portion disposed in the first region, a second portion disposed in the second region, and a third portion disposed in the second region and connecting the first portion and the second portion. The width of the second part and the width of the third part are both greater than the width of the first part. The plurality of gate electrodes and the plurality of third portions are arranged alternately along a second direction intersecting the first direction extending from the gate electrodes. The length of the region in the second direction of the plurality of third portions arranged in the second direction via the gate electrode is longer in the region that is closer to the corner of the semiconductor portion.

2. The semiconductor device according to claim 1, The first region is wider than the second region.

3. The semiconductor device according to claim 1, It also features a common electrode, a first gate pad, and a second gate pad. The upper electrode has a first source electrode and a second source electrode that are separately disposed on the semiconductor portion. The first gate pad is connected to the gate electrode of the first transistor region, and the first transistor region is provided with the first source electrode. The second gate pad is connected to the gate electrode of the second transistor region, and the second transistor region is provided with the second source electrode. The common electrode is disposed on the lower surface of the semiconductor portion in both the first transistor region and the second transistor region.

4. The semiconductor device according to claim 1, The ratio of the area of ​​the third semiconductor layer to the area of ​​the fourth semiconductor layer in the first region is 5:

1. The ratio of the area of ​​the third semiconductor layer to the area of ​​the fourth semiconductor layer in the second region is 2.5:

1.

5. A semiconductor device comprising: Upper electrode; Lower electrode; A semiconductor section has an end, a first region, and a second region located between the first region and the end. The semiconductor section includes: an n-type first semiconductor layer disposed in the end, the first region, and the second region located between the first region and the end, and located between an upper electrode and a lower electrode; a p-type second semiconductor layer disposed between the upper electrode and the first semiconductor layer; an n-type third semiconductor layer disposed between the upper electrode and the second semiconductor layer in connection with the upper electrode, and having multiple layers in a second direction intersecting a first direction from the lower electrode toward the upper electrode; and a p-type fourth semiconductor layer disposed between the upper electrode and the second semiconductor layer in connection with the upper electrode, having multiple layers in the second direction, and the fourth semiconductor layer is configured such that the width of the second semiconductor layer in the second region in the second direction is greater than the width of the second semiconductor layer in the first region in the second direction. The gate electrode has a side facing the second semiconductor layer; as well as An insulating film is disposed between the side surface of the gate electrode and the second semiconductor layer, between the side surface of the gate electrode and the third semiconductor layer, and between the side surface of the gate electrode and the fourth semiconductor layer. The fourth semiconductor layer has a first portion disposed in the first region, a second portion disposed in the second region, and a third portion disposed in the second region and connecting the first portion and the second portion. The width of the second part and the width of the third part are both greater than the width of the first part. The plurality of gate electrodes and the plurality of third portions are arranged alternately along a second direction intersecting the first direction extending from the gate electrodes. The length of the region in the second direction of the plurality of third portions arranged in the second direction via the gate electrode is longer in the region that is closer to the corner of the semiconductor portion.

6. The semiconductor device according to claim 5, The first region is wider than the second region.

7. The semiconductor device according to claim 5, It also features a first gate pad and a second gate pad. The upper electrode has a first source electrode and a second source electrode that are separated from each other. The first gate pad is connected to the gate electrode of the first transistor region, and the first transistor region is provided with the first source electrode. The second gate pad is connected to the gate electrode of the second transistor region, and the second transistor region is provided with the second source electrode. The lower electrode is commonly disposed on both the first transistor region and the second transistor region.

8. The semiconductor device according to claim 5, The p-type impurity concentration of the fourth semiconductor layer is higher than that of the second semiconductor layer.

9. The semiconductor device according to claim 5, The ratio of the area of ​​the third semiconductor layer to the area of ​​the fourth semiconductor layer in the first region is 5:

1. The ratio of the area of ​​the third semiconductor layer to the area of ​​the fourth semiconductor layer in the second region is 2.5:1.

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