Semiconductor devices
By employing separate gate drivers and common drive circuits for power transistors, the problems of increased circuit size and inability to reduce costs in existing technologies are solved, achieving circuit miniaturization and performance improvement.
Patent Information
- Application Number
- CN202111132598.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-10-01
- Filing Date
- 2021-09-26
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2041-09-26
AI Technical Summary
In the prior art, the use of a common gate voltage to drive power transistors limits the increase of MOSFET gate voltage, which prevents the chip size from being reduced, hindering cost reduction and miniaturization. At the same time, it increases the number of components and circuit size, resulting in no reduction in cost and a decrease in performance.
The first and second power transistors are driven by separate gate drivers. The input signal is amplified and branched by a common driving circuit, and different gate voltages are supplied to the first and second power transistors to achieve parallel connection.
This enabled the reduction in circuit size, lowered costs, suppressed transmission delay fluctuations, and improved the quality and performance of semiconductor devices.
Smart Images
Figure CN114268303B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device for parallel driving of power transistors. Background Technology
[0002] In semiconductor devices that drive power transistors in parallel, MOSFETs (unipolar) and IGBTs (bipolar) are combined as power transistors to improve performance. However, if a common gate voltage is used to drive these power transistors, the gate voltage is limited by the short-circuit withstand capability of the IGBT, thus restricting the performance improvement that would result from increasing the gate voltage of the MOSFET. This hinders the reduction of MOSFET chip size, preventing cost reduction and miniaturization. Therefore, a semiconductor device that controls two power transistors using separate drive circuits with different power supply voltages has been proposed (see, for example, Patent Document 1).
[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-18037
[0004] However, because a separate drive circuit is required, the number of components and the circuit size increase, making it impossible to achieve an overall cost reduction. Furthermore, transmission delay fluctuations occur between the two drive circuits with different power supply voltages, leading to a decrease in quality and performance. Summary of the Invention
[0005] The present invention was proposed to solve the above-mentioned problems, and its purpose is to obtain a semiconductor device that can reduce costs and improve quality and performance.
[0006] The semiconductor device of the present invention is characterized by having: first and second power transistors connected in parallel with different saturation currents; and a gate driver that drives the first and second power transistors respectively by separate gate voltages, the gate driver having: a drive circuit that receives an input signal and outputs a drive signal; a first amplifier that amplifies the drive signal according to a first power supply voltage and supplies it to the gate of the first power transistor; and a second amplifier that amplifies the drive signal according to a second power supply voltage different from the first power supply voltage and supplies it to the gate of the second power transistor.
[0007] The effects of the invention
[0008] In this invention, the drive circuit is common to both the first and second power transistors. This reduces the circuit size and lowers costs compared to having separate drive circuits for each power transistor. Furthermore, by making the drive circuit common, the drive signal is branched just before output, thus suppressing propagation delay fluctuations.
[0009] This can improve quality and performance. Attached Figure Description
[0010] Figure 1 This is a circuit diagram illustrating the semiconductor device involved in Embodiment 1.
[0011] Figure 2 This is a circuit diagram representing the driving circuit.
[0012] Figure 3 This is a circuit diagram illustrating the semiconductor device involved in Embodiment 2.
[0013] Figure 4 This is a circuit diagram representing a power supply circuit.
[0014] Figure 5 This is a circuit diagram representing the semiconductor device involved in Embodiment 3.
[0015] Figure 6 This is a circuit diagram illustrating the semiconductor device involved in Embodiment 4. Detailed Implementation
[0016] The semiconductor device according to the embodiments will be described with reference to the accompanying drawings. The same or corresponding structural elements are labeled with the same reference numerals, and sometimes repeated descriptions are omitted.
[0017] Implementation method 1.
[0018] Figure 1 This is a circuit diagram illustrating the semiconductor device according to Embodiment 1. The first power transistor Q1 is a MOSFET, and the second power transistor Q2 is a bipolar transistor such as an IGBT. The gm characteristics and saturation current of the first and second power transistors Q1 and Q2 are different. The first and second power transistors Q1 and Q2 are connected in parallel with each other.
[0019] Gate driver 1 is an IC that drives the first and second power transistors Q1 and Q2 respectively using separate gate voltages. External power supplies 2 and 3 are located outside of gate driver 1, supplying the first and second power supply voltages VCC1 and VCC2 to gate driver 1 respectively. The second power supply voltage VCC2 is different from the first power supply voltage VCC1.
[0020] Gate driver 1 includes a drive circuit 4, a first amplifier 5, and a second amplifier 6. The drive circuit 4 takes an input signal Vin, performs level shifting and other processing, and outputs a drive signal. The drive signal output by the drive circuit 4 is branched into two, which are input to the first amplifier 5 and the second amplifier 6 respectively. The first amplifier 5 amplifies the drive signal according to the first power supply voltage VCC1 and supplies it to the gate of the first power transistor Q1. The second amplifier 6 amplifies the drive signal according to the second power supply voltage VCC2 and supplies it to the gate of the second power transistor Q2. Therefore, not only in transient operating environments but also in static operating environments, the gate voltages of the first and second power transistors Q1 and Q2 can be set to different values.
[0021] Figure 2 This is a circuit diagram representing the drive circuit. The input signal Vin is input to the input circuit 8 via the protection circuit 7. The input circuit 8 is a Schmitt comparator. The output signal of the input circuit 8 is filtered and delayed by the filter circuit-delay circuit 9, and then level-shifted by the level shift circuit 10. The stabilizing power supply circuit 19 supplies power to the input circuit 8, the filter circuit-delay circuit 9, and the level shift circuit 10. The output signal of the level shift circuit 10 is output as a drive signal via the output circuit 11 and inverters 12 and 13.
[0022] In this embodiment, the drive circuit 4 is common to both the first and second power transistors Q1 and Q2. This reduces the circuit size and lowers costs compared to having separate drive circuits for each of the first and second power transistors Q1 and Q2. Furthermore, by making the drive circuit 4 common, the drive signal is branched just before output, thus suppressing transmission delay fluctuations. This improves both quality and performance.
[0023] Furthermore, the first and second power supply voltages VCC1 and VCC2 are supplied to the first and second amplifiers 5 and 6 respectively from separate external power supplies 2 and 3. Moreover, the saturation current of the first power transistor Q1 is smaller than that of the second power transistor Q2, thus allowing the second power supply voltage VCC2 to be smaller than the first power supply voltage VCC1. Therefore, the power from the external power supply 3 is controlled to be the power required to drive the gate of the second power transistor Q2, thereby reducing the circuit size and cost of the external power supply 3.
[0024] Furthermore, the first power transistor Q1 is preferably a SiC MOSFET. SiC MOSFETs have high gate voltage characteristics, and their performance can be improved by increasing the gate voltage. Moreover, costs can be further reduced through chip miniaturization and other methods.
[0025] Implementation method 2.
[0026] Figure 3 This is a circuit diagram illustrating the semiconductor device according to Embodiment 2. In this embodiment, the gate driver 1 further includes a power supply circuit 14 that generates a second power supply voltage VCC2 based on a first power supply voltage VCC1 and supplies it to the second amplifier 6. The second power supply voltage VCC2 is lower than the first power supply voltage VCC1.
[0027] Figure 4 This is a circuit diagram showing the power supply circuit. Power supply circuit 14 is a linear regulator with transistor 15, a reference voltage source Vref, feedback resistors R1 and R2, and an error amplifier 16. Transistor 15 is a PchMOSFET, with its source connected to the input terminal Vref. IN Connection, drain and output terminal V OUT Connection. Output terminal V OUT The voltage is divided by feedback resistors R1 and R2 and input to the positive terminal of error amplifier 16. A reference voltage source Vref is input to the negative terminal of error amplifier 16. The output voltage of error amplifier 16 is supplied to the gate of transistor 15. Furthermore, transistor 15 is not limited to a MOSFET; it can also be a bipolar transistor.
[0028] In this embodiment, a second power supply voltage VCC2 is generated internally within the gate driver 1. Therefore, the external power supply can be reduced. Along with this, the number of IC pads and pins can be reduced, thus minimizing the circuit size of the gate driver 1. Furthermore, cost reductions can be achieved through the reuse of common packages.
[0029] Furthermore, the second power supply voltage VCC2 is a small amount of power required only when the gate of the second power transistor Q2 is driven. Therefore, the second power supply voltage VCC2 can be generated inside the gate driver 1 using a relatively simple power supply circuit 14, such as resistor splitting. Thus, it is possible to suppress the increase in the circuit size of the gate driver 1.
[0030] Implementation method 3.
[0031] Figure 5 This is a circuit diagram illustrating the semiconductor device according to Embodiment 3. The first and second power transistors Q1′ and Q2′ are connected in parallel and connected to the high-potential sides of the first and second power transistors Q1 and Q2. The structures of the first and second power transistors Q1′ and Q2′ are the same as those of the first and second power transistors Q1 and Q2, respectively. The gate driver 1′ is an IC that drives the first and second power transistors Q1′ and Q2′ respectively through individual gate voltages, and its structure is the same as that of the gate driver 1 in Embodiment 2. A half-bridge is formed by the power transistors Q1, Q2, Q1′, Q2′ and the gate drivers 1 and 1′.
[0032] One power supply voltage for the high-potential side gate driver 1' is supplied by a floating power supply that boosts the low-potential side power supply voltage VCC1. The other power supply voltage for the high-potential side gate driver 1' is generated in the high-voltage region of the gate driver 1'. Here, the floating power supply is a bootstrap circuit with a bootstrap capacitor 17 and a bootstrap diode 18. Alternatively, a charging method using the low-potential side power supply voltage, such as a charge pump, can also be employed. Therefore, a reduction in total cost and number of components can be achieved. Furthermore, the same effects as in Embodiments 1 and 2 can be obtained.
[0033] Implementation method 4.
[0034] Figure 6 This is a circuit diagram illustrating the semiconductor device involved in Embodiment 4. A three-phase inverter is constructed by setting three half-bridges of Embodiment 3. As a result, the same effects as Embodiments 1 to 3 can be obtained in applications for controlling three-phase inverters.
[0035] Explanation of the label
[0036] Q1 is the first power transistor, Q2 is the second power transistor, 1 is the gate driver, 4 are the driver circuits, 5 is the first amplifier, 6 is the second amplifier, and 14 are the power supply circuits.
Claims
1. A semiconductor device, characterized in that, have: The first and second power transistors are connected in parallel and have different saturation currents; as well as A gate driver, which drives the first and second power transistors respectively through separate gate voltages. The gate driver has: A drive circuit that takes an input signal as input and outputs a drive signal; A first amplifier amplifies the drive signal according to a first power supply voltage and supplies it to the gate of the first power transistor; as well as A second amplifier amplifies the drive signal based on a second power supply voltage that is different from the first power supply voltage and supplies it to the gate of the second power transistor. Both the first amplifier and the second amplifier use the same driving circuit. The drive signal output from the drive circuit is branched into two, which are respectively input to the first amplifier and the second amplifier.
2. The semiconductor device according to claim 1, characterized in that, The saturation current of the first power transistor is smaller than that of the second power transistor. The second power supply voltage is lower than the first power supply voltage.
3. The semiconductor device according to claim 1, characterized in that, The first and second power supply voltages are supplied to the first and second amplifiers respectively from separate external power supplies.
4. The semiconductor device according to claim 2, characterized in that, The first and second power supply voltages are supplied to the first and second amplifiers respectively from separate external power supplies.
5. The semiconductor device according to claim 1, characterized in that, The first power supply voltage is supplied to the first amplifier from an external power source. The second power supply voltage is lower than the first power supply voltage. The gate driver also has a power supply circuit that generates the second power supply voltage based on the first power supply voltage and supplies it to the second amplifier.
6. The semiconductor device according to claim 2, characterized in that, The first power supply voltage is supplied to the first amplifier from an external power source. The second power supply voltage is lower than the first power supply voltage. The gate driver also has a power supply circuit that generates the second power supply voltage based on the first power supply voltage and supplies it to the second amplifier.
7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The first and second power transistors and the gate driver form a half-bridge.
8. The semiconductor device according to claim 7, characterized in that, A three-phase inverter is formed by three of the aforementioned half-bridges.
9. The semiconductor device according to any one of claims 1 to 6 and 8, characterized in that, The first power transistor is a SiC MOSFET.
10. The semiconductor device according to claim 7, characterized in that, The first power transistor is a SiC MOSFET.
Citation Information
Patent Citations
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JP2020018037A
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JP2020061903A
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US20170019097A1