A method for implementing a 3-line - 1-line encoder based on a ternary memristor

Abstract

The present invention relates to a method for implementing a 3-line - 1-line encoder based on a ternary memristor. The designed 3-line - 1-line ternary encoder circuit of the present invention requires a total of four memristors, namely three input memristors M in1 , M in2 , M in3 and an output memristor M out ; three voltage sources are V, V set1 and V set2 ; two voltage-controlled switches S1 and S2. The structure of the present invention is clear and simple, and is easy to implement. This circuit model can be used for application research in many fields such as multi-valued digital logic operations, and has important significance.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and relates to a method for implementing a 3-line-to-1-line encoder based on a ternary memristor. Background Art

[0002] Classical computer architectures are based on binary logic. However, in the era of artificial intelligence, it has become difficult for traditional binary computers to efficiently imitate some complex functions of the human brain. Ternary logic has more logical levels and is expected to implement more complex functions in computers. Although the same number of binary signals is easier to process than ternary signals, ternary signals have obvious advantages in terms of information-carrying capacity. For example, a single signal line can transmit more information, the circuit complexity is lower, the number of interconnections is less, the circuit's serial-parallel operation ability is stronger, and the circuit complexity is lower, etc.

[0003] As a representative of multi-valued logic, ternary logic was first proposed by Thomas Fowler in 1840. However, due to the lack of corresponding practical ternary devices, the related research on ternary logic has been stagnant. As a multi-valued memristor, the ternary memristor can exhibit three different resistance states without using any additional devices, which are used to represent "0", "1", and "2" in ternary logic, creating favorable conditions for constructing ternary logic circuits. Further, the application of ternary memristors in digital logic circuits can also further reduce the circuit area, lower the circuit power consumption, and increase the storage density, all of which create favorable conditions for realizing ternary logic circuits.

[0004] In logic circuits, encoders mainly undertake the function of signal conversion. Most current encoder integrated chips are based on CMOS technology and are mostly binary encoders. Traditional combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and having more complex connections. Compared with binary combinational logic circuits, the design of ternary combinational logic circuits is more difficult. Therefore, introducing ternary memristors into the design of combinational logic circuits and studying encoder circuits based on ternary memristors can reduce the usage rate of components and lower the circuit complexity, which has a certain promoting effect on the further development of modern information circuits. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the present invention proposes a method for implementing a 3-line-to-1-line encoder based on a ternary memristor.

[0006] The technical solution adopted by the present invention to solve the technical problems is as follows: a 3-line-to-1-line ternary encoder circuit.

[0007] The 3-line-to-1-line ternary encoder circuit designed by the present invention requires a total of four memristors, namely three input memristors Min1 , M in2 , M in3 and an output memristor M out ; The three voltage sources are V, V set1 and V set2 ; Two voltage-controlled switches S1 and S2.

[0008] In the 3-line-1-line ternary encoder circuit described above, the positive pole of the voltage source V is connected to the positive pole of the input memristor M in1 ; The negative pole of the input memristor M in1 is connected to the positive pole of the input memristor M in2 ; The negative pole of the input memristor M in2 is connected to the positive pole of the input memristor M in3 ; The negative pole of the input memristor M in3 , the negative pole of the output memristor M out and the ground wire are connected; The positive poles of the DC voltage sources V se1 and V set2 are respectively connected to the positive pole of the output memristor M out after passing through the voltage-controlled switches S1 and S2.

[0009] The ternary logic described above is a multi-valued logic with three different logic states, namely: "0", "1" and "2". All the ternary combinational logic gate circuits designed in the present invention use the resistance value of the memristor as the logic state variable. The states of the memristors corresponding to the three values are R H , R M and R L , where R H represents the logic "0"; R M represents the logic "1"; R L represents the logic "2". The three input memristors M in1 , M in2 , M in3 can input "100", "010" and "001" according to actual needs, where the initial resistance value of the output memristor M out is R H .

[0010] The operation of the ternary encoder is driven by an excitation voltage source V, and its working process can be divided into two stages. The first stage is the initial stage, and V outputs a smaller initial voltage V Init for measuring the initial states of each memristor. The second stage is the operation stage, and in this stage, V outputs a larger operation voltage V Run for completing the logic operation.

[0011] The DC voltage sources V set1 and V set2The output voltages are v th1 and v th2 respectively, which are used to set M out to "1" and "2". S1 and S2 are voltage-controlled switches, which conduct only when the applied control voltage exceeds their threshold voltages.

[0012] The present invention designs a novel 3-line-1-line encoder circuit model based on a ternary memristor, with a clear and simple structure and easy to implement. This circuit model can be used for application research in many fields such as multi-valued digital logic operations, which is of great significance. Brief Description of the Drawings

[0013] In order to more clearly illustrate the technical solution of the present invention, the drawings required in the description of the prior art will be briefly introduced below.

[0014] Figure 1 is the 3-line-1-line encoder circuit based on the ternary memristor of the present invention. Detailed Embodiments

[0015] In order to enable those skilled in the art to better understand the solution of the present invention, the model proposed by the present invention will be further described below in conjunction with the drawings and specific embodiments.

[0016] The ternary memristor is constructed by a parallel connection method on the basis of a voltage-threshold binary memristor.

[0017] The constructed ternary memristor has voltage-threshold characteristics, and its two threshold voltages are v th1 = 1V and v th2 = 1.2V respectively. R L , R M and R H correspond to three different resistance states of the model from low to high, and their magnitudes are 100Ω, 400Ω and 800Ω respectively. When the voltage v≥1.2V, the memristor is set to R L . When 1V≤v<1.2V, if the resistance value of the memristor is R H at this time, it will quickly drop to R M , otherwise it will remain in its original state. When -1V<v<1V, the memristor will continue to maintain its original state. When -1.2V<v≤-1V, if the resistance value of the memristor is less than R M at this time, it will increase to R M , otherwise it will not change. When v≤-1.2V, the resistance value of the memristor is set to R H .

[0018] A 3-line - 1-line encoder circuit based on a ternary memristor designed by the present invention can realize the function of converting three binary signals into one ternary signal only through three input memristors, one output memristor and the corresponding number of voltage-controlled switches. The truth table of the designed 3-line - 1-line ternary encoder is shown in the following table, where X0, X1, and X2 are three input signals, and the output signal is represented by Y.

[0019]

[0020]

[0021] When the input X0 is logic "1", and X1 and X2 are logic "0", the output Y is logic "0". When the input X1 is logic "1", and X0 and X2 are logic "0", the output Y is logic "1". When the input X2 is logic "1", and X0 and X1 are logic "0", the output Y is logic "2".

[0022] The circuit structure of a 3-line - 1-line encoder based on a ternary memristor designed by the present invention is as Figure 1 shown, where M in1 , M in2 , and M in3 are all input memristors, M out is the output memristor, and the initial resistance value of M out is R H . The output voltage magnitudes of the DC voltage sources V set1 and V set2 are v th1 and v th2 respectively, which are used to perform the "set 1" and "set 2" operations on M out . S1 and S2 are voltage-controlled switches, and the switches conduct only when the applied control voltage exceeds their threshold voltages. Figure 1 The control voltage of switch S1 in in2 is the partial voltage V ba on the input memristor M in3 , and the control voltage of switch S2 is the partial voltage V cb on the input memristor M

[0023] The operation of the 3-line - 1-line encoder based on a ternary memristor is driven by an excitation voltage source V, and its working process can be divided into two stages. The first stage is the initial stage, which corresponds to 0 - 10 ms. In this stage, V outputs a relatively small initial voltage V Init, used to measure the initial state of each memristor, and measure the resistance value of the memristor by reading the voltage across the memristor and the passing current. The value of this measured voltage should be small so that the voltage division on each memristor does not exceed the set threshold voltage. The second stage is the operation stage, corresponding to 10 - 20 ms. In this stage, V will output a relatively large operating voltage V Run is used to complete logical operations. The initial voltage V Init of the ternary encoder is 0.5V, and the operating voltage V Run is 1V.

[0024] For the described 3 - wire to 1 - wire ternary encoder, the specific circuit operation stage can be discussed in the following three cases:

[0025] When the input logic is "100", that is, the input memristor M in1 = 400Ω, the input memristor M in2 = 800Ω, the input memristor M in3 = 800Ω. At this time, the voltage division V in2 on the input memristor M ba is equal to the voltage division V in3 on the input memristor M cb and is equal to -0.4V. The voltage divisions V ba and V cb of the control switches S1 and S2 are lower than their threshold voltage -0.21V. Therefore, both switches S1 and S2 are not conducting, and the output memristor maintains its initial value unchanged, that is, the logic gate outputs logic "0".

[0026] When the input logic is "010", that is, the input memristor M in1 = 800Ω, the input memristor M in2 = 400Ω, the input memristor M in3 = 800Ω. At this time, the voltage division V in2 on the input memristor M ba is -0.2V, the voltage division V in3 on the input memristor M cb is -0.4V. The voltage division V ba of the control switch S1 exceeds its threshold voltage -0.21V, and the voltage division V cb of the control switch S2 does not exceed its threshold voltage -0.21V. Therefore, the switch S1 conducts, and the switch S2 does not conduct, that is, the voltage source V set1 outputs a voltage v th1 to set the output memristor to 400Ω, and the logic gate outputs logic "1".

[0027] When the input logic is "001", that is, the input memristor M in1 = 800Ω, the input memristor M in2= 800 Ω, input memristor M in3 = 400 Ω. At this time, the voltage division V in2 across the input memristor M ba is -0.4 V, and the voltage division V in3 across the input memristor M cb is -0.2 V. The voltage division V ba across the control switch S1 does not exceed its threshold voltage of -0.21 V, and the voltage division V cb across the control switch S2 exceeds its threshold voltage of -0.21 V. Therefore, the switch S1 is not conducting, and the switch S2 is conducting, that is, the output voltage v set2 of the voltage source V th2 sets the output memristor to 100 Ω, and the logic gate outputs logic "2".

[0028] Those of ordinary skill in the art should recognize that the above embodiments are only used to verify the present invention and are not intended to limit the present invention. As long as it is within the scope of the present invention, changes and deformations of the above embodiments will fall within the protection scope of the present invention.

Claims

1. A method for implementing a 3-line to 1-line encoder based on a ternary memristor, characterized in that: The designed 3-line-1-line ternary encoder circuit requires a total of four memristors, namely three input memristors M in1 , M in2 , M in3 and an output memristor M out ; the three voltage sources are V, V set1 and V set2 ; and two voltage-controlled switches S1 and S2; In the described 3-line - 1-line ternary encoder circuit, the positive pole of the voltage source V is connected to the positive pole of the input memristor M in1 ; the negative pole of the input memristor M in1 is connected to the positive pole of the input memristor M in2 ; the negative pole of the input memristor M in2 is connected to the positive pole of the input memristor M in3 ; the negative pole of the input memristor M in3 , the negative pole of the output memristor M out and the ground wire are connected; the positive poles of the DC voltage sources V se1 and V set2 are respectively connected to the positive pole of the output memristor M out after passing through the voltage-controlled switches S1 and S2; The logic of the ternary memristor is a multi-valued logic with three different logic states, namely: "0", "1", and "2"; the designed ternary combinational logic gate circuits all use the resistance value of the memristor as the logic state variable; the states of the memristors corresponding to the three values are R H , R M , and R L , where R H represents the logic "0"; R M represents the logic "1"; R L represents the logic "2"; the three input memristors M in1 , M in2 , M in3 can input "100", "010", and "001" according to actual needs, where the initial resistance value of the output memristor M out is R H .; The operation of the ternary encoder is driven by an excitation voltage source V, and its working process can be divided into two stages; the first stage is the initial stage, where V outputs a small initial voltage V Init , which is used to measure the initial state of each memristor; the second stage is the operation stage, in which V outputs a large operation voltage V Run for performing logical operations; DC voltage source V set1 and V set2 output voltages are v th1 and v th2 respectively, used to perform the "set 1" and "set 2" operations on M out ; S1 and S2 are voltage-controlled switches that conduct only when the applied control voltage exceeds their threshold voltages.

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