Semiconductor device

Abstract

The semiconductor device (1) includes: a substrate (11) made of a semiconductor material, which is in a thin plate shape; a surface electrode (13) disposed on the surface (11ff) of the substrate (11); a back electrode (17) covering the back surface (11fr) of the substrate (11); and a via hole (1h) in the shape of a hole having the surface electrode (13) as the bottom and opening on the back surface (11fr) side, electrically connecting the surface electrode (13) and the back electrode (17), and a protruding portion (1p) protruding in the thickness direction is disposed on the peripheral portion on the back surface (11fr) side.

Description

Technical Field

[0001] The present application relates to a semiconductor device. Background Art

[0002] In a semiconductor device, as in the case of a MMIC (Monolithic Microwave Integrated Circuit), when forming an integrated circuit for high frequencies such as in the microwave band or the quasi-microwave band, the influence of parasitic inductance cannot be ignored. Therefore, the following structure is adopted: vias penetrating the semiconductor substrate are formed, and instead of allowing the wiring to loop in the plane, the electrodes formed on the surface side of the semiconductor substrate are connected to the conductors on the lower surface side to be grounded.

[0003] The semiconductor substrate constituting the above-mentioned integrated circuit for high frequencies is preferably made of a so-called wide bandgap semiconductor material such as GaAs, GaN, SiC, etc. At this time, when the semiconductor substrate is bonded (chip bonding) to the component substrate by solder, if solder having a different linear expansion coefficient from the substrate enters the via, cracks may occur due to temperature changes. Therefore, the following semiconductor device has been proposed: in order to prevent the entry of solder, the opening portion of the via is covered with a material that is not wetted by solder (for example, refer to Patent Documents 1 and 2).

[0004] Patent Document 1: Japanese Patent Laid-Open No. 4-211137 (paragraphs 0016 to 0021, FIG. 1)

[0005] Patent Document 2: Japanese Patent Laid-Open No. 10-303198 (paragraphs 0051 to 0060, Figure 5 -FIG. 6, and paragraphs 0082 to 0094, FIGS. 11 to 12)

[0006] It is considered that if the entry of solder into the via is blocked, cracks caused by the difference in linear expansion coefficient can be suppressed. On the other hand, in an actual manufacturing site, sometimes a small amount of foreign matter adheres to the bonding surface of the semiconductor substrate that is bonded to the component substrate. If chip bonding is performed in such a state, cracks may occur in the via portion due to impact. Cracks also occur when foreign matter adheres to a position away from the via, and it is difficult to remove all minute foreign matters. Therefore, the generation of cracks cannot be eliminated, and it is difficult to improve the yield. Summary of the Invention

[0007] The present application discloses a technique for solving the above-mentioned problems, and aims to obtain a semiconductor device that suppresses parasitic inductance and has high productivity.

[0008] The semiconductor device disclosed in the present application is characterized by comprising: a substrate of a semiconductor material, which is in a thin plate shape; a surface electrode disposed on one surface of the substrate; a back electrode covering the other surface of the substrate; and a via hole, which is in a hole shape with the surface electrode as the bottom and opening on the other surface side, and electrically connects the surface electrode and the back electrode. Protrusions protruding in the thickness direction are intermittently arranged along the circumferential direction at the peripheral portion on the other surface side.

[0009] According to the semiconductor device disclosed in the present application, even if foreign matter adheres, it will not be affected by impact, so a semiconductor device with high productivity can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 1C They are respectively a top view and an end view of the semiconductor device of Embodiment 1 as viewed from the back, and an end view in a state of being joined to a component substrate.

[0011] Figure 2 It is a perspective view of the semiconductor device of Embodiment 1.

[0012] Figure 3 It is an end view of the semiconductor device of the comparative example in a state of being joined to a component substrate.

[0013] Figures 4A to 4C They are respectively a top view and an end view of the semiconductor device of Embodiment 2 as viewed from the back, and an end view in a state of being joined to a component substrate.

[0014] Figure 5 It is a top view of the semiconductor device of Embodiment 3 as viewed from the back.

[0015] Figures 6A to 6C They are respectively end views of the semiconductor device of Embodiment 3 in a state of being joined to a component substrate with different cutting positions.

[0016] Figure 7 It is a top view of the semiconductor device of Embodiment 4 as viewed from the back.

[0017] Figures 8A to 8C They are respectively end views of the semiconductor device of Embodiment 4 in a state of being joined to a component substrate with different cutting positions. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Embodiment 1.

[0019] Figures 1A to 1C , Figure 2 , Figure 3 To describe the structure and effects of the semiconductor device of Embodiment 1, Figures 1A to 1CA top view of the semiconductor device when viewed from the back surface which becomes the bonding surface for bonding to the component substrate ( Figure 1A ), Figure 1A a cross-sectional view taken along line A-A of ( Figure 1B ), and a cross-sectional view corresponding to Figure 1B in the state where the semiconductor device is bonded to the component substrate ( Figure 1C ). In addition, Figure 2 is a perspective view of the semiconductor device when viewed from the surface side which is the mounting surface. Moreover, Figure 3 is a cross-sectional view showing the state where the semiconductor device of the comparative example is bonded to the component substrate and corresponds to Figure 1C .

[0020] In the semiconductor device of each embodiment of the present application, an integrated circuit or a semiconductor element in which an electronic circuit for high frequencies is formed, such as an MMIC, is formed on a base material of a semiconductor material, and a via hole for electrically connecting an electrode disposed on the surface side to a back electrode and grounding is provided. In addition, before explaining the characteristic structure of the semiconductor device of the present application, the structure of the semiconductor device having a via hole will be explained.

[0021] As Figure 2 shown, in a base material 11 made of a semiconductor material, semiconductor elements 16 such as switching elements and rectifying elements are formed, and electronic components such as an inductor 14, a capacitor 15, an antenna 18, and a resistor are disposed on the surface 11ff, for example. Wiring patterns 12, a surface electrode 13, and a via hole 1h whose inner wall is covered with a conductor electrically connected to the surface electrode and opens on the back surface 11fr ( Figures 1A to 1C ) side of the base material 11 are also formed.

[0022] The base material 11 is formed by epitaxy (epitaxial growth) on a so-called wide bandgap semiconductor material such as GaAs, GaN, SiC, or on a substrate thereof, and becomes a thin plate shape. The width W is 1 mm, the depth D is about 1 mm or more, and the thickness tb is often about 0.1 mm. The surface electrode 13 is an electrode mainly made of gold (Au), for example, and is formed by vacuum evaporation, sputtering, electroplating, or the like.

[0023] The via hole 1h is a bottomed hole that perforates the base material 11 from the lower surface side to the surface electrode 13 by dry etching or wet etching. As Figure 1A , Figure 1B shown, the inner wall is covered with a conductor connected to the back electrode 17 and is electrically connected to the surface electrode 13. The via holes 1h each have an inner diameter of about 0.05 to 0.1 mm, and the conductor portion covering the inner wall is integrally formed with the back electrode 17 having a thickness of 1 to 5 μm, and Au is used, for example.

[0024] As Figure 1CAs shown, the semiconductor device 1 of such a structure is used in a state of being connected to the component substrate 30 by means of the chip bonding member 20. As the chip bonding member 20, for example, a solder such as gold tin (AuSn), a conductive resin, etc. is used, and its thickness is 5 μm to 25 μm. As the component substrate 30, for example, copper (Cu), ceramics, resin, etc. are used.

[0025] At this time, among the electronic components mounted on the surface 11ff, the electronic component connected to the surface electrode 13 that conducts with the via 1h is grounded not via the detour path on the surface 11ff, but by being electrically connected to the back electrode 17 in the thickness direction. For example, when grounding the surface electrode of the semiconductor element 16 (mainly the source electrode in a field effect transistor and mainly the emitter electrode in a bipolar transistor), compared with grounding with a wire, since it is grounded via the via 1h, the parasitic inductance can be reduced. Thereby, the high-frequency characteristics are improved, and the area of the chip can be reduced.

[0026] In addition, in the semiconductor device 1 of each embodiment of the present application, a protruding portion 1p protruding in the thickness direction (z direction) is formed at the peripheral portion of the back surface 1fr that becomes the bonding surface with the component substrate 30, and a predetermined interval or more is provided between the component substrate 30 in the main area. The details of each embodiment will be described below.

[0027] In the semiconductor device 1 of the first embodiment, a thick film portion 17p is formed at the peripheral portion of the back electrode 17, and the thick film portion 17p has a thickness tmp thicker than the thickness tm of the main area where the via 1h etc. are arranged, thereby forming the protruding portion 1p. This structure is realized by forming the entire surface with a certain thickness tm when forming the back electrode 17, and then, for example, forming a pattern with a resist and selectively thickening only the peripheral portion of the chip to the thickness tmp.

[0028] Specifically, if the thickness tmp of the peripheral portion is made 20 μm thicker than the thickness tm of the main area of the back electrode 17, the protruding height Δt in the thickness direction (z direction) of the protruding portion 1p becomes 20 μm, and the peripheral portion protrudes 20 μm with respect to the main area. In addition, the thickness tm of the main area of the back electrode 17 is usually about 1 to 6 μm. If the thickness tm is 5 μm, if the thickness tmp of the peripheral portion is made 25 μm, the protruding height Δt is 20 μm.

[0029] On the other hand, when the semiconductor device 1 is bonded to the component substrate 30 by chip bonding, the thickness td of the chip bonding member 20 may be distributed in the range of 5 to 25 μm, but is usually in the range of 7 to 15 μm. In addition, as the foreign matter 90 attached to the back electrode 17 of the semiconductor device 1, gold particles generated during the formation of the back electrode 17 are considered. Although it varies depending on the manufacturing conditions, there remains a height (effective height) of 15 to 25 μm even when a load is applied.

[0030] Under such circumstances, a study was conducted on the case where the semiconductor device 1 of the present application and a semiconductor device without the protrusion 1p as a comparative example were respectively chip-bonded to the component substrate 30. In addition, in order to distinguish from the semiconductor device 1 of the present application, for the semiconductor device of the comparative example, as Figure 3 shown, “C” is added to the end of the reference numeral, for example, it is called the semiconductor device 1C. Moreover, the same foreign matter 90 is attached to the back surface 1fr of the semiconductor device 1 and the back surface 1frC of the semiconductor device 1C, and chip bonding is performed using the same chip bonding member 20 on the same specification component substrate 30.

[0031] In the semiconductor device 1C of the comparative example, the interval between the back surface 1frC and the component substrate 30 via the chip bonding member 20 during chip bonding, that is, the thickness tdC of the chip bonding member 20 becomes any value within the range of 7 to 15 μm. Therefore, even if the thickness tdC of the chip bonding member 20 is the maximum of 15 μm, if there is a foreign matter among the attached foreign matters 90 whose effective height exceeds 15 μm, the load will concentrate on the foreign matter 90 part during chip bonding.

[0032] At this time, even if it is away from the foreign matter 90 where the load is concentrated, the stress concentrates on the part where the via hole 1hC is formed in the base material 11C, and the possibility of generating cracks starting from the via hole 1hC becomes high. That is, when foreign matters with the above-mentioned height of 15 to 25 μm remain mixed in, cracks are likely to be generated and the yield rate is reduced unless the foreign matters are removed.

[0033] In addition, when the thickness tdC of the chip bonding member 20 is the minimum of 7 μm, if there is a foreign matter among the attached foreign matters 90 whose effective height exceeds 7 μm, cracks are generated, and it becomes increasingly difficult to suppress the generation of cracks by removing the foreign matters.

[0034] On the other hand, in the semiconductor device 1 of the first embodiment, the thickness tdp of the peripheral portion in the thickness of the chip bonding member 20 during chip bonding is the same as that of the semiconductor device 1C of the comparative example, and becomes any value within the range of 7 to 15 μm. However, the thickness td of the main region is thicker than the thickness tdp of the peripheral portion by an amount corresponding to the protrusion height Δt. Therefore, when the protrusion height Δt is 20 μm, even when the thickness tdp is the minimum of 7 μm, the thickness td of the main region becomes 27 μm.

[0035] Therefore, as Figure 1C shown, if the foreign object 90 with an effective height of 27 μm or less, it will not contact the component substrate 30 simultaneously with the back surface 1fr of the semiconductor device 1. Therefore, no load concentration occurs on the foreign object 90, and the generation of cracks can be prevented. In other words, if the foreign object 90 with an effective height exceeding 27 μm can be excluded, the generation of cracks caused by the foreign object 90 can be prevented, and the yield can be improved.

[0036] In addition, when the thickness tdp of the peripheral portion is the maximum of 15 μm, as long as the foreign object 90 has a height of 35 μm or less, the generation of cracks can be prevented, and the removal target can be narrowed down to foreign objects with an effective height of 35 μm or more. Therefore, the trouble caused by removal can be reduced, and the yield can be improved.

[0037] In addition, when the maximum effective height of the foreign object 90 is any value between 15 and 25 μm depending on the manufacturing process, if the minimum thickness tdp (7 μm) is used as a basis and the protrusion height Δt required to avoid crack generation is simply calculated, it becomes 8 to 18 μm. However, considering manufacturing deviations, the set value of the protrusion height Δt is preferably set in the range of 13 to 23 μm with a margin of 5 μm.

[0038] However, although rare, the effective height of the foreign object 90 may reach 50 μm depending on the manufacturing process. In such a case, the required amount of the chip bonding member 20 increases, but the maximum protrusion height Δt can be set to 43 μm. In addition, in practical terms, the thickness tdp of the chip bonding member 20 at the peripheral portion is also often about 10 μm. Considering these, the set value of the protrusion height Δt can also be set in the range of 10 to 40 μm.

[0039] Second Embodiment.

[0040] In the above first embodiment, an example of forming a protrusion by changing the thickness of the back electrode has been described. In the second embodiment, an example of forming a protrusion by changing only the thickness of the substrate itself will be described.

[0041] Figures 4A to 4CFIG. 0 is a diagram for explaining the structure of the semiconductor device according to Embodiment 2, and is a top view of the semiconductor device when viewed from the back surface which is the bonding surface to be bonded to the component substrate ( Figure 4A ), and is Figure 4A a cross-sectional view taken along line B-B of Figure 4B ), and is a cross-sectional view corresponding to Figure 4B in the state where the semiconductor device is bonded to the component substrate ( Figure 4C ). In the present Embodiment 2, the structure other than the structure of the protruding portion is the same as that of Embodiment 1, and the same reference numerals are assigned to the same portions. In addition, Figure 2 is directly cited.

[0042] In the semiconductor device 1 of the present Embodiment 2, as also shown in Figures 4A to 4C , a protruding portion 1p protruding in the thickness direction is formed at the peripheral portion on the back surface 1fr side. Moreover, as described in Figure 2 of Embodiment 1, there are formed: a wiring pattern 12 for electrically connecting each electronic component, a surface electrode 13, and a via hole 1h whose inner wall is covered with a conductor for electrically connecting to the surface electrode 13 and which opens on the back surface 11fr side of the base material 11.

[0043] In the semiconductor device 1 of the present Embodiment 2, at the peripheral portion on the side of the base material 11 where the back surface electrode 17 is formed, as shown in Figure 4B , a base material protruding portion 11p with a protruding height Δtb is formed and covered with a back surface electrode 17 having a certain thickness, thereby forming the protruding portion 1p.

[0044] In this structure, the base material 11 is formed into a thin plate shape in the same manner as in Embodiment 1, and further, an epitaxy is selectively formed at the peripheral portion on the side where the back surface electrode 17 is formed to form the base material protruding portion 11p with a protruding height Δtb. Moreover, after forming the surface electrode 13 and the via hole 1h by perforation, a back surface electrode 17 is formed on the entire back surface with a certain thickness tm (1 to 5 μm), thereby enabling the protruding portion 1p with a protruding height Δt (≈Δtb) to be realized.

[0045] The internal structure of the protruding portion 1p is different from that of Embodiment 1, but it can be considered to have the same external shape, as shown in Figure 4C , and is used in the state of being connected to the component substrate 30 using the chip bonding member 20. At this time, by setting the same as the setting of the protruding height Δt (in terms of manufacturing, the setting of the protruding height Δtb) described in Embodiment 1, the same operation is performed on the foreign matter 90 as in Embodiment 1, and the same effect is exerted.

[0046] Embodiment 3.

[0047] In the above-described Embodiment 1 or 2, an example is shown in which the protruding portions are formed continuously over the entire circumference of the peripheral portion. In the present Embodiment 3 and the following Embodiment 4, an example in which a plurality of protruding portions are intermittently arranged along the peripheral portion will be described.

[0048] Figure 5 and Figures 6A to 6C For explaining the structure of the semiconductor device of Embodiment 3, Figure 5 FIG. is a plan view of the semiconductor device when viewed from the back surface which is the bonding surface to be bonded to the component substrate, Figures 6A to 6C FIG. is an end view of different cut surfaces in a state where the semiconductor device is bonded to the component substrate, and is Figure 5 an end view taken along line C-C of Figure 6A ), and is Figure 5 an end view taken along line D-D of Figure 6B ), and is Figure 5 an end view taken along line E-E of Figure 6C ). In the present Embodiment 3, the configuration other than the arrangement of the protruding portions is the same as that of Embodiment 1, and the same reference numerals are given to the same portions. In addition, Figure 2 is also directly referred to.

[0049] In the semiconductor device 1 of the present Embodiment 3, as Figure 5 shown, protruding portions 1p protruding in the thickness direction are intermittently formed along the circumferential direction on the peripheral portion on the back surface 1fr side. In addition, as described in Figure 2 of Embodiment 1, wiring patterns 12, surface electrodes 13, and vias 1h whose inner walls are covered with a conductor for electrically connecting to the surface electrodes 13 and opening on the back surface 11fr side of the base material 11 are formed.

[0050] The intermittently arranged protruding portions 1p in the present Embodiment 3, as Figure 6A shown, similar to Embodiment 1, make the thickness tm of the back surface electrode 17 thicker (thickness tmp) only at necessary portions of the peripheral portion. Thus, as Figures 6A to 6C shown, protruding portions 1p having a protruding height Δt are intermittently formed along the circumferential direction in the peripheral portion.

[0051] This structure can be realized by forming the entire surface with a normal thickness tm when forming the back surface electrode 17, and then, for example, forming a pattern with a resist and selectively thickening only necessary portions in the peripheral portion of the chip to a thickness tmp.

[0052] In the semiconductor device 1 of the third embodiment, the protruding portions 1p are arranged intermittently along the peripheral portion, which is different from the first and second embodiments. However, the intermittently arranged protruding portions 1p are arranged so as to surround the main area, so that the semiconductor device 1 does not tilt with respect to the component substrate 30. Therefore, similar to the case where the protruding portions 1p are formed continuously over the entire circumference, the thickness td of the chip bonding member 20 in the main area can be controlled. That is, it can be considered that the same effect as making the thickness td thick enough not to affect the foreign matter 90 can be obtained, and the same function and effect can be exerted.

[0053] In addition, since the protruding portions 1p are arranged intermittently along the circumferential direction, as Figure 6C shown, although it is rare, when foreign matter 90 adheres to the peripheral portion, as long as there is an intermittent portion, the influence of the foreign matter 90 can be eliminated. As the configuration surrounding the main area, it is not limited to the Figure 5 example shown, and for example, it can also be scattered at the four corners or on the four sides.

[0054] Embodiment 4.

[0055] In the above-described third embodiment, an example in which the protruding portions arranged intermittently along the circumferential direction are formed by changing the thickness of the back electrode has been described. In the fourth embodiment, similar to the difference between the second embodiment and the first embodiment, an example in which the intermittent protruding portions are formed by changing the thickness of the base material itself will be described.

[0056] Figure 7 And Figure 8A ~FIGs. AC are diagrams for explaining the structure of the semiconductor device of the fourth embodiment. Figure 7 It is a top view when observing the semiconductor device from the back surface, which is the bonding surface that becomes bonded to the component substrate. Figure 8A ~FIGs. AC are end views of different cut surfaces in the state where the semiconductor device is bonded to the component substrate, and are Figure 7 the end view at the F-F line of Figure 8A ), and are Figure 7 the end view at the G-G line of Figure 8B ), and are Figure 7 the end view at the H-H line of Figure 8C ). In the fourth embodiment, the structure of the protruding portions is the same as that of the second embodiment, and the arrangement of the protruding portions is the same as that of the third embodiment. In addition, the same reference numerals are given to the same parts. In addition, 2 is also directly referred to.

[0057] In the semiconductor device 1 of the fourth embodiment, similar to the third embodiment, as Figure 7 shown, a plurality of protruding portions are arranged intermittently along the peripheral portion on the back surface 1fr side. In addition, similar to the second embodiment, as Figures 8A to 8CAs shown, a discontinuous substrate protrusion 11p is formed along the peripheral portion of the side of the substrate 11 where the back electrode 17 is formed, and a plurality of protrusions 1p covered by the back electrode 17 having the same thickness tm as the main region are formed.

[0058] Moreover, as described in Embodiment 1 Figure 2 a wiring pattern 12, a surface electrode 13, and a via 1h whose inner wall is covered by a conductor for electrically connecting to the surface electrode 13 and opening on the back 11fr side of the substrate 11 are formed.

[0059] In this structure, similar to Embodiment 2, the substrate 11 is formed into a thin plate shape, and further, an epitaxy is formed at intermittently selected portions on the peripheral portion of the side where the back electrode 17 is formed to form the substrate protrusion 11p with a protrusion height Δtb. Moreover, after forming the surface electrode 13 and the via 1h, the back electrode 17 is formed with a certain thickness tm (1 to 5 μm) over the entire back surface, thereby enabling the discontinuous protrusions 1p with a protrusion height Δt (≈Δtb) to be realized.

[0060] Although the internal structure of the protrusion 1p is different from that of Embodiment 3, it can be considered to have the same external shape and is used in a state where it is connected to the component substrate 30 using the chip bonding member 20. At this time, by setting the protrusion height Δt (in terms of manufacturing, the protrusion height Δtb) to be the same as that described in Embodiment 1, the same operation as that described in Embodiment 1 is achieved for the foreign matter 90, and the same effect is exerted. In addition, the effect of the discontinuous arrangement described in Embodiment 3 is also exerted.

[0061] In addition, this application describes various exemplary embodiments and examples, but the various features, modes, and functions described in one or more embodiments are not limited to the application of a specific embodiment and can also be applied alone or in various combinations to the embodiments. Therefore, within the technical scope disclosed in this application specification, countless deformation examples that are not illustrated can be envisioned. For example, it includes cases where at least one component is deformed, added, or omitted, and also includes cases where at least one component is extracted and combined with the structural elements of other embodiments.

[0062] For example, the protrusion 1p may be a combination of the substrate protrusion 11p and the thick film portion 17p, or may be composed of other materials that are not related to conductivity. In addition, in the above-mentioned embodiments, as the preferred material of the substrate 11, examples of using GaAs, GaN, and SiC as wide-bandgap semiconductor materials are shown, but this is not limited to this, and other semiconductor materials may also be used. In addition, an example of constituting MMIC is shown, but this is not limited to this, and as long as it is a thin plate-shaped semiconductor device with a via 1h, it may also be a single transistor.

[0063] Further, an example is shown in which the conductive member covering the inner wall of the via hole 1h is formed integrally with the back electrode 17, but it is not limited to this. It can also be formed by the same material or a different material. As long as the surface electrode 13 and the back electrode 17 are connected, it is not necessary to cover the entire inner wall. In addition, the material for the surface electrode 13 and the back electrode 17 is not limited to gold, and other materials can be used. In addition, for the chip bonding material 20, as long as the material can control the thickness range, it can be adjusted according to its characteristics by adjusting the protrusion height Δt.

[0064] As described above, according to the semiconductor device 1 of each embodiment, there is provided: a substrate 11 of semiconductor material in a thin plate shape; a surface electrode 13 arranged on one surface (surface 11ff) of the substrate 11; a back electrode 17 covering the other surface (back surface 11fr) of the substrate 11; and a via hole 1h in a hole shape with the surface electrode 13 as a bottom and opening on the other surface (11fr) side, and the surface electrode 13 and the back electrode 17 are electrically connected by a conductive material extending in the thickness direction on the inner wall, and a protrusion 1p protruding in the thickness direction (z direction) is arranged on the peripheral portion of the other surface (back surface 11fr) side, so that cracks can be suppressed from being generated in the via hole 1h portion due to the impact when a load is applied to the attached foreign matter 90. That is, a semiconductor device with high productivity can be obtained while achieving both suppression of parasitic inductance and prevention of cracks during manufacturing.

[0065] At this time, if the protrusion 1p is continuous over the entire circumference, the parallelism between the back surface 1fr of the semiconductor device 1 and the module substrate 30 is maintained, and the interval (thickness td) required to prevent the influence of foreign matter 90 can be maintained over the entire surface of the main area.

[0066] Alternatively, if the protrusions 1p are intermittently arranged along the circumferential direction, the influence of the foreign matter 90 adhering to the peripheral edge can be reduced.

[0067] If the protrusion 1 p is formed by the thick film portion 17 p provided on the back surface electrode 17 , the protrusion height Δt can be easily controlled by a simple combination of masking and plating.

[0068] If the protruding portion 1p is formed by a substrate protruding portion 11p provided on the substrate 11, the protruding portion 1p can be formed without increasing the use of precious metals such as gold used for the electrodes.

[0069] If the protruding height Δt of the protruding portion 1p is 10 μm or more and 40 μm or less, in practical terms, the influence on the foreign matter 90 can be suppressed regardless of the manufacturing process conditions.

[0070] In addition, as the protruding height Δt, if it is set to 13 μm or more and 23 μm or less, considering both the trouble caused by forming the protruding portion 1p, the trouble of materials, etc., and the reduction in the yield due to cracks, a semiconductor device with high productivity can be obtained.

[0071] In the case of the semiconductor device 1 used for forming a monolithic microwave integrated circuit, the influence of parasitic inductance is particularly large, the number of vias 1h used as a countermeasure increases, and the necessity of preventing cracks becomes higher.

[0072] In addition, when any one of GaAs, GaN, and SiC is used as the semiconductor material, compared with ordinary silicon, it has a high hardness and a high heat-resistant temperature. Correspondingly, there is a tendency for the temperature during chip bonding to also become higher. Therefore, the possibility of stress concentration on the via 1h when the foreign matter 90 is attached becomes higher, and the effect of preventing cracks becomes higher.

[0073] Description of Reference Numerals

[0074] 1... Semiconductor device; 1fr... Back surface; 1h... Via; 1p... Protruding portion; 11... Substrate; 11ff... Front surface (one side); 11fr... Back surface (the other side); 11p... Substrate protruding portion; 13... Front surface electrode; 17... Back surface electrode; 17p... Thick film portion; 20... Chip bonding member; 30... Component substrate; 90... Foreign matter; Δt... Protruding height.

Claims

1. A semiconductor device, characterized in that, comprising: a base material of semiconductor material, which is in the shape of a thin plate; a surface electrode disposed on one surface of the base material; a back electrode covering the other surface of the base material; and a via hole, which is in the shape of a hole having the surface electrode as the bottom and opening on the other surface side, and electrically connects the surface electrode and the back electrode, protrusions protruding in the thickness direction are intermittently arranged along the circumferential direction at the peripheral portion on the other surface side, in a state where the semiconductor device is connected to a component substrate by a chip bonding member, the protrusions have a gap with the component substrate.

2. The semiconductor device according to claim 1, characterized in that, the protrusions are formed by base material protrusions provided on the base material.

3. The semiconductor device according to claim 1 or 2, characterized in that, a monolithic microwave integrated circuit is formed.

4. The semiconductor device according to claim 1 or 2, characterized in that, any one of GaAs, GaN, and SiC is used as the semiconductor material.

5. A semiconductor device, characterized in that, comprising: a base material of semiconductor material, which is in the shape of a thin plate; a surface electrode disposed on one surface of the base material; a back electrode covering the other surface of the base material; and a via hole, which is in the shape of a hole having the surface electrode as the bottom and opening on the other surface side, and electrically connects the surface electrode and the back electrode, protrusions are disposed at the peripheral portion on the other surface side, and the protrusions are formed by thick film portions provided on the back electrode and protrude in the thickness direction, in a state where the semiconductor device is connected to a component substrate by a chip bonding member, the protrusions have a gap with the component substrate.

6. The semiconductor device according to claim 5, characterized in that, the protrusions are continuous over the entire circumference.

7. The semiconductor device according to claim 5 or 6, characterized in that, a monolithic microwave integrated circuit is formed.

8. The semiconductor device according to claim 5 or 6, characterized in that, any one of GaAs, GaN, and SiC is used as the semiconductor material.

9. A semiconductor device, characterized in that, comprising: a base material of semiconductor material, which is in the shape of a thin plate; a surface electrode disposed on one surface of the base material; a back electrode covering the other surface of the base material; and a via hole, which is in the shape of a hole having the surface electrode as the bottom and opening on the other surface side, and electrically connects the surface electrode and the back electrode, protrusions protruding in the thickness direction are disposed at the peripheral portion on the other surface side, the protruding height of the protrusions is 10 μm or more and 40 μm or less, in a state where the semiconductor device is connected to a component substrate by a chip bonding member, the protrusions have a gap with the component substrate.

10. The semiconductor device according to claim 9, characterized in that, the protruding height is 13 μm or more and 23 μm or less.

11. The semiconductor device according to claim 9 or 10, characterized in that, The protrusion is continuous and extends throughout the entire circumference.

12. The semiconductor device according to claim 9 or 10, wherein, the protrusion is formed by a substrate protrusion provided on the substrate.

13. The semiconductor device according to claim 9 or 10, wherein, a monolithic microwave integrated circuit is formed.

14. The semiconductor device according to claim 9 or 10, wherein, any one of GaAs, GaN, and SiC is used as the semiconductor material.

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