Multilayer bottom electrode with MTJ device

Abstract

A multilayer bottom electrode for a device including a magnetic tunnel junction (MTJ) is provided. The multilayer bottom electrode comprises, from bottom to top, a base segment having a first diameter and consisting of the remaining portion of a first bottom electrode-containing metal layer, a middle segment having a second diameter and consisting of the remaining portion of a second bottom electrode-containing metal layer, and an upper segment having a third diameter and consisting of the remaining portion of a third bottom electrode-containing metal layer. The first diameter is greater than the second diameter, and the third diameter is equal to or less than the second diameter. The wider base segment of each multilayer bottom electrode prevents tilting and / or bending of the resulting bottom electrode, thereby providing a stable bottom electrode.

Description

Technical Field

[0001] The present application relates to a memory structure and a method for forming the same. More particularly, the present application relates to a magnetoresistive random access memory (MRAM) structure having a stable multilayer bottom electrode. In some embodiments, the stable multilayer bottom electrode has a high aspect ratio. Background Art

[0002] MRAM is a nonvolatile random access memory technology in which data is stored by magnetic storage elements. These elements are typically formed from two ferromagnetic plates, each capable of maintaining a magnetization, separated by a thin dielectric layer (i.e., a tunnel barrier). One of the plates is a permanent magnet set to a specific polarity (i.e., the magnetic reference layer); the other plate's magnetization can be changed to match that of an external field to store memory (i.e., the magnetic free layer). This configuration is known as a magnetic tunnel junction (MTJ) pillar. In leading-edge or neuromorphic computing systems, the MTJ pillar is typically embedded within the back-end-of-line (BEOL) structure.

[0003] In the fabrication of an MRAM device, a capping layer of MTJ pillar material (i.e., magnetic reference material, tunnel barrier, non-magnetic material, and MTJ cap material) and a top electrode material are formed on the bottom electrode of the MRAM device. The capping layer is then patterned by photolithography and etching to provide a material stack of a multilayer MTJ pillar (including the magnetic reference material, tunnel barrier, non-magnetic material, and the remaining portion of the MTJ cap material) and a top electrode located on the bottom electrode.

[0004] A small bottom electrode is key to producing an MTJ post without sidewall residue. Ideally, the bottom electrode is well aligned with the MTJ post and is smaller than the MTJ post so that the bottom electrode is completely underneath the MTJ post. The bottom electrode also needs to have a considerable height so that there is sufficient dielectric thickness to allow over-etching of the MTJ material stack and cleaning of the MTJ post sidewalls without reaching the underlying metal layers. For significantly scaled MTJ posts, this results in a high aspect ratio bottom electrode feature (i.e., a height-to-diameter ratio greater than 2 to 1). As the critical dimension (CD) approaches 20 nm, the stability of the MTJ post is compromised and tilting and / or bending of the bottom electrode is observed.

[0005] It would be desirable to provide a bottom electrode for use in an MRAM device including an MTJ pillar, wherein the bottom electrode is stable (ie, little or no tilting and / or bowing is observed). Summary of the Invention

[0006] A multilayer bottom electrode for a device including a magnetic tunnel junction (MTJ) is provided. The multilayer bottom electrode includes a base segment having a first diameter and composed of a first conductive material, a middle segment having a second diameter and composed of a second conductive material having a different composition than the first conductive material, and an upper segment having a third diameter and composed of a third conductive material having a different composition than the second conductive material. The first diameter is greater than the second diameter, and the third diameter is equal to or less than the second diameter. The wider base segment of each multilayer bottom electrode prevents tilting and / or bending of the resulting bottom electrode. Thus, a stable bottom electrode is provided.

[0007] In one aspect of the present application, a memory structure is provided. In one embodiment, the memory structure includes a multilayer bottom electrode on a surface of a conductive structure embedded in a first interconnected dielectric material layer, wherein the multilayer bottom electrode includes a tapered base segment having a first diameter and composed of a first conductive material, a middle segment having a second diameter and composed of a second conductive material having a different composition than the first conductive material, and an upper segment having a third diameter and composed of a third conductive material having a different composition than the second conductive material, wherein the first diameter is greater than the second diameter and the third diameter is equal to or less than the second diameter. The second interconnected dielectric material layer is located at a position laterally adjacent to the multilayer bottom electrode. A magnetic tunnel junction (MTJ) pillar is located on the highest surface of the upper segment of the multilayer bottom electrode, and a top electrode is located on the MTJ pillar.

[0008] In another embodiment, a memory structure includes a multilayer bottom electrode located on a surface of a conductive structure embedded in a first interconnect dielectric material layer, wherein the multilayer bottom electrode includes: a base segment having a first diameter and composed of a first conductive material, a middle segment having a second diameter and composed of a second conductive material having a different composition than the first conductive material, and an upper segment having a third diameter and composed of a third conductive material having a different composition than both the first and second conductive materials, wherein the first diameter is greater than the second diameter and the third diameter is smaller than both the first and second diameters. The second interconnect dielectric material layer is located laterally adjacent to the multilayer bottom electrode. A magnetic tunnel junction (MTJ) pillar is located on a topmost surface of the upper segment of the multilayer bottom electrode, and a top electrode is located on the MTJ pillar.

[0009] In another aspect of the present application, a method for forming a memory structure is provided. In one embodiment, the method includes forming a structure comprising: an interconnect layer comprising a conductive structure embedded in a first interconnect dielectric material layer, a first bottom electrode-containing metal layer located on the interconnect layer, a second bottom electrode-containing metal layer located on the first bottom electrode-containing metal layer, a third bottom electrode-containing metal layer located on the second bottom electrode-containing metal layer, wherein the second bottom electrode-containing metal layer is composed of a conductive material having a different etch rate than the conductive materials of the first and third bottom electrode-containing metal layers, and a dielectric hard mask layer located on the third bottom electrode-containing metal layer. Next, the dielectric hard mask layer and the third bottom electrode-containing metal layer are patterned using a first etch and a patterned mask as an etch mask to provide a first patterned material stack, the first patterned material stack including a dielectric hard mask material portion and a third bottom electrode-containing metal portion. Subsequently, the dielectric hard mask layer and the third bottom electrode-containing metal layer are patterned using the first etch and the patterned mask as an etch mask to provide a first patterned material stack, the first patterned material stack including a dielectric hard mask material portion and a third bottom electrode-containing metal portion. Next, a second etch is performed to provide a multi-layer bottom electrode, wherein the multi-layer bottom electrode includes, from bottom to top, a tapered base segment having a first diameter and consisting of a remaining portion of the first bottom electrode-containing metal layer, a middle segment having a second diameter and consisting of a remaining portion of the second bottom electrode-containing metal layer, and an upper segment having a third diameter and consisting of a remaining portion of the third bottom electrode-containing metal layer, wherein the first diameter is greater than the second diameter and the third diameter is equal to or smaller than the second diameter.

[0010] In another embodiment, the method includes forming a structure comprising: an interconnect layer including a conductive structure embedded in a first interconnect dielectric material layer; a first bottom electrode-containing metal layer located on the interconnect layer; a second bottom electrode-containing metal layer located on the first bottom electrode-containing metal layer, wherein the second bottom electrode-containing metal layer has a higher lateral trim rate than the first bottom electrode-containing metal layer; a third bottom electrode-containing metal layer located on the second bottom electrode-containing metal layer, wherein the third bottom electrode-containing metal layer has a higher lateral trim rate than the second bottom electrode-containing metal layer; and a dielectric hard mask layer located on the third bottom electrode-containing metal layer. A patterned mask is then formed on the dielectric hard mask layer, wherein the patterned mask is located above the conductive structure embedded in the first interconnect dielectric material layer. Next, a pattern provided by the patterned mask is transferred into the dielectric hard mask layer to provide a dielectric hard mask beneath the patterned mask. Then, each of the first bottom electrode-containing metal layer, the second bottom electrode-containing metal layer, and the third bottom electrode-containing metal layer is patterned using the patterned hard mask as an etching mask to provide a multi-layer bottom electrode, wherein the multi-layer bottom electrode includes, from bottom to top, a base segment having a first diameter and consisting of a remaining portion of the first bottom electrode-containing metal layer, a middle segment having a second diameter and consisting of a remaining portion of the second bottom electrode-containing metal layer, and an upper segment having a third diameter and consisting of a remaining portion of the third bottom electrode-containing metal layer, wherein the first diameter is greater than the second diameter, and the third diameter is smaller than the first diameter and the second diameter.

[0011] In any of the above method embodiments, a second interconnect dielectric material layer may be formed laterally adjacent to the multi-layer bottom electrode, and another patterned material stack may be formed on the second interconnect dielectric material layer, wherein the other patterned material stack contacts the highest surface of the upper segment of the bottom electrode and includes a magnetic tunnel junction (MTJ) pillar and a top electrode. In some embodiments, a packaging pad and a third interconnect dielectric material layer are formed laterally adjacent to the second patterned material stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view of an exemplary structure that may be employed according to embodiments of the present application, wherein the exemplary structure includes a first bottom electrode-containing metal layer located on a surface of an interconnect level, the interconnect level including conductive structures embedded in a first interconnect dielectric material layer.

[0013] Figure 2 yes Figure 1 A cross-sectional view of an exemplary structure after forming a second bottom electrode-containing metal layer on the first bottom electrode-containing metal layer.

[0014] Figure 3 yes Figure 2A cross-sectional view of the exemplary structure of FIG. 1 after forming a third bottom electrode-containing metal layer on the second bottom electrode-containing metal layer.

[0015] Figure 4 yes Figure 3 A cross-sectional view of the exemplary structure after forming a dielectric hard mask layer on the third bottom electrode-containing metal layer.

[0016] Figure 5 yes Figure 4 A cross-sectional view of the exemplary structure after forming a plurality of patterned masks on the dielectric hard mask layer, wherein each patterned mask is located over one of the conductive structures embedded in the first interconnect dielectric material layer.

[0017] Figure 6 is a cross-sectional view of the exemplary structure after patterning the dielectric hard mask layer and the third bottom electrode-containing metal layer using a first etch and a patterned mask as an etch mask to provide a plurality of first patterned material stacks, each first patterned material stack including a dielectric hard mask material portion and a third bottom electrode-containing metal portion.

[0018] Figure 7 yes Figure 6 A cross-sectional view of an exemplary structure after performing a second etch to provide a plurality of multi-layer bottom electrodes, wherein each multi-layer bottom electrode comprises, from bottom to top: a tapered base segment having a first diameter and consisting of a remaining portion of a first bottom electrode-containing metal layer, a middle segment having a second diameter and consisting of a remaining portion of a second bottom electrode-containing metal layer, and an upper segment having a third diameter and consisting of a remaining portion of a third bottom electrode-containing metal layer, wherein the first diameter is greater than the second diameter and the third diameter is equal to or less than the second diameter.

[0019] Figure 8 yes Figure 7 A cross-sectional view of an exemplary structure after forming a second interconnect dielectric material layer laterally adjacent to each multi-layer bottom electrode and forming a plurality of second patterned material stacks on the second interconnect dielectric material layer, wherein each second patterned material stack contacts a highest surface of an upper segment of one of the underlying bottom electrodes and includes a magnetic tunnel junction (MTJ) pillar and a top electrode.

[0020] Figure 9 yes Figure 8 A cross-sectional view of the exemplary structure after forming an encapsulation liner and a third interconnect dielectric material layer laterally adjacent to each second patterned material stack.

[0021] Figure 10is a cross-sectional view of an exemplary structure that may be employed according to another embodiment of the present application, wherein the exemplary structure includes a first bottom electrode-containing metal layer located on a surface of an interconnect layer, the interconnect layer including a conductive structure embedded in a first interconnect dielectric material layer.

[0022] Figure 11 yes Figure 10 A cross-sectional view of an exemplary structure after forming a second bottom electrode containing metal layer on the first bottom electrode containing metal layer, wherein the second bottom electrode containing metal layer has a higher lateral trim rate than the first bottom electrode containing metal layer.

[0023] Figure 12 yes Figure 11 A cross-sectional view of the exemplary structure after forming a third bottom electrode containing metal layer on the second bottom electrode containing metal layer, wherein the third bottom electrode containing metal layer has a higher lateral trim rate than the second bottom electrode containing metal layer.

[0024] Figure 13 yes Figure 12 A cross-sectional view of the exemplary structure after forming a dielectric hard mask layer on the third bottom electrode-containing metal layer and after forming a plurality of patterned masks on the dielectric hard mask layer, wherein each patterned mask is located over one of the conductive structures embedded in the first interconnect dielectric material layer.

[0025] Figure 14 yes Figure 13 A cross-sectional view of the exemplary structure after transferring the pattern provided by each patterned mask into the dielectric hard mask layer to provide a plurality of dielectric hard masks beneath each patterned mask.

[0026] Figure 15 yes Figure 14 A cross-sectional view of an exemplary structure after etching using each patterned hard mask as an etch mask to provide a plurality of multi-layer bottom electrodes, wherein each multi-layer bottom electrode includes, from bottom to top: a base segment having a first diameter and consisting of a remaining portion of the first bottom electrode-containing metal layer, a middle segment having a second diameter and consisting of a remaining portion of the second bottom electrode-containing metal layer, and an upper segment having a third diameter and consisting of a remaining portion of the third bottom electrode-containing metal layer, wherein the first diameter is greater than the second diameter and the third diameter is smaller than the first diameter and the second diameter.

[0027] Figure 16 yes Figure 15A cross-sectional view of an exemplary structure after forming a second interconnect dielectric material layer laterally adjacent to each multi-layer bottom electrode and forming a plurality of patterned material stacks on the second interconnect dielectric material layer, wherein each patterned material stack contacts a highest surface of an upper segment of one of the underlying bottom electrodes and includes a magnetic tunnel junction (MTJ) pillar and a top electrode.

[0028] Figure 17 yes Figure 16 Cross-sectional view of the exemplary structure after forming an encapsulation liner and a third interconnect dielectric material layer laterally adjacent to each patterned material stack. DETAILED DESCRIPTION

[0029] The present application will now be described in more detail with reference to the following discussion and the accompanying drawings. It should be noted that the drawings in this application are provided for illustrative purposes only and, therefore, are not drawn to scale. It should also be noted that identical and corresponding elements are designated by identical reference numerals.

[0030] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques, are set forth in order to provide an understanding of the various embodiments of the present application. However, those skilled in the art will appreciate that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0031] It will be understood that when an element as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. Conversely, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “under” or “beneath” another element, it can be directly beneath or beneath the other element or there may be intervening elements present. Conversely, when an element is referred to as being “directly beneath” or “directly beneath” another element, there are no intervening elements present.

[0032] Note that the figures of this application illustrate memory device regions where memory structures, such as MRAM, are to be formed. Non-memory device regions may be positioned laterally adjacent to the memory device regions shown in the figures of this application. It should also be noted that although this application describes and illustrates forming multiple bottom electrodes for a memory array, this application contemplates embodiments in which a single bottom electrode is formed for a single memory structure.

[0033] First reference Figure 1 , showing an exemplary structure that can be adopted according to an embodiment of the present application. Figure 1The exemplary structure includes an interconnect layer L n The first bottom electrode-containing metal layer 14L, the interconnection layer L n A conductive structure 12 is included that is embedded in a first interconnect dielectric material layer 10 .

[0034] Although not shown in the drawings, a metal layer may be located at the interconnection layer L n In some embodiments, when n is 1, the metal layer is a middle of line (MOL) layer. In other embodiments, when n is 2, 3, 4, etc., the metal layer is located in the interconnect layer L n In any embodiment, the metal layer comprises a dielectric material layer having at least one metal layer conductive structure embedded therein, the metal layer conductive structure being directly or indirectly connected to an underlying CMOS device (not shown) present in a front end of line (FEOL) layer (also not shown).

[0035] When n is 1, the metal layer dielectric material layer can be composed of a MOL dielectric material such as silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term "low-k" refers to a dielectric material having a dielectric constant of less than 4.0 (all dielectric constants expressed herein are measured in a vacuum). Moreover, in such an embodiment (i.e., when n is 1), the at least one metal layer conductive structure is a contact structure comprising a contact metal or a contact metal alloy such as, for example, tungsten (W), cobalt (Co), platinum (Pt), nickel (Ni), or alloys thereof.

[0036] When n is greater than 1, the dielectric material layer of the metal layer can be composed of, for example, silicon dioxide, silsesquioxane, C-doped oxides (i.e., organosilicates) comprising Si, C, O, and H atoms, thermosetting polyarylene ethers, or multilayer interconnected dielectric materials thereof. The term "polyarylene" is used herein to refer to aryl moieties or inert substituted aryl moieties connected together by bonds, fused rings, or inert linking groups (e.g., such as oxygen, sulfur, sulfone, sulfoxide, carbonyl, and the like). Furthermore, in such embodiments (i.e., when n is greater than 1), the at least one metal layer conductive structure is composed of a conductive metal or a conductive metal alloy. Examples of conductive materials that can be used in the present application include copper (Cu), aluminum (Al), or tungsten (W), and an example of a conductive metal alloy is a Cu-Al alloy.

[0037] Interconnect layer L nThe first interconnect dielectric material layer 10 may be formed of one of the above-mentioned interconnect dielectric materials used for the metal layer dielectric material layer. The conductive structure 12 embedded in the first interconnect dielectric material layer 10 may be formed of one of the above-mentioned conductive metals or metal alloys used for at least one metal layer conductive structure.

[0038] In some embodiments, a diffusion barrier liner (not shown) is formed along the sidewalls and bottom wall of the conductive structure 12. In some embodiments and as Figure 1 As shown, there is no diffusion barrier liner. The diffusion barrier liner is composed of a diffusion barrier material (i.e., a material that acts as a barrier layer to prevent the diffusion of conductive materials such as copper). Examples of diffusion barrier materials that can be used to provide a diffusion barrier liner include, but are not limited to, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, the diffusion barrier material can include a material stack of diffusion barrier materials. In one example, the diffusion barrier material can be composed of a stack of Ta / TaN.

[0039] The metal layer and the interconnect layer L can be formed using conventional processes well known to those skilled in the art. n In order not to obscure the method of the present application, the method for forming the metal layer and the interconnect layer L is not provided herein. n In one embodiment, the metal layer and the interconnect layer L can be formed by a damascene process. n The damascene process may include forming openings in the dielectric material, filling the openings with a contact metal-containing material or a conductive metal-containing material, and, if necessary, performing a planarization process such as chemical mechanical polishing (CMP) and / or grinding. In some embodiments, each conductive structure 12 has a top surface that is coplanar with a top surface of the first interconnect dielectric material layer 10.

[0040] In forming the interconnection layer L n Afterwards, at the interconnect layer L n The first bottom electrode-containing metal layer 14L is formed on the entire interconnection layer L. n The continuous layer above. Figure 1 As shown, a first bottom electrode-containing metal layer 14L is formed on the first interconnect dielectric material layer 10 and on each conductive structure 12 .

[0041] The first bottom electrode-containing metal layer 14L is composed of a first conductive material including, but not limited to, Al, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, or WN. The first bottom electrode-containing metal layer 14L has a first thickness that can be 10 nm to 100 nm. In one example, the first bottom electrode-containing metal layer 14L is composed of one of TaN, TiN, or W and has a first thickness of 20 nm to 30 nm. The first bottom electrode-containing metal layer 14L can be formed by a deposition process such as, for example, sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0042] Now refer to Figure 2 , showing the second bottom electrode-containing metal layer 16L after forming the second bottom electrode-containing metal layer 16L on the first bottom electrode-containing metal layer 14L Figure 1 An exemplary structure of Figure 2 As shown, the second bottom electrode containing metal layer 16L is a continuous layer formed over the entire first bottom electrode containing metal layer 14L.

[0043] The second bottom electrode-containing metal layer 16L is composed of a second conductive material having a different composition than the first conductive material used to form the first bottom electrode-containing metal layer 14L. Therefore, the second bottom electrode-containing metal layer 16L has a different etch rate than the first bottom electrode-containing metal layer 14L. Exemplary second conductive materials that can be used to form the second bottom electrode-containing metal layer 16L include, but are not limited to, Al, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, or WN. The second bottom electrode-containing metal layer 16L has a second thickness that is less than the first thickness. In one embodiment, the second thickness is between 1 nm and 20 nm. In one example, when the first bottom electrode-containing metal layer 14L is composed of one of TaN, TiN, or W and has a first thickness of between 20 nm and 30 nm, the second bottom electrode-containing metal layer 16L is composed of Ru and has a second thickness of between 5 nm and 10 nm. The second bottom electrode-containing metal layer 16L can be formed by a deposition process such as, for example, sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0044] Now refer to Figure 3 , showing the third bottom electrode-containing metal layer 18L after being formed on the second bottom electrode-containing metal layer 16L Figure 2 An exemplary structure of Figure 3 As shown, the third bottom electrode containing metal layer 18L is a continuous layer formed over the entire second bottom electrode containing metal layer 16L.

[0045] The third bottom electrode-containing metal layer 18L is composed of a third conductive material having a composition that is different from at least the second conductive material that provides the second bottom electrode-containing metal layer 16L. The third conductive material that provides the third bottom electrode-containing metal layer 18L can have the same or different composition than the first conductive material that provides the first bottom electrode-containing metal layer 14L. Therefore, the etching rate of the third bottom electrode-containing metal layer 18L is different from the etching rate of the second bottom electrode-containing metal layer 16L, and the etching rate of the third bottom electrode-containing metal layer 18L can be the same or different from the etching rate of the first bottom electrode-containing metal layer 14L. Exemplary third conductive materials that can be used to provide the third bottom electrode-containing metal layer 18L include, but are not limited to, Al, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, or WN. The third bottom electrode-containing metal layer 16L has a third thickness that is greater than the second and first thicknesses described above. In one example, the third thickness is between 100 nm and 300 nm. In one example, when the first bottom electrode-containing metal layer 14L is composed of one of TaN, TiN, or W and has a first thickness of 20 nm to 30 nm, and the second bottom electrode-containing metal layer 16L is composed of Ru and has a second thickness of 5 nm to 10 nm, the third bottom electrode-containing metal layer 18L is composed of one of TaN, TiN, or W and has a third thickness of 150 nm to 225 nm. The third bottom electrode-containing metal layer 18L can be formed by a deposition process such as, for example, sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0046] Now refer to Figure 4 , showing the dielectric hard mask layer 20L after forming the third bottom electrode-containing metal layer 18L Figure 3 The dielectric hard mask layer 20L is a continuous layer covering the entire third bottom electrode-containing metal layer 18L. The dielectric hard mask layer 20L is composed of a dielectric hard mask material including, for example, silicon dioxide, silicon oxynitride, silicon nitride, or any combination thereof.

[0047] In some embodiments, the dielectric hard mask layer 20L can be formed using a deposition process such as, for example, chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). The dielectric hard mask layer 20L can have a thickness of 50 nm to 150 nm; however, other thicknesses of the dielectric hard mask layer 20L are also contemplated and can be used in the present application.

[0048] Now refer to Figure 5 , showing the dielectric hard mask layer 20L after forming a plurality of patterned masks 22 Figure 4, wherein each patterned mask 22 is located over one of the conductive structures 12 embedded in the first interconnect dielectric material layer 10. Each patterned mask 22 is spaced apart from adjacent masks and is composed of a photoresist material such as a positive tone photoresist material, a negative tone photoresist material, or a mixed tone photoresist material.

[0049] Each patterning mask 22 can be formed by photolithography. Photolithography involves applying a photoresist material to the material or material stack to be patterned, exposing the photoresist material to a desired radiation pattern, and developing the exposed photoresist material using a conventional resist developer. The photoresist material can be applied using a deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or spin coating.

[0050] Now refer to Figure 6 , shows an exemplary structure after patterning dielectric hard mask layer 20L and third bottom electrode-containing metal layer 18L using a first etch and patterned mask 22 as an etch mask to provide a plurality of first patterned material stacks, each of which includes a dielectric hard mask material portion 20P and a third bottom electrode-containing metal portion 18P. The first etch stops on second bottom electrode-containing metal layer 16L. In one embodiment, the first etch is a reactive ion etch (RIE). In another embodiment, the first etch is a plasma etch.

[0051] The dielectric hard mask material portion 20P of each first patterned material stack is comprised of the remaining (i.e., non-etched) portion of the dielectric hard mask layer 20L, while the third bottom electrode-containing metal portion 18P is comprised of the remaining (i.e., non-etched) portion of the third bottom electrode-containing metal layer 18L. The outermost walls of the dielectric hard mask material portion 20P are vertically aligned with the outermost walls of the third bottom electrode-containing metal portion 18P. In some embodiments, each first patterned material stack (18P / 20P) has a width (i.e., diameter) that is equal to or less than the width (i.e., diameter) of the underlying conductive structure 12.

[0052] After the first etch, each patterned mask 22 can be removed from the first patterned material stack (18P / 20P) using a material removal process such as etching or planarization (i.e., chemical mechanical polishing (CMP) or grinding). Each patterned mask 22 can be removed before or after patterning the second bottom electrode-containing metal layer 16L and the first bottom electrode-containing metal layer 14L.

[0053] Now refer to Figure 7 , showing after performing a second etch to provide a plurality of multilayer bottom electrodes 19S Figure 6An exemplary structure, wherein each multilayer bottom electrode 19S includes, from bottom to top, a conical base segment S1 having a first diameter, which is composed of the remaining portion of the first bottom electrode-containing metal layer 14L (hereinafter referred to as the first bottom electrode-containing metal material 14); a middle segment S2 having a second diameter, which is composed of the remaining portion of the second bottom electrode-containing metal layer 16L (hereinafter referred to as the second bottom electrode-containing metal material 16); and an upper segment S3 having a third diameter, which is composed of the remaining portion of the third bottom electrode-containing metal portion 18P (hereinafter referred to as the third bottom electrode-containing metal material 18), wherein the first diameter is greater than the second diameter, and the third diameter is equal to or less than the second diameter.

[0054] The term "tapered base segment" means that the base segment of each multilayer bottom electrode 19S has an outermost sidewall that slopes outward from the highest surface of the base segment to the lowest surface of the base segment. In other words, the tapered base segment S1 of each multilayer bottom electrode is tapered in shape, with the width of the upper portion being smaller than the width of the lower portion.

[0055] The second etch used in this step of the present application causes tapering. The second etch can be an ion beam etch (IBE) or a reactive ion etch (RIE). In one example, IBE is used where the ion beam is directed at a high angle (i.e., from 35° to 65°) relative to the vertical sidewalls of each first patterned material stack so that etching is performed at such an angle. The ion beam can be rotated around each first patterned material stack to provide uniform 'patterning'. During IBE, the third bottom electrode containing metal portion 18P is trimmed and the second bottom electrode containing metal layer 16L and the first bottom electrode containing metal layer 14L are etched to provide Figure 7 The multilayer bottom electrode 19S is shown. The shape of the upper segment S3 and the middle segment S2 of each multilayer bottom electrode 19S can be cylindrical, but other asymmetric shapes are also possible and can be used as the shape of the upper segment S3 and the middle segment S2 of each multilayer bottom electrode 19S in the present application. In another example, reactive ion etching (RIE) is used, where the parameters of the reactive ion etching cause tapering to provide the multilayer bottom electrode 19S of the present application.

[0056] In one embodiment of the present application, the first diameter S1 of the tapered base section of each multi-layer bottom electrode 19S may be from 20 nm to 150 nm, the second diameter S2 of the middle section of each multi-layer bottom electrode 19S may be from 7 nm to 120 nm, and the third diameter S3 of the upper section of each multi-layer bottom electrode 19S may be from 6 nm to 110 nm. In the present application, the tapered base section S1 of each multi-layer bottom electrode 19S has the first height of the first bottom electrode-containing metal layer 14L, the middle section S2 of each multi-layer bottom electrode 19S has the second height of the second bottom electrode-containing metal layer 16L, and the upper section S3 of each multi-layer bottom electrode 19S has the third height of the third bottom electrode-containing metal layer 18L.

[0057] Each multilayer bottom electrode 19S typically has a high aspect ratio. "High aspect ratio" means that the multilayer bottom electrode 19S has a height-to-diameter ratio greater than 2 to 1 (the height is the first height plus the second height plus the third height, and the diameter is determined by the diameter of the tapered lower section S1 of each multilayer bottom electrode 19S). In one example, each multilayer bottom electrode 19S has an aspect ratio of from 4:1 to 100:1. In some embodiments, each multilayer bottom electrode 19S may have an aspect ratio of 2 to 1 or less (i.e., 1 to 1).

[0058] Each multilayer bottom electrode 19S directly contacts one of the underlying conductive structures 12. Each multilayer bottom electrode 19S has a width that is less than the width of the underlying conductive structure 12. The wider tapered base section S1 of each multilayer bottom electrode 19S prevents tilting and / or bending of the resulting bottom electrode 19S. Thus, a stable bottom electrode 19S is provided.

[0059] After performing the second etch, each dielectric hard mask material portion 20P and each patterned mask 22 (if not previously removed) may be removed using one or more material removal processes. In one example, when each patterned mask 22 is present during the second etch, each patterned mask 22 and each dielectric hard mask material portion 20P may be removed using planarization (i.e., chemical mechanical polishing (CMP) or grinding). In another example, when each patterned mask 22 is present during the second etch, each patterned mask 22 may be removed using a first material removal process (i.e., chemical wet etching), and thereafter each dielectric hard mask material portion 20P may be removed using a second material removal process, such as planarization (i.e., chemical mechanical polishing (CMP) or grinding). In another embodiment, when each patterned mask 22 has already been removed before the second etch, each dielectric hard mask material portion 20 may be removed using an etching process or a planarization process (i.e., chemical mechanical polishing (CMP) or grinding).

[0060] Now see Figure 8 , shows the state after forming a second interconnect dielectric material layer 24 laterally adjacent to each multi-layer bottom electrode 19S and forming a plurality of second patterned material stacks on the second interconnect dielectric material layer 24 Figure 7 An exemplary structure in which each second patterned material stack contacts the highest surface of the upper segment S3 of one of the underlying bottom electrodes 19S and includes a magnetic tunnel junction (MTJ) pillar 26P and a top electrode 34.

[0061] The second interconnect dielectric material layer 24 formed on the interconnect layer Ln can be composed of one of the interconnect dielectric materials described above for the first interconnect dielectric material layer 10. In one embodiment, the second interconnect dielectric material layer 24 is composed of an interconnect dielectric material having the same composition as the interconnect dielectric material providing the first interconnect dielectric material layer 10. In another embodiment, the second interconnect dielectric material layer 24 is composed of an interconnect dielectric material having a different composition than the interconnect dielectric material providing the first interconnect dielectric material layer 10. The second interconnect dielectric material layer 24 can be formed using one of the deposition processes described above for forming the first interconnect dielectric material layer 10. After depositing the interconnect dielectric material providing the second interconnect dielectric material layer 24, a planarization process such as CMP can be performed. The second interconnect dielectric material layer 24 has a top surface that is coplanar with the top surface of the upper segment S3 of each bottom electrode 19S.

[0062] After forming the second interconnect dielectric material layer 24, an MTJ material stack (not shown) and a top electrode-containing metal layer (not shown) are formed. The MTJ material stack may include at least a magnetic pinned layer, a tunnel barrier layer, and a magnetic free layer. In some embodiments, the MTJ material stack is a bottom pinned MTJ material stack, which includes a magnetic pinned layer, a tunnel barrier layer, and a magnetic free layer from bottom to top. An optional metal seed layer (not shown) may also be present in the bottom pinned MTJ material stack. In the bottom pinned MTJ material stack, an optional metal seed layer is formed below the magnetic pinned layer. The bottom pinned MTJ material stack may also include a non-magnetic spacer layer (not shown) located on the magnetic free layer, a second magnetic free layer (not shown) located on the non-magnetic spacer layer, and / or an MTJ cap layer (not shown) located on the magnetic free layer or on the second magnetic free layer.

[0063] In other embodiments, the MTJ material stack is a top-pinned MTJ material stack, which includes a magnetic free layer, a tunnel barrier layer, and a magnetic pinned layer from bottom to top. In such embodiments, the top-pinned MTJ material stack may further include an optional metal seed layer below the magnetic free layer, a nonmagnetic spacer layer on the magnetic free layer, a second magnetic free layer on the nonmagnetic spacer layer, and / or an MTJ cap layer on the magnetic pinned layer.

[0064] The various material layers of the MTJ material stack may be formed by utilizing one or more deposition processes, such as sputtering, plasma enhanced atomic layer deposition (PEALD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0065] The optional metal seed layer can be composed of platinum (Pt), palladium (Pd), nickel (Ni), rhodium (Rh), iridium (Ir), rhenium (Re), or alloys and multilayers thereof. In one example, the optional metal seed layer is composed of platinum (Pt).

[0066] The magnetic pinned layer has a fixed magnetization state. The magnetic pinned layer may be composed of a metal or metal alloy (or stack thereof) including one or more metals exhibiting high spin polarization. In alternative embodiments, exemplary metals for forming the magnetic pinned layer include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys may include the metals exemplified above. In another embodiment, the magnetic pinned layer may be a multilayer arrangement having (1) a high spin polarization region formed of a metal and / or a metal alloy using the above metals and (2) a region composed of one or more materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and may be arranged as alternating layers. The strong PMA region may also include an alloy exhibiting strong PMA, wherein exemplary alloys include cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys may be arranged as alternating layers. In one embodiment, a combination of these materials and regions may also be used as a magnetic pinning layer.

[0067] The tunnel barrier layer is composed of an insulator material and is formed to a thickness that provides appropriate tunneling resistance. Exemplary materials for the tunnel barrier layer include magnesium oxide, aluminum oxide, and titanium oxide, or materials with higher tunnel conductance, such as semiconductors or low-bandgap insulators.

[0068] The magnetic free layer can be composed of a magnetic material (or a stack of magnetic materials) having a magnetization that can change orientation relative to the magnetization orientation of the magnetic pinned layer. Exemplary magnetic materials for the magnetic free layer include alloys and / or multilayers of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys.

[0069] If present, the non-magnetic metallic spacer layer is composed of a non-magnetic metal or metal alloy that allows magnetic information to be transferred therethrough and also allows the two magnetically free layers to be magnetically coupled together such that, at equilibrium, the first and second magnetically free layers are always parallel. The non-magnetic metallic spacer layer allows for spin torque switching between the first and second magnetically free layers.

[0070] If present, the second magnetically free layer can include one of the magnetic materials described above for the magnetically free layer. In one embodiment, the second magnetically free layer is composed of the same magnetic material as the magnetically free layer. In another embodiment, the second magnetically free layer is composed of a magnetic material having a different composition than the magnetically free layer.

[0071] If present, the MTJ cap layer may be composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al, or other high melting point metals or conductive metal nitrides. The MTJ cap layer may have a thickness from 2 nm to 25 nm; other thicknesses are also possible and may be used as the thickness of the MTJ cap layer in this application.

[0072] The top electrode-containing metal layer may be composed of a conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. In one embodiment of the present application, the top electrode-containing metal layer is composed of Ti / TiN. In the present application, the top electrode-containing metal layer may have a thickness of 100 nm to 500 nm; although other thicknesses are also possible and may be used as the thickness of the top electrode-containing metal layer. The top electrode-containing metal layer may be formed by a deposition process such as sputtering, plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0073] Next, the top electrode-containing metal layer and the MTJ material stack are patterned to provide a plurality of second patterned material stacks. As described above, each second patterned material stack includes a magnetic tunnel junction (MTJ) pillar 26P and a top electrode 34. The MTJ pillar 26P includes the remaining (i.e., unetched) portion of the MTJ material stack. The top electrode 34 includes the remaining (i.e., unetched) portion of the top electrode-containing metal layer.

[0074] The patterning of the top electrode-containing metal layer and the MTJ material stack may include first forming a patterned mask (not shown) on the physically exposed surface of the top electrode-containing metal layer. In some embodiments, the patterned mask may be composed of a photoresist stack. In one embodiment, the photoresist stack providing the patterned mask may include a bottom organic layer, an intermediate inorganic layer, and a top resist layer. The bottom organic layer of the photoresist stack may include an organic planarization layer (OPL). The bottom organic layer of the photoresist stack may include a spin-on organic layer such as near-frictionless carbon (NFC), diamond-like carbon, thermosetting polyarylene ether, or polyimide. The intermediate inorganic layer of the photoresist stack may include any oxide layer, such as a low-temperature (e.g., less than or equal to 250° C.) CVD oxide, an oxide derived from TEOS (tetraethyl orthosilicate), silicon oxide, silane oxide, or a silicon-containing antireflective coating material (SiARC). The top resist layer of the photoresist stack may be composed of a resist material that provides high-resolution photolithographic patterning. A series of deposition processes may be first provided to form a photoresist stack, including a first spin-coating of a bottom organic layer, a second spin-coating of a middle inorganic layer, and a third spin-coating of a top resist layer. After providing the photoresist stack, the top resist layer is patterned by photolithography (i.e., exposing the top resist layer to an illumination pattern and then developing the exposed top resist layer), and then the pattern provided to the top resist layer is transferred into the underlying layers of the photoresist stack, thereby providing a patterned mask. The transfer may include one or more etching processes.

[0075] In some embodiments, patterning can include first patterning the top electrode-containing metal layer using a first etching process, such as reactive ion etching, using the patterned mask as an etch mask. The remaining (i.e., unpatterned) portion of the top electrode-containing metal layer provides the top electrode 34. The shape of the top electrode 34 can be cylindrical; although other asymmetric shapes are also possible and can be used as the shape of the top electrode 34 in this application. The critical dimension (CD) of the top electrode 34 can vary and is not critical in this application.

[0076] After patterning the top electrode-containing metal layer, the patterning mask is removed from the top of the top electrode 34 formed using conventional methods known to those skilled in the art. Patterning of the MTJ material stack is then performed using ion beam etching (IBE), wherein the top electrode 34 is used as a patterning mask. The remaining (i.e., unpatterned) portion of the MTJ material stack provides the MTJ pillar 26P. In one example, as Figure 8As shown, each MTJ pillar 26P includes, from bottom to top, a magnetic pinned material layer portion 28 (i.e., the remaining, unetched portion of the magnetic pinned material layer), a tunnel barrier layer portion 30 (i.e., the remaining, unetched portion of the tunnel barrier layer), and a magnetic free layer portion 32 (i.e., the remaining, unetched portion of the magnetic free layer). In another example (not shown), each MTJ pillar 26P includes, from bottom to top, a magnetic free layer portion, a tunnel barrier layer portion, and a magnetic pinned material layer portion. The MTJ pillar 26P may include the remaining portion of any other layer present in the MTJ material stack. The shape of the MTJ pillar 26P may be cylindrical, but other asymmetric shapes are also possible and may be used as the shape of the MTJ pillar 26P in this application; the MTJ pillar 26P and the top electrode 34 have the same shape. The critical dimension (CD) of the MTJ pillar 26P may vary and is not critical in this application. The CD of the MTJ pillar 26P is typically the same as the CD of the top electrode 34. As shown, the CD of the MTJ pillar 26P and the CD of the top electrode 34 are greater than the CD of the underlying top segment S3 of the bottom electrode 19S. The bottom electrode 19S, the MTJ pillar 26P, and the top electrode 34 collectively provide a memory structure according to the present application.

[0077] Now see Figure 9 , showing the encapsulation liner 36 and the third interconnect dielectric material layer 38 after forming the encapsulation liner 36 and the third interconnect dielectric material layer 38 laterally adjacent to each second patterned material stack Figure 8 The packaging liner 36 laterally surrounds the top electrode 34 and the MTJ pillar 26P. A third interconnect dielectric material layer 38 is located on the packaging liner 36 and fills the gaps between adjacent memory structures.

[0078] The packaging liner 36 is composed of a dielectric material having a different composition from that of the second interconnect dielectric material layer 24. The dielectric material providing the packaging liner 36 can provide passivation for the top electrode 34 and the MTJ pillar 26P. In one embodiment, the packaging liner 36 is composed of silicon nitride. In another embodiment, the packaging liner 36 can be composed of a dielectric material containing silicon, carbon, and hydrogen atoms. In some embodiments, in addition to carbon and hydrogen atoms, the dielectric material providing the packaging liner 36 can include atoms of at least one of nitrogen and oxygen. In other embodiments, in addition to silicon, nitrogen, carbon, and hydrogen atoms, the dielectric material providing the packaging liner 36 can include boron atoms. In one example, the packaging liner 36 can be composed of an nBLOK dielectric material containing atoms of silicon, carbon, hydrogen, nitrogen, and oxygen. In an alternative example, the packaging liner 36 can be composed of a SiBCN dielectric material containing atoms of silicon, boron, carbon, hydrogen, and nitrogen.

[0079] The encapsulation liner 36 can be formed by first depositing a continuous layer of dielectric material that provides the encapsulation liner 36. During a subsequent planarization process for forming the third interconnect dielectric material layer 38, the dielectric material that provides the encapsulation liner 36 is removed from the highest surface of each top electrode 34. The encapsulation liner 36 can have a thickness of from 10 nm to 200 nm. Other thicknesses are also possible and can be used as the thickness of the encapsulation liner 36. The encapsulation liner 36 generally has a highest surface that is coplanar with the highest surface of the top electrode 34.

[0080] Third interconnect dielectric material layer 38 may include one of the aforementioned interconnect dielectric materials. The composition of the interconnect dielectric material providing third interconnect dielectric material layer 38 may be the same as or different from the composition of the interconnect dielectric material providing first interconnect dielectric material layer 10 and / or second interconnect dielectric material layer 24. Third interconnect dielectric material layer 38 may be formed using conventional deposition processes including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or spin coating. Following deposition of the interconnect dielectric material providing third interconnect dielectric material layer 38, a planarization process such as chemical mechanical polishing (CMP) may be performed; as described above, this planarization step also removes the dielectric material providing package liner 36 from the uppermost surface of top electrode 34.

[0081] Now refer to Figure 10 , which shows an exemplary structure that can be adopted according to another embodiment of the present application. Figure 10 The exemplary structure includes an interconnect layer L n The first bottom electrode-containing metal layer 50L on the surface of the interconnect layer L includes a conductive structure 12 embedded in the first interconnect dielectric material layer 10. n With the above for this application Figure 1 The same is mentioned in the exemplary structure shown in FIG.

[0082] Although not shown in the drawings, the metal layer defined above may be located below the interconnect layer Ln. Figure 10 In some embodiments, when n is 1, the metal layer is a middle of line (MOL) layer as defined above. In other embodiments, when n is 2, 3, 4, etc., the metal layer is located in the interconnect layer L as defined above. n In any embodiment, the metal layer comprises a layer of dielectric material (as defined above) containing at least one metal layer conductive structure (as defined above) embedded therein, the at least one metal layer conductive structure being directly or indirectly connected to an underlying CMOS device (not shown) present in a front end of line (FEOL) layer (also not shown).

[0083] A first bottom electrode-containing metal layer 50L is formed over the entire interconnect layer Ln. The first bottom electrode-containing metal layer 50L is composed of a first conductive material including, but not limited to, Al, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, or WN. The first bottom electrode-containing metal layer 50L has a first thickness. In one example, the first bottom electrode-containing metal layer 50L is composed of Ru. The first bottom electrode-containing metal layer 50L can be formed by a deposition process such as, for example, sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0084] Now see Figure 11 , showing the second bottom electrode-containing metal layer 52L formed on the first bottom electrode-containing metal layer 50L Figure 10 An exemplary structure wherein the second bottom electrode-containing metal layer 52L has a higher lateral trim rate than the first bottom electrode-containing metal layer 50L. Figure 11 As shown, the second bottom electrode containing metal layer 52L is a continuous layer formed over the entire first bottom electrode containing metal layer 50L. The term "lateral etch rate" refers to the rate at which material is removed starting from the outer sidewalls and moving inward toward the interior of the material.

[0085] The second bottom electrode-containing metal layer 52L is composed of a second conductive material having a different composition than the first conductive material providing the first bottom electrode-containing metal layer 50L. In the present application, the second conductive material is selected to have a higher lateral etch rate than the first conductive material. Exemplary second conductive materials that can be used to provide the second bottom electrode-containing metal layer 52L include, but are not limited to, Al, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, or WN. The second bottom electrode-containing metal layer 52L has a second thickness that is equal to, less than, or greater than the first thickness. In one example, when the first bottom electrode-containing metal layer 50L is composed of Ru, the second bottom electrode-containing metal layer 52L is composed of TaN. The second bottom electrode-containing metal layer 52L can be formed by a deposition process such as, for example, sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0086] Now refer to Figure 12 , showing the third bottom electrode-containing metal layer 54L after being formed on the second bottom electrode-containing metal layer 52L Figure 11 An exemplary structure wherein the third bottom electrode-containing metal layer 54L has a higher lateral trim rate than the second bottom electrode-containing metal layer 52L. Figure 12 As shown, the third bottom electrode containing metal layer 54L is a continuous layer formed over the entire second bottom electrode containing metal layer 52L.

[0087] The third bottom electrode-containing metal layer 54L is composed of a third conductive material selected to have a higher lateral trim rate than the second conductive material and the first conductive material. Thus, the third conductive material is compositionally different from the second conductive material providing the second bottom electrode-containing metal layer 54L and compositionally different from the first conductive material providing the first bottom electrode-containing metal layer 50L. Exemplary third conductive materials that can be used to provide the third bottom electrode-containing metal layer 54L include, but are not limited to, Al, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, or WN. The third bottom electrode-containing metal layer 54L has a third thickness that can be equal to, less than, or greater than the first and second thicknesses described above. In one example, when the first bottom electrode-containing metal layer 50L is composed of Ru and the second bottom electrode-containing metal layer 52L is composed of TaN, the third bottom electrode-containing metal layer 54L is composed of one of Ti, TiN, or Al. The third bottom electrode-containing metal layer 54L can be formed by a deposition process such as, for example, sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0088] Now see Figure 13 , showing after a dielectric hard mask layer 56L is formed on the third bottom electrode-containing metal layer 54L and after a plurality of patterned masks 58 are formed on the dielectric hard mask layer 56L Figure 12 , wherein each patterned mask 58 is located over one of the conductive structures 12 embedded in the first interconnect dielectric material layer 10.

[0089] The dielectric hard mask layer 56L is a continuous layer that covers the entire third bottom electrode-containing metal layer 54L. The dielectric hard mask layer 56L is composed of one of the dielectric hard mask materials described above for the dielectric hard mask layer 20L. The dielectric hard mask layer 56L can be formed using one of the deposition processes described above for forming the dielectric hard mask layer 20L, and the thickness of the dielectric hard mask layer 56L can be within the thickness range of the dielectric hard mask layer 20L described above.

[0090] Patterned mask 58 can be formed from one of the photoresist materials described above for patterned mask 22. Patterned mask 58 can be formed using the techniques described above for forming patterned mask 22.

[0091] Now refer to Figure 14 , shows after the pattern provided by each patterned mask 58 is transferred into the dielectric hard mask layer 56L to provide a plurality of dielectric hard masks 56P below each patterned mask 58 Figure 13Transferring the pattern provided by each patterned mask 58 into the dielectric hard mask layer 56L can be performed using an etching process such as plasma etching or reactive ion etching. The etching for pattern transfer stops on the third bottom electrode-containing metal layer 54L.

[0092] Each dielectric hard mask 56P is formed from a remaining (ie, unetched) portion of dielectric hard mask layer 56L. The outermost sidewall of each dielectric hard mask 56P is vertically aligned with the outermost sidewall of one of the overlying patterned masks 58.

[0093] Each patterned mask 58 is typically performed after a pattern transfer step. Figure 15 The removal of each patterned mask 58 may be performed using a material removal process such as etching or a planarization process (ie, chemical mechanical polishing or grinding).

[0094] Now refer to Figure 15 , showing after etching using each patterned hard mask 56 as an etch mask to provide a plurality of multilayer bottom electrodes 55S Figure 14 An exemplary structure of a multilayer bottom electrode 55S. Each multilayer bottom electrode 55S comprises, from bottom to top, a base segment S1 having a first diameter and formed from the remaining portion of the first bottom electrode-containing metal layer 50L (hereinafter referred to as the first bottom electrode-containing metal material 50); a middle segment S2 having a second diameter and formed from the second bottom electrode-containing metal layer 52L (hereinafter referred to as the second bottom electrode-containing metal material 52); and an upper segment S3 having a third diameter and formed from the remaining portion of the third bottom electrode-containing metal layer 54L (hereinafter referred to as the third bottom electrode-containing metal material 54). The first diameter is greater than the second diameter, and the third diameter is smaller than the first and second diameters. The wider base segment S1 of each multilayer bottom electrode 55S prevents the resulting bottom electrode 55S from tilting and / or bending. Thus, a stable bottom electrode 55S is provided.

[0095] In the present application, the base segment S1 of the multilayer bottom electrode 55S has a larger critical dimension (CD) than the middle segment S2 of the multilayer bottom electrode 55S, and the middle segment S2 of the multilayer bottom electrode 55S has a larger critical dimension (CD) than the upper segment S3 of the multilayer bottom electrode 55S.

[0096] In this embodiment, the etching process for providing each multilayer bottom electrode 55S may include IBE or RIE. The shape of the upper segment S3, the middle segment S2, and the base segment S1 of each multilayer bottom electrode 55S may be cylindrical, however, other asymmetric shapes are also possible and may be used as the shape of the upper segment S3, the middle segment S2, and the base segment S1 of each multilayer bottom electrode 55S in the present application.

[0097] In one embodiment of the present application, the first diameter S1 of the base segment of each multi-layer bottom electrode 55S may be from 20 nm to 150 nm, the second diameter S2 of the middle segment of each multi-layer bottom electrode 55S may be from 7 nm to 120 nm, and the third diameter S3 of the upper segment of each multi-layer bottom electrode 55S may be from 6 nm to 110 nm. In the present application, the base segment S1 of each multi-layer bottom electrode 55S has the first height of the first bottom electrode-containing metal layer 50L, the middle segment S2 of each multi-layer bottom electrode 55S has the second height of the second bottom electrode-containing metal layer 52L, and the upper segment S3 of each multi-layer bottom electrode 55S has the third height of the third bottom electrode-containing metal layer 54L.

[0098] Each multilayer bottom electrode 55S typically has a high aspect ratio. "High aspect ratio" means that the multilayer bottom electrode 55S has a height-to-diameter ratio greater than 2 to 1 (the height is the first height plus the second height plus the third height, and the diameter is determined by the diameter of the lower segment S1 of each multilayer bottom electrode 55S). In one example, each multilayer bottom electrode 55S has an aspect ratio from 4:1 to 100:1. In some embodiments, each multilayer bottom electrode 55S may have an aspect ratio of 2 to 1 or less (i.e., 1 to 1).

[0099] Each multi-layer bottom electrode 55S directly contacts one of the underlying conductive structures 12. The width of each multi-layer bottom electrode 55S is smaller than the width of the underlying conductive structure 12.

[0100] After performing the etching that provides the multi-layer bottom electrode 55S, each patterned hard mask 56P is removed. The removal of each patterned hard mask 56P may be performed using a material removal process such as etching or a planarization process (ie, chemical mechanical polishing or grinding).

[0101] Now see Figure 16 , shows the state after forming a second interconnect dielectric material layer 24 laterally adjacent to each multi-layer bottom electrode 55S and forming a plurality of patterned material stacks on the second interconnect dielectric material layer 24 Figure 15 An exemplary structure in which each patterned material stack contacts the highest surface of the upper segment S3 of one of the underlying bottom electrodes 55S and includes a magnetic tunnel junction (MTJ) pillar 26P and a top electrode 32.

[0102] The second interconnect dielectric material layer 24 of this embodiment of the present application is similar to the above-mentioned Figure 8 The second interconnect dielectric material layer 24 is the same as that described in the exemplary structure shown. Figure 8The exemplary structure shown in FIG is the same as that described with respect to the MTJ pillar 26P and the top electrode 32. Thus, the various materials and processes described above for the second interconnect dielectric material layer 24 and the MTJ pillar 26P and the top electrode 32 are applicable here to this embodiment of the present application.

[0103] Now see Figure 17 , showing the encapsulation liner 36 and the third interconnect dielectric material layer 38 after forming each patterned material stack (ie, MTJ pillar 26P and top electrode 32) laterally adjacent to the Figure 16 An exemplary structure of .

[0104] The packaging liner 36 and the third interconnect dielectric material layer 38 of this embodiment of the present application are similar to those described above. Figure 9 The encapsulation liner 36 and the third interconnect dielectric material layer 38 are the same as those described in the exemplary structure shown in FIG. Therefore, the various materials and treatments described above for the encapsulation liner 36 and the third interconnect dielectric material layer 38 are applicable here to this embodiment of the present application.

[0105] Although the present application has been particularly shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. A memory structure comprising: a multi-layer bottom electrode positioned on a surface of a conductive structure embedded in the first interconnect dielectric material layer, wherein the multi-layer bottom electrode comprises a base segment having a first diameter and comprised of a first conductive material, a middle segment having a second diameter and comprised of a second conductive material having a different composition than the first conductive material, and an upper segment having a third diameter and comprised of a third conductive material having a different composition than the second conductive material, wherein the first diameter is greater than the second diameter and the third diameter is equal to or less than the second diameter; a second interconnect dielectric material layer laterally adjacent to the multi-layer bottom electrode, wherein the second interconnect dielectric material layer contacts the highest surfaces of both the base segment and the middle segment of the multi-layer bottom electrode; a magnetic tunnel junction (MTJ) pillar located on a topmost surface of an upper segment of the multi-layer bottom electrode; and Top electrode located on the MTJ pillar.

2. The memory structure according to claim 1, wherein: The base section tapers from a first diameter to a surface in contact with the mid-section.

3. The memory structure according to claim 1, wherein: The third diameter is smaller than the first diameter and the second diameter.

4. A memory structure according to any one of the preceding claims, wherein: The first diameter is 20 nm to 150 nm, the second diameter is 7 nm to 120 nm, and the third diameter is 6 nm to 110 nm.

5. The memory structure according to claim 1 or 2, wherein: The third conductive material has the same composition as the first conductive material.

6. The memory structure according to claim 2 or 3, wherein: The third conductive material has a different composition from the first conductive material.

7. The memory structure according to any one of claims 1 to 3, wherein: The MTJ pillar consists of a top-pinned MTJ material stack.

8. The memory structure according to any one of claims 1 to 3, wherein: The MTJ pillar consists of a bottom-pinned MTJ material stack.

9. The memory structure according to any one of claims 1 to 3, wherein: The MTJ pillar and the top electrode have the same critical dimension, and the critical dimensions of the MTJ pillar and the top electrode are larger than the critical dimension of the upper segment of the multi-layer bottom electrode.

10. The memory structure of claim 9, further comprising a packaging liner and a third interconnect dielectric material layer laterally adjacent to the MTJ pillar and the top electrode, wherein A packaging pad contacts sidewalls of the MTJ pillar and the top electrode, and a third interconnect dielectric material layer is located on the packaging pad.

11. A method of forming a memory structure, the method comprising: forming a structure comprising: an interconnect layer including a conductive structure embedded in a first interconnect dielectric material layer, a first bottom electrode-containing metal layer on the interconnect layer, a second bottom electrode-containing metal layer on the first bottom electrode-containing metal layer, a third bottom electrode-containing metal layer on the second bottom electrode-containing metal layer, wherein the second bottom electrode-containing metal layer is composed of a conductive material having a different etch rate than conductive materials of the first and third bottom electrode-containing metal layers, and a dielectric hard mask layer on the third bottom electrode-containing metal layer; forming a patterned mask on the dielectric hard mask layer, wherein the patterned mask is located over the conductive structure embedded in the first interconnect dielectric material layer; patterning the dielectric hard mask layer and the third bottom electrode-containing metal layer using a first etch and the patterned mask as an etch mask to provide a first patterned material stack, the first patterned material stack including a dielectric hard mask material portion and a third bottom electrode-containing metal portion; performing a second etch to provide a multi-layer bottom electrode, wherein the multi-layer bottom electrode comprises, from bottom to top, a tapered base segment having a first diameter and consisting of a remaining portion of the first bottom electrode-containing metal layer, a middle segment having a second diameter and consisting of a remaining portion of the second bottom electrode-containing metal layer, and an upper segment having a third diameter and consisting of a remaining portion of the third bottom electrode-containing metal layer, wherein the first diameter is greater than the second diameter and the third diameter is equal to or less than the second diameter; and A second interconnect dielectric material layer is formed laterally adjacent to the multi-layer bottom electrode, wherein the second interconnect dielectric material layer contacts the highest surfaces of both the base segment and the middle segment of the multi-layer bottom electrode.

12. The method according to claim 11, further comprising: A second patterned material stack is formed on the second interconnect dielectric material layer, wherein the second patterned material stack contacts a highest surface of an upper segment of the bottom electrode and includes a magnetic tunnel junction (MTJ) pillar and a top electrode. 13 . The method of claim 12 , further comprising forming an encapsulation liner and a third interconnect dielectric material layer laterally adjacent to the second patterned material stack.

14. The method according to claim 11, wherein The first etching includes plasma etching or reactive ion etching, and the second etching includes ion beam etching or reactive ion etching.

15. The method according to claim 11, wherein The first conductive material is one of TaN, TiN, or W, the second conductive material is Ru, and the third conductive material is one of TaN, TiN, or W.

16. The method according to claim 11, wherein The first bottom electrode-containing metal layer has a first height, the second bottom electrode-containing metal layer has a second height, and the third bottom electrode-containing metal layer has a third height, wherein the first height is less than the second height and the second height is less than the third height.

17. A method of forming a memory structure, the method comprising: forming a structure comprising: an interconnect layer comprising a conductive structure embedded in a first interconnect dielectric material layer, a first bottom electrode-containing metal layer on the interconnect layer, a second bottom electrode-containing metal layer on the first bottom electrode-containing metal layer, wherein the second bottom electrode-containing metal layer has a higher lateral trim rate than the first bottom electrode-containing metal layer, a third bottom electrode-containing metal layer on the second bottom electrode-containing metal layer, wherein the third bottom electrode-containing metal layer has a higher lateral trim rate than the second bottom electrode-containing metal layer, and a dielectric hard mask layer on the third bottom electrode-containing metal layer; forming a patterned mask on the dielectric hard mask layer, wherein the patterned mask is located over the conductive structure embedded in the first interconnect dielectric material layer; transferring a pattern provided by the patterned mask into the dielectric hard mask layer to provide a dielectric hard mask beneath the patterned mask; patterning each of the first bottom electrode-containing metal layer, the second bottom electrode-containing metal layer, and the third bottom electrode-containing metal layer using the patterned hard mask as an etch mask to provide a multi-layer bottom electrode, wherein the multi-layer bottom electrode includes, from bottom to top, a base segment having a first diameter and consisting of a remaining portion of the first bottom electrode-containing metal layer, a middle segment having a second diameter and consisting of a remaining portion of the second bottom electrode-containing metal layer, and an upper segment having a third diameter and consisting of a remaining portion of the third bottom electrode-containing metal layer, wherein the first diameter is greater than the second diameter and the third diameter is smaller than the first diameter and the second diameter; and A second interconnect dielectric material layer is formed laterally adjacent to the multi-layer bottom electrode, wherein the second interconnect dielectric material layer contacts the highest surfaces of both the base segment and the middle segment of the multi-layer bottom electrode.

18. The method according to claim 17, further comprising: A patterned material stack is formed on the second interconnect dielectric material layer, wherein the patterned material stack contacts a highest surface of an upper segment of the bottom electrode and includes a magnetic tunnel junction (MTJ) pillar and a top electrode.

19. The method of claim 18, further comprising forming an encapsulation liner and a third interconnect dielectric material layer laterally adjacent to the patterned material stack.

20. The method according to claim 17, wherein The first bottom electrode-containing metal layer is composed of Ru, the second bottom electrode-containing metal layer is composed of TaN, and the third bottom electrode-containing metal layer is composed of one of Ti, TiN, or Al.

21. The method according to claim 17, wherein The patterning of each of the first bottom electrode containing metal layer, the second bottom electrode containing metal layer, and the third bottom electrode containing metal layer includes ion beam etching or reactive ion etching.

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