Method, apparatus, and autonomous vehicle for system on chip (soc) upgrade

Abstract

The disclosure provides a method for system on chip (SOC) upgrading, applied to a target central processing unit (CPU) core, the SOC containing at least two CPU cores, the target CPU core being one of the at least two CPU cores, relating to the technical field of computers, and particularly to the technical fields of system on chip and intelligent driving. The specific implementation scheme is as follows: reading a preset configuration file; determining a role of the target CPU core based on the preset configuration file, wherein the role includes a master core or a slave core; and according to the determined role, performing one of the following two: in response to determining that the role is the master core, performing master core flashing according to a detected upgrading instruction from outside the SOC; and in response to determining that the role is the slave core, stopping communication with the outside of the SOC.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the fields of system-on-chip (SOC) and intelligent driving technology, especially to methods, apparatus for upgrading system-on-chip and autonomous vehicles. Background Technology

[0002] With the rapid development of intelligent driving technology, higher demands are being placed on the processing capabilities of vehicles. To meet these performance requirements, System-on-Chips (SoCs) are gradually being widely used in vehicles.

[0003] In existing technologies, microcontroller units (MCUs) typically appear in a heterogeneous multi-core form. Their upgrade process usually involves a fixed master core interacting with the outside world and flashing the other slave cores. The multi-cores involved in this upgrade process have a fixed master-slave structure, and the flashing direction is simply from the master core to the slave cores. Summary of the Invention

[0004] A method, apparatus, and autonomous vehicle for system-on-chip upgrades are provided.

[0005] According to a first aspect, a method for upgrading a system-on-a-chip (SoC) is provided, applied to a target central processing unit (CPU) core, the SoC comprising at least two CPU cores, the target CPU core being one of the at least two CPU cores, the method comprising: reading a preset configuration file; determining the role of the target CPU core based on the preset configuration file, wherein the role includes a master core or a slave core; and, according to the determined role, performing one of the following: in response to determining the role as a master core, performing a master core flash according to a detected upgrade instruction from outside the SoC; and in response to determining the role as a slave core, stopping communication with outside the SoC.

[0006] According to a second aspect, an apparatus for system-on-chip (SoC) upgrade is provided, applied to a target CPU core, wherein the SoC includes at least two CPU cores, and the target CPU core is one of the at least two CPU cores. The apparatus includes: a read unit configured to read a preset configuration file; a determine unit configured to determine the role of the target CPU core based on the preset configuration file, wherein the role includes a master core or a slave core; and an execute unit configured to perform one of the following based on the determined role: in response to determining that the role is a master core, performing a master core flash according to a detected upgrade instruction from outside the SoC; in response to determining that the role is a slave core, stopping communication with outside the SoC.

[0007] According to a third aspect, a system-on-a-chip is provided, the system-on-a-chip comprising: at least two homogeneous CPU cores, wherein the at least two homogeneous CPU cores include a CPU core serving as a master core and at least one CPU core serving as a slave core; and a memory communicatively connected to the at least two homogeneous CPU cores; wherein the memory stores instructions executable by the at least two homogeneous CPU cores, the instructions being executed by at least one CPU core to enable the at least one CPU core to perform a method as described in any implementation of the first aspect.

[0008] According to a fourth aspect, a non-transitory computer-readable storage medium is provided that stores computer instructions for enabling a computer to perform methods as described in any implementation of the first aspect.

[0009] According to a fifth aspect, a computer program product is provided, including a computer program that, when executed by a processor, implements the method as described in any implementation of the first aspect.

[0010] According to the sixth aspect, an autonomous vehicle is provided, including an on-chip system as described in the third aspect.

[0011] According to the seventh aspect, a roadside device is provided, including a system-on-a-chip as described in the third aspect.

[0012] The technology disclosed herein enables each CPU core of the on-chip system to read a preset configuration file and determine whether it is a master core or a slave core. This allows the CPU core with the role of master core to undertake external communication and upgrade functions, thus realizing the dynamic determination of the master and slave core roles and providing a foundation for ensuring the reliability of the entire on-chip system upgrade.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0014] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0015] Figure 1 This is a schematic diagram based on the first embodiment of the present disclosure;

[0016] Figure 2 This is a schematic diagram according to the second embodiment of the present disclosure;

[0017] Figure 3 This is a schematic diagram of an application scenario in which the method for upgrading an on-chip system according to the embodiments of this disclosure can be implemented;

[0018] Figure 4 This is a schematic diagram of an apparatus for system-on-chip upgrade according to an embodiment of the present disclosure;

[0019] Figure 5 This is a block diagram of an on-chip system used to implement the method for on-chip system upgrades in the embodiments of this disclosure. Detailed Implementation

[0020] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0021] Figure 1 This illustrates a schematic diagram 100 according to a first embodiment of the present disclosure. The method for system-on-chip upgrades, applied to a target CPU core on a System-on-Chip (SoC) containing at least two CPU cores, specifically includes the following steps:

[0022] S101, read the preset configuration file.

[0023] In this embodiment, the execution entity of the method for system-on-chip upgrade (e.g., the target CPU core on a SoC containing at least two CPU cores) can read a preset configuration file in various ways. The target CPU core can be, for example, any pre-specified CPU. The preset configuration file can be used to indicate whether one of the at least two CPUs in the SoC where the execution entity resides is a master core or a slave core. The master and slave cores can typically be designed using the same architecture. As an example, the preset configuration file can record the correspondence between CPU core identifiers and their corresponding roles (e.g., master core or slave core), allowing each CPU core to determine its role based on its identifier.

[0024] It should be noted that the aforementioned execution entity can be the target CPU core. The aforementioned SoC can contain at least two CPU cores. The aforementioned target CPU core can be one of the aforementioned at least two CPU cores.

[0025] S102 determines the role of the target CPU core based on a preset configuration file.

[0026] In this embodiment, the execution entity can determine the role of the target CPU core based on the preset configuration file read in step S101 through various methods. The role can include a master core or a slave core. The master core typically represents a CPU core that interacts with the external systems on the chip. The master core can also send upgrade commands to slave cores via inter-core communication. The slave core typically represents a CPU core with external communication and active upgrade functions disabled, typically retaining only the functions of receiving flash commands and flashing itself.

[0027] S103, depending on the determined role, perform one of the following two actions: in response to determining that the role is the master core, perform master core flashing according to the detected upgrade instructions from outside the SOC; in response to determining that the role is the slave core, stop communication with outside the SOC.

[0028] In this embodiment, based on the role determined in step S102, the execution entity may perform one of the following two actions: in response to determining that the role is the master core, perform master core flashing according to the detected upgrade instructions from outside the SOC; in response to determining that the role is the slave core, stop communication with outside the SOC.

[0029] In this embodiment, in response to determining that the role determined in step S102 is the main core, the execution entity can detect upgrade commands from outside the SOC. These upgrade commands can be, for example, upgrade commands sent by a server to upgrade the SOC system. In response to detecting an upgrade command from outside the SOC, the execution entity can perform main core flashing according to the detected upgrade command in various ways. As an example, the execution entity can perform main core flashing according to a preset upgrade process or the upgrade process indicated by the upgrade command.

[0030] In this embodiment, in response to determining that the role identified in step S102 is a slave core, the execution entity can stop communicating with the outside of the SOC. Specifically, since at least two CPU cores on the SOC are typically designed using the same architecture, both CPU cores have the foundation to implement all the functions of the CPU core. However, when the target CPU core among the at least two CPU cores determines that its role is a slave core, the execution entity can disable its module for communicating with the outside of the SOC, thereby still being able to communicate with the master core through inter-core communication. Optionally, the execution entity as a slave core can also disable the active upgrade module, thereby retaining only the module for receiving flash commands and flashing itself.

[0031] The method provided in the above embodiments of this disclosure enables each CPU core of the on-chip system to read a preset configuration file and determine whether it is a master core or a slave core. This allows the CPU core with the role of master core to undertake external communication and upgrade functions, thereby realizing the dynamic determination of the master core and slave core roles and providing a foundation for ensuring the reliability of the entire on-chip system upgrade.

[0032] In some optional implementations of this embodiment, based on a preset configuration file, the execution entity can determine the role of the target CPU core according to the following steps:

[0033] S1021, in response to determining that the preset configuration file indicates the target CPU core to be the master core, sends a master core confirmation signal to other CPU cores on the SOC through inter-core communication.

[0034] In these implementations, in response to determining that a preset configuration file indicates the target CPU core's role as the master core, the aforementioned execution entity can send a master core acknowledgment signal to other CPU cores on the SOC via inter-core communication. This master core acknowledgment signal can be used to notify the existence of a master core.

[0035] Optionally, the aforementioned execution entity can also periodically send master core confirmation signals to other CPU cores on the SOC via inter-core communication at preset time intervals.

[0036] S1022, based on the received response confirmation information corresponding to the main core confirmation signal, determine the role of the target CPU core.

[0037] In these implementations, based on the response confirmation information received corresponding to the main core confirmation signal sent in step S1021 above, the execution entity can determine the role of the target CPU core in various ways.

[0038] As an example, if the execution entity does not receive response confirmation information corresponding to the master core confirmation signal sent in step S1021 within a preset time interval, the execution entity can determine that the target CPU core is a slave core. As another example, if the execution entity receives response confirmation information corresponding to the master core confirmation signal sent in step S1021, the execution entity can determine that the target CPU core is a master core. The response confirmation information can be used to indicate that the slave core acknowledges the existence of the master core.

[0039] Based on the above-mentioned optional implementation methods, this solution can use the main core confirmation signal used to notify the existence of the main core and the corresponding response confirmation information to comprehensively determine the role of the target CPU core, thereby improving the accuracy of the role determination of the target CPU core and providing technical assurance for subsequent system upgrades.

[0040] Optionally, based on the above-mentioned optional implementation method, and based on the response confirmation information corresponding to the main core confirmation signal received, the execution entity can determine the role of the target CPU core according to the following steps:

[0041] The first step is to receive a response confirmation message corresponding to the main core confirmation signal and then perform a second verification according to the preset configuration file.

[0042] In these implementations, in response to receiving a response confirmation message corresponding to the master core confirmation signal, the execution entity can perform a second verification based on the preset configuration file to confirm whether the master core indicated in the configuration file is itself.

[0043] The second step is to verify the result of the second verification based on the preset configuration file to determine the role of the target CPU core.

[0044] In these implementations, based on the results of the re-verification performed in the first step above, the execution entity can determine the role of the target CPU core in various ways.

[0045] Optionally, based on the method described in the second step above, and according to the result of a second verification based on a preset configuration file, the execution entity can determine the role of the target CPU core according to the following steps:

[0046] Step 1: In response to the result of the re-verification based on the preset configuration file, the role of the target CPU core as the master core is determined.

[0047] Step 2: In response to the result of the re-verification based on the preset configuration file indicating that the target CPU core is not the master core, determine that the target CPU core is a slave core.

[0048] Based on the above-mentioned optional implementation methods, this solution can perform a second verification according to a preset configuration file after receiving the response confirmation information corresponding to the main core confirmation signal, and determine the role of the target CPU core based on the result of the second verification, thereby further improving the accuracy of the role determination of the target CPU core and providing a more solid technical guarantee for subsequent system upgrades.

[0049] In some optional implementations of this embodiment, based on a preset configuration file, in response to determining that the preset configuration file indicates that the target CPU core is not a master core, the execution entity can determine that the target CPU core is a slave core.

[0050] Based on the above optional implementation methods, this solution can directly confirm the role of the target CPU core as a slave core when the preset configuration file indicates that the target CPU core is not the master core, thereby improving the efficiency of confirming the role of the target CPU core.

[0051] In some optional implementations of this embodiment, in response to determining that the role is a slave core and receiving a confirmation signal from the master core, the aforementioned execution entity may also reply with a response confirmation message.

[0052] In these implementations, the aforementioned master core acknowledgment signal can be used to notify the master core of its existence. The aforementioned response acknowledgment information can be used to indicate that the slave core acknowledges the existence of the master core.

[0053] Based on the above-mentioned optional implementation methods, this solution can confirm the master core by sending response confirmation information corresponding to the received master core confirmation signal from the slave core, thereby helping to improve the accuracy of master core determination.

[0054] In some optional implementations of this embodiment, in response to determining that the role is a slave core, the aforementioned execution entity can also perform a flashing operation based on the flashing instruction received through inter-core communication.

[0055] In these implementations, in response to the determination that the role is a slave core, the aforementioned execution entity can perform a flashing operation by receiving a flashing instruction sent by the master core through inter-core communication, thereby completing its own upgrade.

[0056] As an example of these implementations, the flashing command described above may include the complete upgrade package. As yet another example, the flashing command may include the upgrade file parsed by the main kernel; this is not a limitation here.

[0057] In some optional implementations of this embodiment, in response to determining that the role is the master core, the aforementioned execution entity may also send a flashing instruction to the CPU core on the SOC whose role is the slave core through inter-core communication based on the detected upgrade instruction from outside the SOC.

[0058] In these implementations, the upgrade instructions from outside the SOC can be the same as described above, and will not be repeated here. The flashing instructions can include a complete upgrade compressed package or an upgrade file parsed by the main core; this is not limited here.

[0059] Based on the above optional implementation methods, this solution can realize the master core to flash and upgrade the slave core through inter-core communication.

[0060] In some optional implementations of this embodiment, the upgrade instructions from outside the SOC can be used to instruct the vehicle software system to be upgraded.

[0061] In these implementations, the aforementioned SOC may include a multi-core controller for the vehicle. The upgrade instructions from outside the SOC may be instructions issued by a server connected via a communication link, instructing the vehicle's software system to be upgraded.

[0062] Based on the above-mentioned optional implementation methods, this solution can be applied to the vehicle infotainment system, thereby improving the reliability of multi-core SOC flashing, reducing maintenance costs, and thus improving the system upgrade reliability of vehicles with multi-core SOC controllers.

[0063] In some optional implementations of this embodiment, the execution entity may further perform the following steps:

[0064] The first step is to check if the preset configuration file has been updated.

[0065] In these implementations, the execution entity can detect whether the preset configuration file has been updated in various ways. For example, the execution entity can detect whether the preset configuration file has been updated using file modification time, file size, file identifier (e.g., MD5 checksum), etc.

[0066] The second step is to reread the updated configuration file in response to the detection of a preset configuration file update.

[0067] The third step is to determine the role of the target CPU core based on the updated configuration file.

[0068] In these implementations, the execution entity can refer to the method described in step S102 and its optional implementations above, and replace the "preset configuration file" with the "updated configuration file" to determine the role of the target CPU core.

[0069] Based on the above optional implementation methods, this solution can update the roles of the master core and slave core by modifying the configuration file, thereby improving the usability of the system.

[0070] In some optional implementations of this embodiment, in response to receiving an arbitration result indicating that the target CPU core is the master core, the execution entity may also determine that the current role of the target CPU core is the master core.

[0071] In these implementations, the arbitration result can be generated through an arbitration method involving at least two CPU cores on the aforementioned SOC.

[0072] Based on the above-mentioned optional implementation methods, this solution can also reselect the main core through arbitration in the event of a missing main core, thereby improving the reliability of the entire SOC system.

[0073] See also Figure 2 , Figure 2 This is a schematic diagram 200 according to a second embodiment of the present disclosure. The method for system-on-chip upgrades, applied to a target CPU core on a System-on-Chip (SoC) containing at least two CPU cores, specifically includes the following steps:

[0074] S201, Read the preset configuration file.

[0075] S202 determines the role of the target CPU core based on a preset configuration file.

[0076] S203, depending on the determined role, perform one of the following two actions: in response to determining the role as the master core, perform master core flashing according to the detected upgrade command from outside the SOC; in response to determining the role as the slave core, stop communication with outside the SOC.

[0077] The above S201, S202, and S203 can be consistent with S101, S102, and S103 and their optional implementations in the foregoing embodiments, respectively. The description of S101, S102, and S103 and their optional implementations above also applies to S201, S202, and S203, and will not be repeated here.

[0078] S204, in response to determining the role as the primary core, determines whether the target CPU core can be upgraded via external communication.

[0079] In this embodiment, in response to determining the role as the main core, the execution entity of the method for system-on-chip upgrade (e.g., the target CPU core on a SoC containing at least two CPU cores) can determine in various ways whether the target CPU core can be used for upgrade via external communication.

[0080] In this embodiment, as an example, the aforementioned execution entity can detect whether it is possible to use relevant modules to control the upgrade of the aforementioned SOC based on the upgrade instructions obtained from external communication.

[0081] It should be noted that the aforementioned execution entity can be the target CPU core. The aforementioned SoC can contain at least two CPU cores. The aforementioned target CPU core can be one of the aforementioned at least two CPU cores.

[0082] S205, in response to determining that the target CPU core cannot be upgraded via external communication, updates the target CPU core's role to slave core.

[0083] In this embodiment, in response to step S204 above determining that the target CPU core cannot be upgraded via external communication, the execution entity can update the role of the target CPU core to a slave core.

[0084] In some optional implementations of this embodiment, the execution entity may determine whether the target CPU core can be upgraded via external communication by following these steps:

[0085] S2041, detects the communication status with external devices of the SOC.

[0086] In these implementations, the execution entity can detect the communication status with the external device of the SOC in various ways. For example, the execution entity can test the communication status between the target CPU core and the external device of the SOC using the ping (Packet Internet Groper) command. Then, the execution entity can determine whether the target CPU core can be upgraded via external communication based on the communication status. For example, when the execution entity determines that the connection is normal (e.g., the connection speed is within a preset range), it can determine that the target CPU core can be upgraded via external communication.

[0087] S2042, in response to determining that the external communication status is abnormal, it is determined that the target CPU core cannot be upgraded via external communication.

[0088] In these implementations, in response to determining that the external communication status is abnormal (e.g., connection is broken or connection is poor), the aforementioned execution entity can determine that the target CPU core cannot be upgraded via external communication.

[0089] Based on the above optional implementation methods, this solution can determine whether the target CPU core can be upgraded through external communication based on the detected communication status between the target CPU core and the SOC external device.

[0090] In some optional implementations of this embodiment, in response to determining that the role is the master core, the aforementioned execution entity may also send a flashing instruction to the CPU core on the SOC whose role is the slave core through inter-core communication based on the detected upgrade instruction from outside the SOC.

[0091] In these implementations, the upgrade instructions from outside the SOC can be the same as described above, and will not be repeated here. The flashing instructions can include a complete upgrade compressed package or an upgrade file parsed by the main core; this is not limited here.

[0092] Based on the above optional implementation methods, this solution can realize the master core to flash and upgrade the slave core through inter-core communication.

[0093] In some optional implementations of this embodiment, the upgrade instructions from outside the SOC can be used to instruct the vehicle software system to be upgraded.

[0094] In these implementations, the aforementioned SOC may include a multi-core controller for the vehicle. The upgrade instructions from outside the SOC may be instructions issued by a server connected via a communication link, instructing the vehicle's software system to be upgraded.

[0095] Based on the above-mentioned optional implementation methods, this solution can be applied to the vehicle infotainment system, thereby improving the reliability of multi-core SOC flashing, reducing maintenance costs, and thus improving the system upgrade reliability of vehicles with multi-core SOC controllers.

[0096] In some optional implementations of this embodiment, the execution entity may further perform the following steps:

[0097] The first step is to check if the preset configuration file has been updated.

[0098] In these implementations, the execution entity can detect whether the preset configuration file has been updated in various ways. For example, the execution entity can detect whether the preset configuration file has been updated using file modification time, file size, file identifier (e.g., MD5 checksum), etc.

[0099] The second step is to reread the updated configuration file in response to the detection of a preset configuration file update.

[0100] The third step is to determine the role of the target CPU core based on the updated configuration file.

[0101] In these implementations, the execution entity can refer to the method described in step S102 and its optional implementations above, and replace the "preset configuration file" with the "updated configuration file" to determine the role of the target CPU core.

[0102] Based on the above optional implementation methods, this solution can update the roles of the master core and slave core by modifying the configuration file, thereby improving the usability of the system.

[0103] In some optional implementations of this embodiment, in response to receiving an arbitration result indicating that the target CPU core is the master core, the execution entity may also determine that the current role of the target CPU core is the master core.

[0104] In these implementations, the arbitration result can be generated through an arbitration method involving at least two CPU cores on the aforementioned SOC.

[0105] Based on the above-mentioned optional implementation methods, this solution can also reselect the main core through arbitration in the event of a missing main core, thereby improving the reliability of the entire SOC system.

[0106] from Figure 2 As can be seen from the diagram, the process 200 of the method for upgrading a system-on-a-chip in this embodiment embodies the steps of determining whether the target CPU core can be upgraded via external communication in response to determining that the target CPU core's role is the master core, and updating the target CPU core's role to a slave core in response to determining that the target CPU core cannot be upgraded via external communication. Therefore, the solution described in this embodiment can promptly switch the original master core to a slave core when the master core cannot be upgraded via external communication, so that the master core with the updated role can continue to be upgraded via external communication, thereby ensuring the reliability of the entire SOC system upgrade.

[0107] See also Figure 3 , Figure 3 This is a schematic diagram illustrating an application scenario of a method for system-on-chip upgrades according to embodiments of the present disclosure. Figure 3 In the application scenario, a vehicle 301 with assisted driving functions may include a system-on-a-chip (SoC) 3011. The SoC 3011 may include CPU1 and CPU2. CPU1 and CPU2 can exchange information via inter-core communication. CPU1 and CPU2 can each read a preset configuration file 3012. Based on the preset configuration file 3012, CPU1 and CPU2 can determine their respective roles, for example, CPU1 is the master core and CPU2 is the slave core. In response to determining its role as the master core, CPU1 can perform a master core rewrite based on an upgrade command 303 detected from an external backend server 302. In response to determining its role as the slave core, CPU2 stops communication with the external system-on-a-chip, for example, disconnecting the communication connection, thus preventing it from receiving upgrade commands 303 from the external backend server 302.

[0108] Currently, one common technology employs a heterogeneous multi-core architecture, where a single master core interacts with the outside world and updates other slave cores. This results in a fixed master-slave structure, with updates only occurring from the master core to the slave cores. Consequently, a failure in the master core can affect the entire on-chip system, causing communication failures or preventing upgrades. The method provided in the embodiments of this disclosure, however, allows each CPU core of the on-chip system to read a preset configuration file and determine its role as either master or slave. This allows the CPU core designated as master to handle external communication and upgrades, achieving dynamic determination of master and slave roles and providing a foundation for ensuring the reliability of the entire on-chip system upgrade.

[0109] Further reference Figure 4As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of an apparatus for system-on-chip upgrades, applied to a target CPU core on a System-on-Chip (SoC) containing at least two CPU cores. This apparatus embodiment is similar to... Figure 1 or Figure 2 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0110] like Figure 4 As shown, the apparatus 400 for system-on-chip upgrades, applied to a target CPU core on a System-on-Chip (SoC) containing at least two CPU cores, provided in this embodiment, includes a reading unit 401, a determining unit 402, and an execution unit 403. The reading unit 401 is configured to read a preset configuration file; the determining unit 402 is configured to determine the role of the target CPU core based on the preset configuration file, wherein the role includes a master core or a slave core; the execution unit 403 is configured to perform one of the following actions based on the determined role: in response to determining the role as a master core, performing master core flashing according to detected upgrade instructions from outside the SoC; in response to determining the role as a slave core, stopping communication with outside the SoC.

[0111] In this embodiment, the specific processing of the reading unit 401, the determining unit 402, and the execution unit 403 in the device 400 for on-chip system upgrade, and the resulting technical effects, can be referred to respectively. Figure 1 The relevant descriptions of steps S101, S102, and S103 in the corresponding embodiments will not be repeated here.

[0112] In some optional implementations of this embodiment, the determining unit 402 may include: a sending module (not shown in the figure), configured to send a master core confirmation signal to other CPU cores on the SOC via inter-core communication in response to determining that a preset configuration file indicates the target CPU core's role as a master core; and a determining module (not shown in the figure), configured to determine the role of the target CPU core based on the received response confirmation information corresponding to the master core confirmation signal. The master core confirmation signal can be used to notify the existence of a master core.

[0113] In some optional implementations of this embodiment, the determining module may include: a verification submodule (not shown in the figure), configured to perform a second verification according to a preset configuration file in response to receiving a response confirmation information corresponding to the main core confirmation signal; and a determining submodule (not shown in the figure), configured to determine the role of the target CPU core based on the result of the second verification according to the preset configuration file.

[0114] In some optional implementations of this embodiment, the aforementioned determining submodule can be further configured to: determine the target CPU core as a main core in response to the result of the re-verification based on the preset configuration file indicating that the target CPU core is a main core; and determine the target CPU core as a slave core in response to the result of the re-verification based on the preset configuration file indicating that the target CPU core is not a main core.

[0115] In some optional implementations of this embodiment, the determining unit 402 can be further configured to: determine the role of the target CPU core as a slave core in response to determining that the preset configuration file indicates that the target CPU core is not a master core.

[0116] In some optional implementations of this embodiment, the apparatus 400 for on-chip system upgrade may further include: a response unit (not shown in the figure), configured to respond to a response confirmation message in response to determining that the role is a slave core and receiving a master core confirmation signal. The master core confirmation signal can be used to notify that a master core exists.

[0117] In some optional implementations of this embodiment, the apparatus 400 for system-on-chip upgrade may further include: a flashing unit (not shown in the figure), configured to flash according to a flashing instruction received through inter-core communication in response to determining that the role is a slave core.

[0118] In some optional implementations of this embodiment, the apparatus 400 for upgrading a system-on-a-chip may further include: an upgrade confirmation unit (not shown in the figure), configured to determine whether the target CPU core can be upgraded via external communication in response to determining that the target CPU core is a master core; and an update unit (not shown in the figure), configured to update the role of the target CPU core to a slave core in response to determining that the target CPU core cannot be upgraded via external communication.

[0119] In some optional implementations of this embodiment, the upgrade confirmation unit can be further configured to: detect the communication status with external devices of the SOC; and in response to determining that the external communication status is abnormal, determine that the target CPU core cannot be upgraded through external communication.

[0120] In some optional implementations of this embodiment, the apparatus 400 for system-on-chip upgrade may further include: a sending unit (not shown in the figure), configured to: in response to determining that the role is master core, send a flashing instruction to the CPU core on the SOC whose role is slave core via inter-core communication according to the detected upgrade instruction from outside the SOC.

[0121] In some optional implementations of this embodiment, the upgrade instructions from outside the SOC can be used to instruct the vehicle software system to be upgraded.

[0122] In some optional implementations of this embodiment, the device 400 for system-on-chip upgrade can be further configured to: detect whether a preset configuration file has been updated; in response to determining that the preset configuration file has been updated, reread the updated configuration file; and determine the role of the target CPU core based on the updated configuration file.

[0123] In some optional implementations of this embodiment, the apparatus 400 for system-on-chip upgrades may further include: a master core determination unit (not shown in the figure), configured to: determine the current role of the target CPU core as the master core in response to receiving an arbitration result indicating that the target CPU core is the master core. The arbitration result may be generated using an arbitration method involving at least two CPU cores on the SOC described above.

[0124] The apparatus provided in the above embodiments of this disclosure enables each CPU core of the on-chip system to read a preset configuration file through the reading unit 401, determines whether it is a master core or a slave core through the determining unit 402, and enables the CPU core acting as the master core to undertake the functions of external communication and upgrade through the execution unit 403, while the CPU core acting as the slave core stops external communication. This realizes the dynamic determination of the master core and slave core roles, providing a basis for ensuring the reliability of the entire on-chip system upgrade.

[0125] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0126] According to embodiments of this disclosure, this disclosure also provides a system-on-a-chip, a readable storage medium, a computer program product, an autonomous vehicle, and a roadside device.

[0127] Figure 5 A schematic block diagram of an example system-on-a-chip 500 that can be used to implement embodiments of the present disclosure is shown. The system-on-a-chip 500 can be installed in various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0128] The autonomous vehicles provided in this disclosure may include, for example, Figure 5 The above-described system-on-a-chip 500 is shown.

[0129] The roadside equipment provided in this disclosure includes, in addition to, the following: Figure 5 The system-on-chip 500 shown above may also include communication components, etc. The system-on-chip 500 can be integrated with the communication components or they can be set separately. The system-on-chip 500 can acquire data from sensing devices (such as roadside cameras), such as images and videos, and then perform image and video processing and data calculations.

[0130] like Figure 5 As shown, the system-on-a-chip 500 includes a computing unit 501, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. The RAM 503 may also store various programs and data required for the operation of the device 500. The computing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0131] Multiple components in device 500 are connected to I / O interface 505, including: input unit 506, such as keyboard, mouse, etc.; output unit 507, such as various types of monitors, speakers, etc.; storage unit 508, such as disk, optical disk, etc.; and communication unit 509, such as network card, modem, wireless transceiver, etc. Communication unit 509 allows device 500 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0132] The computing unit 501 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the various methods and processes described above, such as methods for system-on-chip upgrades. For example, in some embodiments, the methods for system-on-chip upgrades may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by the computing unit 501, one or more steps of the methods for system-on-chip upgrades described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform methods for system-on-chip upgrades by any other suitable means (e.g., by means of firmware).

[0133] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0134] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0135] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0136] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0137] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0138] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0139] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0140] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for upgrading a System-on-a-Chip (SOC), applied to a target CPU core, the SOC comprising at least two CPU cores, the target CPU core being one of the at least two CPU cores, comprising: Read the preset configuration file; Based on the preset configuration file, the role of the target CPU core is determined, wherein the role includes a master core or a slave core, including: in response to determining that the preset configuration file indicates that the target CPU core is a master core, sending a master core confirmation signal to other CPU cores on the SOC via inter-core communication, wherein the master core confirmation signal is used to notify that a master core exists; and determining the role of the target CPU core based on the response confirmation information received corresponding to the master core confirmation signal. Based on the determined role, perform one of the following: in response to determining that the role is the master core, perform master core flashing according to the detected upgrade command from outside the SOC; in response to determining that the role is the slave core, stop communication with outside the SOC.

2. The method according to claim 1, wherein, The step of determining the role of the target CPU core based on the received response confirmation information corresponding to the main core confirmation signal includes: In response to receiving the response confirmation information corresponding to the main core confirmation signal, a second verification is performed according to the preset configuration file; The role of the target CPU core is determined based on the result of a second verification using the preset configuration file.

3. The method according to claim 2, wherein, The step of determining the role of the target CPU core based on the result of the re-verification according to the preset configuration file includes: In response to the result of the re-verification based on the preset configuration file indicating that the target CPU core is a master core, the role of the target CPU core is determined to be a master core; In response to the result of the re-verification based on the preset configuration file indicating that the target CPU core is not a master core, the target CPU core is determined to be a slave core.

4. The method according to claim 1, wherein, The process of determining the role of the target CPU core based on the preset configuration file includes: In response to determining that the preset configuration file indicates that the target CPU core is not a master core, the target CPU core is determined to be a slave core.

5. The method according to any one of claims 1-4, wherein, The method further includes: In response to determining that the role is a slave core and receiving a master core confirmation signal, a response confirmation message is sent, wherein the master core confirmation signal is used to notify that a master core exists.

6. The method according to claim 1, wherein, The method further includes: In response to determining that the role is a slave core, a flashing operation is performed according to the flashing command received through inter-core communication.

7. The method according to any one of claims 1-4, wherein, The method further includes: In response to determining that the role is the main core, it is determined whether the target CPU core can be upgraded via external communication; In response to the determination that the target CPU core cannot be upgraded via external communication, the role of the target CPU core is updated to that of a slave core.

8. The method according to claim 7, wherein, The determination of whether the target CPU core can be upgraded via external communication includes: Detect the communication status with the outside of the SOC; In response to determining that the communication status is abnormal, it is determined that the target CPU core cannot be upgraded via external communication.

9. The method according to claim 1, wherein, The method further includes: In response to determining that the role is the master core, based on the detected upgrade command from outside the SOC, a flash command is sent to the CPU core on the SOC whose role is the slave core via inter-core communication.

10. The method according to claim 1, wherein, The upgrade command from outside the SOC is used to instruct the vehicle software system to be upgraded.

11. The method according to claim 1, wherein, The method further includes: Check whether the preset configuration file has been updated; In response to the determination that the preset configuration file has been updated, the updated configuration file is reread; Based on the updated configuration file, the role of the target CPU core is determined.

12. The method according to claim 1, wherein, The method further includes: In response to receiving an arbitration result indicating that the target CPU core is a master core, the current role of the target CPU core is determined to be a master core, wherein the arbitration result is generated by an arbitration method involving at least two CPU cores on the SOC.

13. An apparatus for upgrading a system-on-a-chip (SoC), applied to a target central processing unit (CPU) core, the SoC comprising at least two CPU cores, the target CPU core being one of the at least two CPU cores, comprising: The read unit is configured to read a preset configuration file; The determining unit is configured to determine the role of the target CPU core based on the preset configuration file, wherein the role includes a master core or a slave core; The execution unit is configured to perform one of the following based on the determined role: in response to determining that the role is the master core, perform master core flashing according to the detected upgrade instructions from outside the SOC; in response to determining that the role is the slave core, stop communication with outside the SOC. The determining unit includes: a sending module configured to, in response to determining that the preset configuration file indicates the target CPU core's role as a master core, send a master core confirmation signal to other CPU cores on the SOC via inter-core communication, wherein the master core confirmation signal is used to notify that a master core exists; and a determining module configured to determine the role of the target CPU core based on the received response confirmation information corresponding to the master core confirmation signal.

14. A system-on-a-chip (SoC), comprising: At least two isomorphic CPU cores, wherein the at least two isomorphic CPU cores include a CPU core as the master core and at least one CPU core as the slave core; and A memory communicatively connected to the at least two isomorphic CPU cores; wherein, The memory stores instructions that can be executed by the at least two isomorphic CPU cores, the instructions being executed by at least one CPU core to enable the at least one CPU core to perform the method of any one of claims 1-12.

15. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-12.

16. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-12.

17. An autonomous vehicle comprising a System-on-Chip (SOC) as described in claim 14.

18. A roadside device comprising a System-on-Chip (SOC) as described in claim 14.

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