Chip real-time detection method and device, chip and storage medium

Abstract

The application discloses a kind of real-time detection method, device and chip of chip, storage medium, the method includes: when receiving any detection circuit sends alarm signal, first check algorithm and second check algorithm are used respectively to check signal and obtain first check signal and second check signal, the detection circuit is correspondingly set with each module of the chip;When the first check signal and the second check signal fail to compare, the chip is triggered to reset operation or self-destruction operation;By using first check algorithm and second check algorithm to check signal and carry out check operation, and the state of different check signals is compared, when state is inconsistent, it is determined that alarm signal is attacked, and alarm signal is fed back to application, with the effect of resisting multi-point fault attack.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a real-time detection method, apparatus, chip, and storage medium for chips. Background Technology

[0002] As attack techniques develop and mature, critical data stored in chips poses security risks. For example, attackers can indirectly obtain or alter chip operating environment parameters or sensitive data using methods such as fault injection (e.g., heavy ion radiation, electromagnetic interference, power supply interference), threatening the stable operation of the power grid. For chips used in the power grid, if unauthorized individuals obtain sensitive data within the chip through some means, it could lead to security vulnerabilities such as the power grid malfunctioning.

[0003] Currently, there are many security design methods for chip protection and detection circuits, such as glitch signal detection and self-destruct circuits. Most of these designs aim to detect attacks. With the development of attack techniques, multi-point fault attack techniques have become mature. This means that when a chip is attacked, its alarm signal will be attacked simultaneously, preventing the chip from feeding back the alarm signal to the application or performing self-destruction operations, even if it detects the attack, thus giving attackers further opportunities to attack.

[0004] The defects of the related technologies are: (1) they can only partially detect or cannot guarantee that the alarm signal will be correctly fed back after the attack is detected, that is, they cannot resist multi-point fault injection attacks; (2) they cannot effectively detect the chip status and accurately handle the alarm signal problem, and they have not designed for false alarms. Summary of the Invention

[0005] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the object of this invention is to propose a real-time detection method for chips that can resist multi-point fault attacks.

[0006] Therefore, embodiments of the present invention provide a real-time detection method for a chip, wherein each module of the chip is provided with a detection circuit, and the method includes:

[0007] When an alarm signal is received from any detection circuit, the alarm signal is verified using the first verification algorithm and the second verification algorithm respectively to obtain the first verification signal and the second verification signal.

[0008] When the comparison between the first verification signal and the second verification signal fails, the chip is triggered to perform a reset operation or a self-destruct operation.

[0009] Furthermore, the detection circuit includes at least one of a memory verification and protection circuit, an algorithm self-test circuit, an environment detection circuit, a random number self-test circuit, and a mode switching protection circuit.

[0010] Furthermore, the method further includes: when receiving alarm signals sent by multiple detection circuits, summarizing the alarm signals sent by each detection circuit so as to verify each alarm signal separately.

[0011] Furthermore, the method also includes:

[0012] The alarm signal is sampled for n consecutive cycles to obtain the signal within n cycles;

[0013] Determine whether all signals within the n periods are valid signals;

[0014] If so, the alarm signal is determined to be a valid alarm signal;

[0015] If not, the alarm signal is determined to be an invalid alarm signal;

[0016] Specifically, when the alarm signal is determined to be a valid alarm signal, the first verification algorithm and the second verification algorithm are used to perform verification operations on the valid alarm signal.

[0017] Furthermore, the valid signal is a high-level signal or a low-level signal.

[0018] Furthermore, the method also includes:

[0019] Determine whether the alarm signal is received continuously within a set time period;

[0020] If so, the alarm signal is determined to be a non-false alarm signal;

[0021] If not, the alarm signal is determined to be a false alarm signal;

[0022] When the alarm signal is a non-false alarm signal, the first verification algorithm and the second verification algorithm are used to perform verification operations on the non-false alarm signal.

[0023] Furthermore, the reset operation includes power-on / power-off reset of the chip and reset of the non-power-on reset register.

[0024] Furthermore, the method also includes:

[0025] The alarm signal that triggers the non-power-on reset register reset is stored so that it can be retrieved by the CPU after the chip reset is completed.

[0026] Furthermore, to achieve the above objectives, embodiments of the present invention provide a real-time detection device for a chip, wherein each module of the chip is provided with a detection circuit, and the device includes:

[0027] The verification module is used to perform verification operations on the alarm signal by using a first verification algorithm and a second verification algorithm respectively when receiving an alarm signal sent by any detection circuit, so as to obtain a first verification signal and a second verification signal.

[0028] The comparison module is used to send a trigger command to the reset module when the comparison between the first verification signal and the second verification signal fails, so that the reset module performs a reset operation or a self-destruct operation on the chip.

[0029] Furthermore, the detection circuit includes at least one of a memory verification and protection circuit, an algorithm self-test circuit, an environment detection circuit, a random number self-test circuit, and a mode switching protection circuit.

[0030] Furthermore, it also includes:

[0031] The safety control management module is used to summarize the alarm signals sent by each of the multiple detection circuits when it receives alarm signals sent by multiple detection circuits, and send the summarized alarm signals to the verification module.

[0032] Furthermore, the device also includes:

[0033] A signal sampling unit is used to sample the alarm signal for n consecutive cycles to obtain the signal within n cycles;

[0034] The first judgment unit is used to determine whether the signals within the n periods are all valid signals, wherein the valid signals are either high-level signals or low-level signals;

[0035] The first determining unit is configured to determine that the alarm signal is a valid alarm signal when the output result of the determining unit is yes, and to determine that the alarm signal is an invalid alarm signal when the output result of the determining unit is no.

[0036] The verification module is used to perform verification calculations on the valid alarm signals.

[0037] Furthermore, the device also includes:

[0038] The second judgment unit is used to determine whether the alarm signal is continuously received within a set time period;

[0039] The second determining unit is used to determine that the alarm signal is a false alarm signal when the output result of the second determining unit is negative, and to determine that the alarm signal is a non-false alarm signal when the output result of the second determining unit is positive.

[0040] The verification module is used to perform verification operations on the non-false alarm signals.

[0041] Furthermore, the reset module includes:

[0042] The first reset unit is used to trigger the chip to perform a power-on reset when the chip is powered on / off.

[0043] The second reset unit is used to trigger the non-power-on reset register to reset when the comparison between the first verification signal and the second verification signal fails.

[0044] Furthermore, the device also includes:

[0045] An alarm source storage module is used to store the alarm signal that triggers the reset of the non-power-on reset register, so that the CPU can retrieve it after the chip reset is completed.

[0046] In addition, to achieve the above objectives, embodiments of the present invention provide a chip, which includes the apparatus described above.

[0047] In addition, to achieve the above objectives, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method described above.

[0048] The real-time chip detection method provided in this invention, upon receiving an alarm signal from a detection circuit corresponding to any module of the chip, performs verification operations on the alarm signal using a first verification algorithm and a second verification algorithm to obtain a first verification signal and a second verification signal. If the comparison between the first verification signal and the second verification signal fails, the chip is triggered to perform a reset operation or a self-destruct operation. By splitting the alarm signal sent by any detection circuit into two paths and verifying them separately to generate two verification signals, the two verification signals are compared. When the state of either verification signal is an alarm state, the chip is triggered to perform a reset operation or a self-destruct operation. Since it is almost impossible for the chip to be attacked and both alarm signals to be attacked simultaneously, even if the chip is attacked and one alarm signal is attacked simultaneously, it can still ensure that the alarm signal is correctly fed back for application or that the chip self-destructs, thus resisting multi-point fault attacks. Attached Figure Description

[0049] Figure 1 This is a flowchart of the real-time detection method for the chip in the first embodiment of the present invention;

[0050] Figure 2 This is a flowchart of the real-time detection method for the chip in the second embodiment of the present invention;

[0051] Figure 3 This is a structural block diagram of the real-time chip detection device in the third embodiment of the present invention;

[0052] Figure 4This is a structural block diagram of the real-time chip detection device in the fourth embodiment of the present invention. Detailed Implementation

[0053] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0054] The following is a reference appendix. Figure 1 This invention describes a real-time detection method for a chip, wherein each module of the chip is equipped with a detection circuit, and includes the following steps:

[0055] S10. When an alarm signal is received from any detection circuit, the alarm signal is verified by the first verification algorithm and the second verification algorithm respectively to obtain the first verification signal and the second verification signal.

[0056] It should be noted that the verification algorithm used in this embodiment can be an existing verification algorithm, such as SM3, CRC and other verification algorithms. The first verification algorithm and the second verification algorithm can be the same or different. This embodiment does not make specific limitations.

[0057] It should be noted that after the verification algorithm is used to verify the alarm signal, the verification signal is output and latched. If the CPU does not clear the verification signal status, but the calculation result shows an attacked status, it is considered that the alarm status of the verification signal has been tampered with.

[0058] S20. When the comparison between the first verification signal and the second verification signal fails, the chip is triggered to perform a reset operation or a self-destruct operation.

[0059] It should be noted that in this embodiment, the states of the first verification signal and the second verification signal include a safe state and an alarm state. The failure to match the first verification signal and the second verification signal means that at least one of the first verification signal and the second verification signal is in an alarm state.

[0060] This embodiment divides the alarm signal sent by the detection circuit into two paths for verification. The two verification signals are compared, and when either verification signal is in an alarm state, the chip is triggered to perform a reset or self-destruct operation. Since it is almost impossible for the chip to be attacked and both alarm signals to be attacked at the same time, even if the chip is attacked and one alarm signal is attacked at the same time, the alarm signal can still be correctly fed back to the application or the chip can be self-destructed. This can resist multi-point fault attacks.

[0061] Furthermore, the detection circuit includes at least one of a memory verification and protection circuit, an algorithm self-test circuit, an environment detection circuit, a random number self-test circuit, and a mode switching protection circuit.

[0062] Furthermore, the method also includes the following steps:

[0063] When multiple alarm signals are received from the detection circuits, the alarm signals sent by each detection circuit are summarized so that each alarm signal can be verified separately.

[0064] It should be noted that since there are various alarm signals received from different detection circuits, and different alarm signals are processed in different ways, it is necessary to summarize and process the alarm signals sent by the same detection module to ensure the accuracy of alarm signal processing.

[0065] Furthermore, the method also includes:

[0066] The alarm signals sent by the multiple detection circuits are stored.

[0067] It should be noted that this embodiment stores the alarm signal to avoid the inability to perform verification calculations on the alarm signal due to its short duration.

[0068] For example, when a memory module is equipped with a verification protection circuit and is attacked, the verification protection circuit will output a verification error alarm signal. After summarizing, the alarm signal with the verification error is verified using the first verification algorithm and the second verification algorithm to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are compared. When the state of any verification signal is alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0069] If a self-test circuit is added to the algorithm module, when the self-test circuit fails to self-test, it outputs an alarm signal indicating that the algorithm has failed to self-test. After summarizing, the alarm signal indicating that the algorithm has failed to self-test is verified by the first verification algorithm and the second verification algorithm to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are then compared. When the state of any verification signal is an alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0070] If a random number is added to the self-test circuit, when the self-test circuit fails, it outputs an alarm signal indicating that the random number self-test has failed to the safety control management unit. After summarizing, the alarm signal indicating that the random number self-test has failed is verified using the first verification algorithm and the second verification algorithm to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are then compared. When the state of any verification signal is alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0071] If the chip has an environmental safety detection circuit, such as a temperature detection circuit, it will output an over-temperature alarm signal when the temperature exceeds the design range. After summarizing, the over-temperature alarm signal is verified by the first verification algorithm and the second verification algorithm to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are compared. When the state of any verification signal is alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0072] If a mode switching protection circuit is set in the chip, an alarm signal for illegal mode switching will be output when the mode is illegally switched. After being summarized, the alarm signal for illegal mode switching is verified by the first verification algorithm and the second verification algorithm to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are compared. When the state of any verification signal is alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0073] In one embodiment, reference is made to Figure 2 Based on the first embodiment, a second embodiment of the real-time detection method for the chip of the present invention is proposed, the method further comprising the following steps:

[0074] S101. Upon receiving an alarm signal from any detection circuit, the alarm signal is sampled for n consecutive cycles to obtain the signal within the n cycles.

[0075] It should be noted that in this embodiment, the value of n is 3. Considering that glitches may occur during the signal generation process, the alarm signal is sampled for 3 consecutive clock cycles to achieve filtering.

[0076] It is understood that those skilled in the art can set the number of sampling periods set in this embodiment according to the actual situation, and this embodiment does not make specific limitations.

[0077] S102. Determine whether all signals within the n periods are valid signals. If yes, proceed to step S103; otherwise, proceed to step S104.

[0078] S103. Determine that the alarm signal is a valid alarm signal;

[0079] S104. Determine that the alarm signal is an invalid alarm signal;

[0080] S105. When the alarm signal is determined to be a valid alarm signal, the first verification algorithm and the second verification algorithm are used to perform verification operations on the valid alarm signal.

[0081] It is understandable that if the alarm signal is determined to be invalid, no further verification or calculation will be performed.

[0082] It should be noted that the verification algorithm used in this embodiment can be an existing verification algorithm, such as SM3, CRC and other verification algorithms. The first verification algorithm and the second verification algorithm can be the same or different. This embodiment does not make specific limitations.

[0083] Furthermore, the valid signal is a high-level signal or a low-level signal.

[0084] This embodiment splits the alarm signal sent by the detection circuit into two channels for verification. The two verification signals are compared, and if either verification signal is in an alarm state, the chip is triggered to reset or self-destruct. Since it is nearly impossible for the chip to be attacked simultaneously with both alarm signals, even if the chip is attacked and one alarm signal is attacked simultaneously, the system can still ensure that the alarm signal is correctly fed back to the application or that the chip self-destructs, thus resisting multi-point fault attacks. Simultaneously, by setting the alarm signal to be active high or low, and sampling the alarm signal for three consecutive clock cycles, with the signal remaining high or low throughout all three clock cycles, the alarm signal is considered valid. Verification calculations are then performed on valid alarm signals to ensure the accuracy and effectiveness of chip status detection.

[0085] Furthermore, the method also includes the following steps:

[0086] Determine whether the alarm signal is received continuously within a set time period;

[0087] If so, the alarm signal is determined to be a non-false alarm signal;

[0088] If not, the alarm signal is determined to be a false alarm signal;

[0089] When the alarm signal is a non-false alarm signal, the first verification algorithm and the second verification algorithm are used to perform verification operations on the non-false alarm signal.

[0090] It is understood that those skilled in the art can set the time according to actual needs, such as 3 to 30 times the clock cycle, and this embodiment does not make specific limitations.

[0091] Understandably, if the alarm signal is determined to be a false alarm, no further verification or calculation will be performed.

[0092] It should be noted that since the current environmental detection circuits are all implemented using analog circuits, false alarm signals may be generated from the time the environmental detection circuit is turned on until the environmental monitoring circuit is working stably. This embodiment eliminates false alarm signals by judging whether an alarm signal is received within a set time, thereby ensuring the accuracy of the alarm signal and guaranteeing the effectiveness of the verification operation.

[0093] It should be noted that when the memory module is equipped with a verification protection circuit and is attacked, the verification protection circuit will output an alarm signal for verification error. After summarizing, filtering and eliminating false alarms, the first verification algorithm and the second verification algorithm are used to perform verification operations on the valid non-false alarm signals to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are compared. When the state of any verification signal is an alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0094] If a self-test circuit is added to the algorithm module, when the self-test circuit fails to self-test, it outputs an alarm signal indicating that the algorithm has failed to self-test. After summarizing, filtering, and eliminating false alarms, the first and second verification algorithms are used to verify the valid non-false alarm signals to obtain the first and second verification signals. The first and second verification signals are then compared. When the state of any verification signal is an alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0095] If a random number is added to the self-test circuit, when the self-test circuit fails, it outputs an alarm signal indicating that the random number self-test has failed to the safety control and management unit. After summarizing, filtering, and eliminating false alarms, the first and second verification algorithms are used to verify the valid non-false alarm signals to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are then compared. When the state of any verification signal is an alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0096] If the chip has an environmental safety detection circuit, such as a temperature detection circuit, it will output an overheat alarm signal when the detected temperature exceeds the design range. After summarizing, filtering and eliminating false alarms, the first and second verification algorithms are used to verify the valid non-false alarm signals to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are compared. When the state of any verification signal is an alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0097] If a mode switching protection circuit is set in the chip, an alarm signal for illegal mode switching will be output when the mode is illegally switched. After summarizing, filtering and eliminating false alarms, the first and second verification algorithms are used to verify the valid non-false alarm signals to obtain the first verification signal and the second verification signal. The first verification signal and the second verification signal are compared. When the state of any verification signal is alarm state, the chip is triggered to perform a reset or self-destruct operation.

[0098] In one embodiment, the reset operation includes power-on / power-off reset of the chip and reset of the non-power-on reset register.

[0099] It should be noted that if the states of the two verification signals are found to be inconsistent during comparison, it is determined that the alarm signal has been attacked, triggering the chip to perform a reset or self-destruct operation. There are two reset methods depending on the reset source: one is a system-triggered reset method, which only resets when the chip is powered on / off; the other is a reset method triggered when the alarm signal is attacked, which resets all non-power-on reset registers, such as sensitive parameter registers.

[0100] In one embodiment, the method further includes the following steps:

[0101] The alarm signal that triggers the reset of the non-power-on reset register is stored so that it can be retrieved by the CPU after the chip reset is completed.

[0102] It should be noted that in this embodiment, when the alarm signal is attacked, the alarm signal is stored. The specific storage module uses power-on reset. When the chip is reset after generating an alarm signal, the CPU can still obtain the alarm source signal after the chip reset is completed. The upper layer application can flexibly process data or perform self-destruction chip operation according to the alarm source signal.

[0103] It should be noted that the improvement of the real-time chip detection method provided in this embodiment compared with related technologies lies in:

[0104] (1) By using the first verification algorithm and the second verification algorithm to perform verification calculations on the alarm signal and comparing the states of different verification signals, the alarm signal is determined to be attacked when the states are inconsistent, and the alarm signal is fed back to the application. This has the effect of resisting multi-point fault attacks, while related technologies can only detect glitch attacks. When the attacker attacks the alarm signal of the glitch detection circuit again, it cannot return to the alarm state.

[0105] (2) By sampling the alarm signal for a continuous clock cycle and setting it to be active at high or low level, the validity of the alarm signal is confirmed. At the same time, the alarm signal is checked only after the set time is met, eliminating erroneous operations and providing an accurate alarm signal.

[0106] (3) By storing the alarm source signal and using the power-on reset of the storage module, even if the chip is reset, the upper layer application can still read the alarm source through the CPU to determine whether the chip has encountered a multi-point fault attack. It can take the self-destruction method to protect the data security in the chip. The chip using the real-time detection method of this embodiment has passed the Level 2 security test of the Commercial Confidentiality Testing Center.

[0107] In addition, refer to Figure 3 The third embodiment of the present invention also proposes a real-time detection device for a chip, wherein each module of the chip is provided with a detection circuit, and the device includes:

[0108] The verification module 10 is used to perform verification operations on the alarm signal by using a first verification algorithm and a second verification algorithm respectively when receiving an alarm signal sent by any detection circuit, so as to obtain a first verification signal and a second verification signal.

[0109] It should be noted that the verification module in this embodiment can be implemented using existing verification algorithms, such as SM3, CRC and other verification algorithms. The first verification algorithm and the second verification algorithm can be the same or different. This embodiment does not make specific limitations.

[0110] It should be noted that after the verification algorithm is used to verify the alarm signal, the verification signal is output and latched. If the CPU does not clear the verification signal status, but the calculation result shows an attacked status, it is considered that the alarm status of the verification signal has been tampered with.

[0111] The comparison module 20 is used to send a trigger command to the reset module when the comparison between the first verification signal and the second verification signal fails, so that the reset module 30 performs a reset operation or a self-destruct operation on the chip.

[0112] It should be noted that in this embodiment, the states of the first verification signal and the second verification signal include a safe state and an alarm state. The failure to match the first verification signal and the second verification signal means that at least one of the first verification signal and the second verification signal is in an alarm state, which confirms that the alarm signal has been attacked.

[0113] This embodiment verifies the alarm signal sent by the detection circuit by splitting it into two paths and comparing the two verification signals. When either verification signal is in an alarm state, the chip is triggered to perform a reset or self-destruct operation. Since it is almost impossible for the chip to be attacked and both alarm signals to be attacked at the same time, even if the chip is attacked and one alarm signal is attacked at the same time, the attack on the alarm signal is confirmed and the application is correctly fed back or the chip self-destructs. This can resist multi-point fault attacks.

[0114] Furthermore, the detection circuit includes at least one of a memory verification and protection circuit, an algorithm self-test circuit, an environment detection circuit, a random number self-test circuit, and a mode switching protection circuit.

[0115] Furthermore, the device also includes:

[0116] The safety control management module 40 is used to summarize the alarm signals sent by each of the multiple detection circuits when it receives alarm signals sent by multiple detection circuits, and send the summarized alarm signals to the verification module.

[0117] It should be noted that the safety control management module 40 can be used to protect the integrity of data sent by environmental detection circuits (such as power supply voltage, temperature, etc.) or memory verification protection circuits, such as protecting the use of detection circuits, alarm signals of detection circuits, etc., and summarizing and storing them.

[0118] In one embodiment, reference is made to Figure 4 Based on the third embodiment, a fourth embodiment of the real-time detection device for the chip of the present invention is proposed. The device includes a signal processing module 50, which includes:

[0119] A signal sampling unit is used to sample the alarm signal for n consecutive cycles to obtain the signal within n cycles;

[0120] It should be noted that in this embodiment, the value of n is 3. Considering that glitches may occur during the signal generation process, the alarm signal is sampled for 3 consecutive clock cycles to achieve filtering.

[0121] It is understood that those skilled in the art can set the number of sampling periods set in this embodiment according to the actual situation, and this embodiment does not make specific limitations.

[0122] The first judgment unit is used to determine whether the signals within the n periods are all valid signals, wherein the valid signals are either high-level signals or low-level signals;

[0123] The first determining unit is configured to determine that the alarm signal is a valid alarm signal when the output result of the determining unit is yes, and to determine that the alarm signal is an invalid alarm signal when the output result of the determining unit is no.

[0124] The verification module 10 is used to perform verification calculations on the valid alarm signal.

[0125] It should be noted that the verification algorithm used by the verification module 10 in this embodiment can be an existing verification algorithm, such as SM3, CRC, etc. The first verification algorithm and the second verification algorithm can be the same or different. This embodiment does not make specific limitations.

[0126] Furthermore, the valid signal is a high-level signal or a low-level signal.

[0127] This embodiment splits the alarm signal sent by the detection circuit into two channels for verification. The two verification signals are compared, and if either verification signal is in an alarm state, the chip is triggered to reset or self-destruct. Since it is nearly impossible for the chip to be attacked simultaneously with both alarm signals, even if the chip is attacked and one alarm signal is attacked simultaneously, the system can still ensure that the alarm signal is correctly fed back to the application or that the chip self-destructs, thus resisting multi-point fault attacks. Simultaneously, by setting the alarm signal to be active high or low, and sampling the alarm signal for three consecutive clock cycles, with the signal remaining high or low throughout all three clock cycles, the alarm signal is considered valid. Verification calculations are then performed on valid alarm signals to ensure the accuracy and effectiveness of chip status detection.

[0128] In one embodiment, the signal processing module 50 further includes:

[0129] The second judgment unit is used to determine whether the alarm signal is continuously received within a set time period;

[0130] The second determining unit is configured to determine that the alarm signal is a false alarm signal when the output result of the second determining unit is negative, and to determine that the alarm signal is a non-false alarm signal when the output result of the second determining unit is positive.

[0131] The verification module 10 is used to perform verification calculations on the non-false alarm signals.

[0132] It is understood that those skilled in the art can set the time according to the actual situation, and this embodiment does not make specific limitations.

[0133] It should be noted that since the current environmental detection circuits are all implemented using analog circuits, false alarm signals may be generated from the time the environmental detection circuit is turned on until the environmental monitoring circuit is working stably. This embodiment eliminates false alarm signals by judging whether an alarm signal is received within a set time, thereby ensuring the effectiveness of the verification operation.

[0134] In one embodiment, the reset module 30 includes:

[0135] The first reset unit is used to trigger the chip to perform a power-on reset when the chip is powered on / off.

[0136] The second reset unit is used to trigger the non-power-on reset register to reset when the comparison between the first verification signal and the second verification signal fails.

[0137] It should be noted that if the states of the two verification signals are found to be inconsistent during comparison, it is determined that the alarm signal has been attacked, triggering the chip to perform a reset or self-destruct operation. There are two reset methods depending on the reset source: one is a system-triggered reset method, which only resets when the chip is powered on / off; the other is a reset method triggered when the alarm signal is attacked, which resets all non-power-on reset registers, such as sensitive parameter registers.

[0138] In one embodiment, the device further includes:

[0139] The alarm source storage module 60 is used to store the alarm signal that triggers the non-power-on reset register to be reset, so that the CPU can retrieve it after the chip reset is completed.

[0140] It should be noted that in this embodiment, when the alarm signal is attacked, the alarm signal is stored in the alarm source storage module 60 and the alarm source storage module 60 is reset upon power-on. When the chip is reset after generating the alarm signal, the CPU can still obtain the alarm source signal after the chip reset is completed. The upper layer application can flexibly process data or perform self-destruct chip operation according to the alarm source signal.

[0141] Furthermore, the fifth embodiment of the present invention also provides a chip, the chip including the apparatus described in the above embodiments.

[0142] Furthermore, the sixth embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the method described in the above embodiments.

[0143] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0144] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0145] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0146] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0147] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0148] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0149] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0150] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A real-time detection method for a chip, characterized in that, Each module of the chip is equipped with a detection circuit, and the method includes: Upon receiving an alarm signal from any of the aforementioned detection circuits, the alarm signal is sampled for n consecutive cycles to obtain the signal within the n cycles. Determine whether all signals within the n periods are valid signals, wherein a valid signal is a high-level signal or a low-level signal; If so, the alarm signal is determined to be a valid alarm signal; If not, the alarm signal is determined to be an invalid alarm signal; When the alarm signal is determined to be a valid alarm signal, the first verification algorithm and the second verification algorithm are used to perform verification operations on the valid alarm signal to obtain a first verification signal and a second verification signal. The states of the first verification signal and the second verification signal include a safe state and an alarm state. When the comparison between the first verification signal and the second verification signal fails, the chip is triggered to perform a reset operation or a self-destruct operation. The comparison failure means that at least one of the first verification signal and the second verification signal is in an alarm state. The method further includes: Upon receiving alarm signals from multiple detection circuits, the alarm signals sent by each detection circuit are aggregated for verification, and the alarm signals sent by multiple detection circuits are stored.

2. The real-time chip detection method as described in claim 1, characterized in that, The detection circuit includes a memory verification and protection circuit, an algorithm self-test circuit, an environment detection circuit, a random number self-test circuit, and a mode switching protection circuit.

3. The real-time chip detection method as described in claim 1, characterized in that, The method further includes: Determine whether the alarm signal is received continuously within a set time period; If so, the alarm signal is determined to be a non-false alarm signal; If not, the alarm signal is determined to be a false alarm signal; When the alarm signal is a non-false alarm signal, the first verification algorithm and the second verification algorithm are used to perform verification operations on the non-false alarm signal.

4. The real-time chip detection method as described in claim 1, characterized in that, The reset operation includes power-on / power-off reset of the chip and reset of the non-power-on reset register.

5. The real-time chip detection method as described in claim 4, characterized in that, The method further includes: The alarm signal that triggers the non-power-on reset register reset is stored so that it can be retrieved by the CPU after the chip reset is completed.

6. A real-time detection device for a chip implementing the method as described in any one of claims 1-5, characterized in that, Each module of the chip is equipped with a detection circuit, and the device includes: The verification module is used to perform verification operations on the alarm signal by using a first verification algorithm and a second verification algorithm respectively when receiving an alarm signal sent by any detection circuit, so as to obtain a first verification signal and a second verification signal. The comparison module is used to send a trigger command to the reset module when the comparison between the first verification signal and the second verification signal fails, so that the reset module performs a reset operation or a self-destruct operation on the chip.

7. The real-time chip detection device as described in claim 6, characterized in that, Also includes: The safety control management module is used to summarize the alarm signals sent by each of the multiple detection circuits when it receives alarm signals sent by multiple detection circuits, and send the summarized alarm signals to the verification module.

8. The real-time chip detection device as described in claim 6, characterized in that, The device further includes: A signal sampling unit is used to sample the alarm signal for n consecutive cycles to obtain the signal within n cycles; The first judgment unit is used to determine whether the signals within the n periods are all valid signals, wherein the valid signals are either high-level signals or low-level signals; The first determining unit is configured to determine that the alarm signal is a valid alarm signal when the output result of the first determining unit is yes, and to determine that the alarm signal is an invalid alarm signal when the output result of the first determining unit is no. The verification module is used to perform verification calculations on the valid alarm signals.

9. The real-time chip detection device as described in claim 6, characterized in that, The device further includes: The second judgment unit is used to determine whether the alarm signal is continuously received within a set time period; The second determining unit is configured to determine that the alarm signal is a false alarm signal when the output result of the second determining unit is negative, and to determine that the alarm signal is a non-false alarm signal when the output result of the second determining unit is positive. The verification module is used to perform verification operations on the non-false alarm signals.

10. The real-time chip detection device as described in claim 6, characterized in that, The reset module includes: The first reset unit is used to trigger the chip to perform a power-on reset when the chip is powered on / off. The second reset unit is used to trigger the non-power-on reset register to reset when the comparison between the first verification signal and the second verification signal fails.

11. The real-time chip detection device as described in claim 10, characterized in that, The device further includes: An alarm source storage module is used to store the alarm signal that triggers the reset of the non-power-on reset register, so that the CPU can retrieve it after the chip reset is completed.

12. A chip, characterized in that, Includes the apparatus as described in any one of claims 6-11.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-5.

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