Data matrix processing apparatus, method, device and medium

Abstract

The application provides a data matrix processing device, method, equipment and medium, the device comprises: interface module, cache module;The interface module is connected with the cache module, is used for receiving first data, and obtaining data information of the first data, the data information includes that the first data is M*N data matrix, M is the row number of the data matrix, N is the column number of the data matrix, M and N are all positive integers;The interface module is also used for generating first call instruction according to the data information, and adjusting the address depth of the cache module according to the first call instruction, and the address depth is adjusted to N;The interface module is used for controlling the cache module to write first data, and is also used for controlling the cache module to read out first data.The application adjusts the address depth of the cache module, so that the same row data in the data matrix can be read out simultaneously, and the working efficiency of the cache module is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuit integration, and in particular to a data matrix processing device, method, equipment and medium. BACKGROUND

[0002] In image processing, various windows are often used for data processing, such as 3x3, 5x5, 7x7, 9x9 data matrix processing windows, and multiple rows of data matrices need to be stored and the same row of data in the data matrix needs to be read out at the same time.

[0003] Generally, a line buffer is used to store data in the data matrix, and the data in the line buffer is outputted after a row is filled. Therefore, the data that should be outputted at the same time is delayed to the next row output in the line buffer, as shown in the following figure: Figure 1 The line buffer obtains the data matrix, and the data in each row of the line buffer can be read out only after the row is filled with data, which easily causes the same row of data in the data matrix to be unable to be read at the same time, affecting the efficiency of the subsequent module calling the data in the line buffer.

[0004] Therefore, in order to ensure the simultaneity of reading the same row of data in the data matrix, the present application provides a data matrix processing device, method, equipment and medium, thereby ensuring the simultaneity of reading the same row of data in the data matrix. SUMMARY

[0005] The embodiment of the present application provides a data matrix processing device, method, equipment and medium, and the address depth of the buffer module is adjusted, so that the same row of data in the data matrix can be read out at the same time, and the working efficiency of the buffer module is improved.

[0006] In a first aspect, the present application provides a data matrix processing device, comprising: an interface module, a cache module; the interface module is connected to the cache module; the interface module comprises a receiving unit, the receiving unit is used for receiving first data and generating data information of the first data, the data information comprises that the first data is an M*N data matrix, M is the number of rows of the data matrix, N is the number of columns of the data matrix, and M and N are both positive integers; the interface module further comprises an instruction generating unit, the instruction generating unit is used for receiving the data information and generating a first calling instruction according to the data information; the interface module further comprises an adjusting unit, the adjusting unit is used for receiving the first calling instruction and adjusting the address depth of the cache module according to the first calling instruction, and the address depth is adjusted to N; the interface module further comprises a control unit, the control unit is used for controlling the cache module to write the first data, and is also used for controlling the cache module to read out the first data.

[0007] The beneficial effects are that the address depth is adjusted to N, that is, the address depth of the cache module is adjusted to be consistent with the column number of the first data, so that the cache module can read out the data in the same row of the first data at the same time when reading out the first data, the reading time of the data in the same row is avoided to be inconsistent, and the working efficiency of the cache module is improved.

[0008] Optionally, the interface module is connected with an algorithm module; the algorithm module is also connected to the cache module, and the algorithm module is used for obtaining the first data output by the cache module; the receiving unit is also used for obtaining the number of rows K of the algorithm module and sending the number of rows K of the algorithm module to the instruction generating unit; the instruction generating unit is also used for receiving the number of rows K of the algorithm module and generating a second calling instruction according to the number of rows K of the algorithm module; the adjusting unit is also used for receiving the second calling instruction and adjusting the number of rows of the cache module according to the second calling instruction, and the number of rows of the cache module is adjusted to K, K is a positive integer. The beneficial effects are that the number of rows of the cache module is adjusted to K, that is, the number of rows of the cache module is adjusted to be consistent with the number of rows of the algorithm module, the operation space of the algorithm module can be fully utilized, and the efficiency of data processing is improved.

[0009] Optionally, the data width of the cache module is equal to the product of the bit width and the number of rows of the cache module. The beneficial effects are that the data width of the cache module is equal to the product of the bit width and the number of rows of the cache module, so that the amount of data output by the cache module at a time just meets the demand of the number of rows of the algorithm module, and the efficiency of data processing is improved.

[0010] Optionally, the cache module comprises L SRAMs, L being a positive integer. The advantage is that by comprising L SRAMs, the address depth of the cache module can be adjusted by adjusting the arrangement and number of the SRAMs.

[0011] In a second aspect, the application provides a data matrix processing method, comprising: providing an interface module and a cache module, wherein the interface module comprises a receiving unit, an instruction generating unit, an adjusting unit and a control unit; the receiving unit receives first data and generates data information of the first data, wherein the data information comprises that the first data is a M*N data matrix, M is the number of rows of the data matrix, N is the number of columns of the data matrix, and M and N are both positive integers; the instruction generating unit receives the data information and generates a first calling instruction according to the data information; the adjusting unit receives the first calling instruction and adjusts the address depth of the cache module according to the first calling instruction, and adjusts the address depth to N; and the control unit controls the cache module to write the first data and also controls the cache module to read out the first data.

[0012] The advantage is that by adjusting the address depth to N, i.e. adjusting the address depth of the cache module to be consistent with the number of columns of the first data, the cache module can read out the data of the same row in the first data at the same time when reading out the first data, avoiding inconsistent reading time of the data of the same row, and improving the working efficiency of the cache module.

[0013] Optionally, the method further comprises: providing an algorithm module; the receiving unit acquires the number of rows K of the algorithm module and sends the number of rows K of the algorithm module to the instruction generating unit; the instruction generating unit receives the number of rows K of the algorithm module and generates a second calling instruction according to the number of rows K of the algorithm module; and the adjusting unit receives the second calling instruction and adjusts the number of rows of the cache module according to the second calling instruction, and adjusts the number of rows of the cache module to K, K being a positive integer. The advantage is that by adjusting the number of rows of the cache module to K, i.e. adjusting the number of rows of the cache module to be consistent with the number of rows of the algorithm module, the operation space of the algorithm module can be fully utilized, and the efficiency of data processing is improved.

[0014] Optionally, the data width of the cache module is equal to the product of the bit width and the number of rows of the cache module. The advantage is that by making the data width of the cache module equal to the product of the bit width and the number of rows of the cache module, the amount of data output by the cache module at one time can meet the demand of the number of rows of the algorithm module, and the efficiency of data processing is improved.

[0015] Optionally, the cache module comprises L SRAMs, L being a positive integer. The beneficial effect is that by comprising L SRAMs, the address depth of the cache module can be adjusted by adjusting the arrangement and number of the SRAMs.

[0016] In a third aspect, an electronic device is provided, comprising a processor and a memory. The memory is configured to store one or more programs. When the one or more programs stored in the memory are executed by the processor, the electronic device is enabled to implement the method of any possible design of the second aspect.

[0017] In a fourth aspect, a readable storage medium is provided. The readable storage medium stores a program. When the program is executed by a processor, the method of any possible design of the second aspect is implemented.

[0018] The beneficial effects of the third aspect to the fourth aspect can be seen from the description of the first aspect or the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A schematic diagram of a working mode of a line buffer;

[0020] Figure 2 A schematic diagram of a data matrix processing device provided by an embodiment of the application;

[0021] Figure 3 A schematic diagram of another data matrix processing device provided by an embodiment of the application;

[0022] Figure 4 A flowchart of a data matrix processing method provided by an embodiment of the application;

[0023] Figure 5 A schematic diagram of an electronic device provided by an embodiment of the application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing the specific embodiments and are not intended to be limiting on the present application. As used in the specification and the appended claims of the present application, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that "at least one" and "one or more" as used in the embodiments herein indicates one or two or more (including two). The term "and / or" is used to describe the relationship between associated objects, which means that there can be three relationships; for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects.

[0025] In the present specification, the reference "one embodiment" or "some embodiments" and the like means that a specific feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in other embodiments", "in additional embodiments" and the like appearing in various places in the specification are not necessarily all referring to the same embodiment, but mean that "one or more but not all embodiments", unless otherwise specifically stated. The terms "including", "containing", "having" and their variants mean "including but not limited to", unless otherwise specifically stated. The term "connected" includes direct and indirect connections, unless otherwise specified. "First", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0026] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the embodiments of the present application is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0027] The embodiments of the present application provide a data matrix processing device, as shown in Figure 2 The device 200 includes an interface module 201 and a cache module 202.

[0028] The interface module 201 comprises a receiving unit 2011 configured to receive first data and generate data information of the first data, the data information comprising that the first data is an MxN data matrix, M is a number of rows of the data matrix, N is a number of columns of the data matrix, and M and N are both positive integers. The interface module 201 further comprises an instruction generating unit 2012 configured to receive the data information and generate a first calling instruction according to the data information. The interface module 201 further comprises an adjusting unit 2013 configured to receive the first calling instruction and adjust an address depth of the cache module 202 according to the first calling instruction, and adjust the address depth to N. The interface module 201 further comprises a control unit 2014 configured to control the cache module 202 to write the first data and control the cache module 202 to read out the first data.

[0029] In the embodiments of the present application, not only the data matrix with equal number of rows and columns can be processed, but also the data matrix with unequal number of rows and columns can be processed, and the data matrix processing window is not limited to 3x3, 5x5, 7x7, 9x9 and the like as mentioned in the background art. For example, it is assumed that the first data is a 4x1024 data matrix, and the number of rows of the data matrix is 4 and the number of columns is 1024. The interface module 201 adjusts the address depth of the cache module 202 to 1024 according to the number of columns of the data matrix, because the cache module comprises L SRAMs, and it is assumed that the address depth of one SRAM is 512, then two SRAMs are connected together, which is regarded as an extension in the address depth direction, so as to achieve the purpose of adjusting the address depth of the cache module 202 to 1024, that is, the number of columns of data that can be accommodated by the cache module 202 at one time is 1024, so that the cache module 202 can read out 1024 data of each row of the first data at the same time.

[0030] Optionally, the interface module 201 is connected with an algorithm module 301, and the algorithm module 301 is further connected with the cache module 202, such as Figure 3The algorithm module 301 is configured to obtain the first data output by the cache module 202; the receiving unit 2011 is further configured to obtain the number of rows K of the algorithm module 301, and send the number of rows K of the algorithm module 301 to the instruction generation unit 2012; the instruction generation unit 2012 is further configured to receive the number of rows K of the algorithm module 301, and generate a second calling instruction according to the number of rows K of the algorithm module 301; and the adjusting unit 2013 is further configured to receive the second calling instruction, and adjust the number of rows of the cache module 202 according to the second calling instruction, and adjust the number of rows of the cache module 202 to K, where K is a positive integer.

[0031] For example, assuming that the number of rows of the algorithm module 203 is 4, the receiving unit 2011 is further configured to obtain the number of rows 4 of the algorithm module 301, and send the number of rows 4 of the algorithm module 301 to the instruction generation unit 2012; the instruction generation unit 2012 is further configured to receive the number of rows 4 of the algorithm module 301, and generate a second calling instruction according to the number of rows 4 of the algorithm module 301; and the adjusting unit 2013 is further configured to receive the second calling instruction, and adjust the number of rows of the cache module 202 according to the second calling instruction, and adjust the number of rows of the cache module 202 to 4, so that the number of rows of the cache module 202 is consistent with the number of rows of the algorithm module 203, the operation space of the algorithm module 203 can be fully utilized, and the efficiency of data processing is improved.

[0032] Optionally, the data width of the cache module is equal to the product of the bit width and the number of rows of the cache module. In this embodiment, the data width of the cache module 202 is equal to the product of the bit width and the number of rows of the cache module 202, so that the amount of data output by the cache module 202 at a time is just enough to meet the demand of the number of rows of the algorithm module 203, and the efficiency of data processing is improved.

[0033] Optionally, the cache module 202 includes L static random access memories (SRAMs) (not shown in the figure), and L is a variable, where L is a positive integer. In this embodiment, the cache module 202 includes L SRAMs, so that the arrangement mode and the number of the SRAMs can be adjusted to achieve the purpose of adjusting the address depth of the cache module 202. Of course, the cache module 202 can also be composed of dynamic random access memories (DRAMs), flash memories, first input first output (FIFO) memories and other memories without limitation on the number and combination mode.

[0034] Exemplarily, if the address depth of the cache module 202 needs to be adjusted to 2048, because the cache module includes L SRAMs, and assuming that the address depth of one SRAM is 512, then four SRAMs need to be connected together, that is, L is 4 at this time, and three SRAMs can be regarded as an extension of another SRAM in the address depth direction, so as to achieve the purpose of adjusting the address depth of the cache module 202 to 1024.

[0035] An embodiment of the present application provides a data matrix processing method, a method flow of the method is as shown in Figure 4 The specific steps are as follows:

[0036] S401, providing an interface module and a cache module, and the interface module includes a receiving unit, an instruction generating unit, an adjusting unit and a control unit.

[0037] In this step, the interface module is connected with the cache module, and information interaction exists.

[0038] S402, the receiving unit receives first data, and generates data information of the first data, the data information including that the first data is an M*N data matrix, M is the number of rows of the data matrix, N is the number of columns of the data matrix, and M and N are positive integers.

[0039] In this step, the data information can further include address information of the first data, and the first data is determined to be an M*N data matrix according to the address information, for example, the first data is a 4*1024 data matrix, M is the number of rows of the data matrix, and N is the number of columns of the data matrix.

[0040] S403, the instruction generating unit receives the data information, and generates a first calling instruction according to the data information.

[0041] In this step, if the data information is that the first data is a 4*1024 data matrix, 4 is the number of rows of the data matrix, and 1024 is the number of columns of the data matrix, then the instruction generating unit generates a first calling instruction according to the data information.

[0042] S404, the adjusting unit receives the first calling instruction, and adjusts the address depth of the cache module according to the first calling instruction, and adjusts the address depth to N.

[0043] In this step, if the number of columns of the first data is 1024, then the adjusting unit adjusts the address depth of the cache module to 1024 according to the first calling instruction.

[0044] S405, the control unit controls the cache module to write the first data, and further controls the cache module to read out the first data.

[0045] The above embodiment adjusts the address depth to N, i.e. adjusts the address depth of the cache module to be consistent with the column number of the data matrix, so that the cache module can read out the data of the same row in the first data at the same time when reading out the first data, avoids inconsistency in reading out the data of the same row, and improves the working efficiency of the cache module.

[0046] In a possible embodiment, the method further provides an algorithm module; the receiving unit obtains the row number K of the algorithm module and sends the row number K of the algorithm module to the instruction generation unit; the instruction generation unit receives the row number K of the algorithm module and generates a second calling instruction according to the row number K of the algorithm module; and the adjustment unit receives the second calling instruction and adjusts the row number of the cache module according to the second calling instruction, and adjusts the row number of the cache module to K, K being a positive integer.

[0047] For example, assuming that the row number of the algorithm module is 4, the receiving unit obtains the row number 4 of the algorithm module and sends the row number 4 of the algorithm module to the instruction generation unit; the instruction generation unit is further configured to receive the row number 4 of the algorithm module and generate a second calling instruction according to the row number 4 of the algorithm module; and the adjustment unit is further configured to receive the second calling instruction and adjust the row number of the cache module according to the second calling instruction, and adjust the row number of the cache module to 4, so that the row number of the cache module is consistent with the row number of the algorithm module, the operation space of the algorithm module can be fully utilized, and the efficiency of data processing is improved.

[0048] In yet another possible embodiment, the data width of the cache module is equal to the product of the bit width and the row number of the cache module.

[0049] In still another possible embodiment, the cache module comprises L SRAMs, L being a positive integer, and the L is variable.

[0050] For example, if the address depth of the cache module needs to be adjusted to 2048, because the cache module comprises L SRAMs, assuming that the address depth of one SRAM is 512, four SRAMs need to be connected together, i.e. at this time, L is 4, and three SRAMs can be regarded as an extension of another SRAM in the address depth direction, so as to achieve the purpose of adjusting the address depth of the cache module to 1024.

[0051] In some other embodiments of the present application, the embodiments of the present application disclose an electronic device, such as Figure 5As shown, the electronic device can include one or more processors 501, a memory 502, a display 503, one or more application programs (not shown), and one or more programs 504, which can be connected through one or more communication buses 505. The one or more programs 504 are stored in the above-mentioned memory 502 and configured to be executed by the one or more processors 501, and the one or more programs 504 include instructions that can be used to perform each step in the above-mentioned respective embodiments.

[0052] Through the description of the above embodiments, those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional modules is exemplified, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0053] Each functional unit in each embodiment of the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0054] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a readable storage medium, includes a plurality of instructions to make a device (which can be a server, or a network device, etc.) or a processor execute all or part of the steps of the method of the embodiments of the present application. And the above-mentioned readable storage medium includes: flash memory, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk and various program codes that can be stored in the medium.

[0055] The above is only a specific implementation of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto, any change or replacement within the technical scope disclosed in the embodiments of the present application should be covered in the protection scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

1. A data matrix processing device, characterized in that, include: Interface module, cache module; The interface module is connected to the cache module; The interface module includes a receiving unit, which receives first data and generates data information of the first data. The data information includes the first data as... The data matrix, where M is the number of rows and N is the number of columns, and both M and N are positive integers; The interface module further includes an instruction generation unit, which is used to receive the data information and generate a first call instruction based on the data information; The interface module further includes an adjustment unit, which is used to receive the first call instruction and adjust the address depth of the cache module according to the first call instruction, and adjust the address depth to N; wherein, the cache module includes L SRAMs, where L is a positive integer and L is a variable; the address depth of the cache module is adjusted by adjusting the arrangement and number of the SRAMs. The interface module further includes a control unit, which is used to control the cache module to write first data and to control the cache module to read out the first data. The interface module is connected to the algorithm module; the algorithm module is also connected to the cache module, and the algorithm module is used to obtain the first data output by the cache module; The receiving unit is further configured to obtain the row number K of the algorithm module and send the row number K of the algorithm module to the instruction generation unit; The instruction generation unit is also used to receive the row number K of the algorithm module and generate a second calling instruction based on the row number K of the algorithm module; The adjustment unit is further configured to receive the second call instruction, adjust the number of rows of the cache module according to the second call instruction, and adjust the number of rows of the cache module to K, where K is a positive integer.

2. The apparatus according to claim 1, characterized in that, The data width of the cache module is equal to the product of the bit width and the number of rows in the cache module.

3. A data matrix processing method, characterized in that, include: The system provides an interface module, a cache module, and an algorithm module. The interface module includes a receiving unit, an instruction generation unit, an adjustment unit, and a control unit. The cache module includes L SRAMs, where L is a positive integer and L is a variable. The interface module is connected to the algorithm module. The algorithm module is also connected to the cache module. The receiving unit receives first data and generates data information of the first data, the data information including the first data as... The data matrix, where M is the number of rows and N is the number of columns, and both M and N are positive integers; The instruction generation unit receives the data information and generates a first calling instruction based on the data information; The adjustment unit receives the first call instruction and adjusts the address depth of the cache module according to the first call instruction, and adjusts the address depth to N; wherein, the address depth of the cache module is adjusted by adjusting the arrangement and quantity of the SRAM; The control unit controls the cache module to write the first data, and also controls the cache module to read the first data. The algorithm module obtains the first data output by the cache module; The receiving unit obtains the row number K of the algorithm module and sends the row number K of the algorithm module to the instruction generation unit; The instruction generation unit receives the row number K of the algorithm module and generates a second calling instruction based on the row number K of the algorithm module; The adjustment unit receives the second call instruction and adjusts the number of rows in the cache module according to the second call instruction, and adjusts the number of rows to K, where K is a positive integer.

4. The method according to claim 3, characterized in that, The data width of the cache module is equal to the product of the bit width and the number of rows in the cache module.

5. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a program that can run on the processor, and when the program is executed by the processor, causes the processor to implement the method as described in any one of claims 3 to 4.

6. A readable storage medium storing a program, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 3 to 4.

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