Data processing device, integrated circuit chip, equipment and implementation method thereof

Abstract

The present disclosure relates to a data processing device, method, integrated circuit chip, electronic device and board, wherein the data processing device is included in a computing device, the computing device may be included in a combined processing device, and the combined processing device may further include a universal interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operations specified by the user. The combined processing device may further include a storage device, which is respectively connected to the computing device and the other processing devices and is used to store data from the computing device and the other processing devices. The solution disclosed herein can be widely used in various types of conversions of multi-dimensional data to improve the efficiency of data conversion.

Description

Technical Field

[0001] The present disclosure generally relates to the field of data processing, and more specifically, to a data processing device, an integrated circuit chip, an electronic device, a board, and a method implemented by the data processing device. Background Art

[0002] Operations in the field of artificial intelligence usually involve the processing of multi-dimensional data (such as two-dimensional matrices or three-dimensional arrays). Taking the processing of two-dimensional matrices as an example, its transformation operations can include transposition, rotation, or mirroring. For such transformation operations, dedicated matrix operation custom circuits are generally used to implement them. However, these matrix operation circuits are relatively complex in design, and their interfaces and functions are relatively fixed. Moreover, one type of matrix operation circuit can only process matrix transformations of the corresponding type and cannot perform multiple matrix transformation operations according to actual needs. Therefore, how to obtain a data processing device that can perform transformation operations on multi-dimensional data has become a problem that needs to be solved in the prior art.

[0003] Furthermore, in a computing system, an instruction set is a set of instructions used to perform calculations and control the computing system, and plays a key role in improving the performance of computing chips (such as processors) in the computing system. Current computing chips (especially those in the field of artificial intelligence) use associated instruction sets to complete various general or specific control operations and data processing operations. However, current instruction sets still have many shortcomings. For example, existing instruction sets are limited by hardware architecture and have poor flexibility. Furthermore, current instructions still have room for improvement in converting various data types, especially in describing and processing multi-dimensional data. Summary of the Invention

[0004] In order to at least solve the technical problems mentioned in the above background technology section and provide a computing architecture and instruction system for efficiently processing multi-dimensional data, the solution disclosed in this disclosure will be described in the following multiple aspects.

[0005] In a first aspect, the present disclosure provides a data processing apparatus comprising a data cache circuit and a data conversion circuit, wherein the data cache circuit is configured to perform caching of multi-dimensional data; and

[0006] The data conversion circuit is configured to perform write and read operations on the multidimensional data in the data cache circuit according to a data conversion instruction to achieve data conversion of the multidimensional data, wherein the data conversion instruction includes a descriptor for indicating a shape of the multidimensional data, and the descriptor is used to determine a storage address corresponding to the multidimensional data, wherein the data conversion circuit is configured to perform write and read operations on the multidimensional data according to the storage address.

[0007] In a second aspect, the present disclosure provides an integrated circuit chip, which includes the data processing device described in the first aspect above.

[0008] In a third aspect, the present disclosure provides an electronic device comprising the integrated circuit chip as described in the second aspect above.

[0009] In a fourth aspect, the present disclosure provides a board comprising the integrated circuit chip as described in the third aspect above.

[0010] In a fifth aspect, the present disclosure provides a method implemented by a data processing device, wherein the data processing device includes a data cache circuit and a data conversion circuit, and the method includes: using the data cache circuit to cache multidimensional data; and using the data conversion circuit to perform storage and read operations on the multidimensional data in the data cache circuit according to a data conversion instruction to implement data conversion of the multidimensional data, wherein the data conversion instruction includes a descriptor for indicating the shape of the multidimensional data, and the descriptor is used to determine a storage address corresponding to the multidimensional data, wherein the data conversion circuit is used to perform storage and read operations on the multidimensional data according to the storage address.

[0011] Through the data processing devices, integrated circuit chips, electronic devices, boards and methods provided in the above-mentioned aspects, the scheme disclosed herein can realize data conversion of data, such as multi-dimensional data, by using data conversion instructions to perform storage and read operations on the data to be converted in the data cache circuit, the scheme disclosed herein can realize various operations such as addressing, transporting and deformation of multi-dimensional data. Furthermore, since the aforementioned data conversion operations are implemented by means of instructions, the scheme disclosed herein reduces the changes to the hardware architecture and improves the efficiency of data conversion. In addition, by using descriptors, the scheme disclosed herein promotes the addressing and storage of multi-dimensional data, thereby improving the execution speed of storage and read operations on multi-dimensional data, thereby also accelerating the efficiency of multi-dimensional data conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts.

[0013] Figure 1 is a schematic diagram illustrating a data processing apparatus according to an embodiment of the present disclosure;

[0014] Figure 2 is a schematic diagram illustrating a data storage space for multi-dimensional data according to an embodiment of the present disclosure;

[0015] Figure 3-Figure 5 are flowcharts respectively illustrating various operations of the data conversion circuit according to an embodiment of the present disclosure;

[0016] Figure 6 is a schematic diagram illustrating a computing device according to an embodiment of the present disclosure;

[0017] Figure 7 is a flowchart illustrating a method implemented by a data processing device according to an embodiment of the present disclosure;

[0018] Figure 8 is a structural diagram illustrating a combined processing device according to an embodiment of the present disclosure; and

[0019] Figure 9 2 is a schematic diagram showing the structure of a board according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of this disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this disclosure, not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this disclosure.

[0021] It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, specification, and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0022] It should also be understood that the terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the term "and / or" as used in this disclosure and the claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0023] As used in this specification and claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0024] The specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0025] Figure 1 FIG. 1 is a schematic diagram showing a data processing device 100 according to an embodiment of the present disclosure. Figure 1 As shown in , the data processing device 100 includes a data cache circuit 102 and a data conversion circuit 104. In one embodiment, the data cache circuit can be configured to perform caching of multi-dimensional data. In an exemplary application scenario, the multi-dimensional data disclosed herein may include tensor data of two dimensions or higher. In one embodiment, the data conversion circuit can be configured to perform storage and read operations on the multi-dimensional data in the aforementioned data cache circuit according to the data conversion instruction to achieve data conversion of the multi-dimensional data. For example, by performing storage and read operations on the converted data in different ways, the scheme disclosed herein can perform transformation operations on the multi-dimensional data in various spatial positions to obtain the transformed data. In one embodiment, the aforementioned data conversion instruction may include a descriptor for indicating the shape of the multi-dimensional data, and the descriptor may be used to determine the storage address of the corresponding multi-dimensional data. Further, the data conversion circuit can be configured to perform storage and read operations on the multi-dimensional data according to the storage address.

[0026] In one embodiment, the data conversion instruction disclosed herein may include an identifier of a descriptor and / or the content of the descriptor, and the content of the descriptor may include at least one shape parameter representing the shape of the multidimensional data and / or at least one address parameter representing the address of the multidimensional data. In another embodiment, the address parameter of the multidimensional data may include a reference address of a data reference point of the descriptor in a data storage space of the multidimensional data. In another embodiment, the data conversion instruction may include data volume information and / or inter-dimensional offset information for performing storage and read operations on each dimension of the multidimensional data, and the data volume information and / or inter-dimensional offset information may be determined based on the address parameter and / or shape parameter in the descriptor.

[0027] Based on the discussion of the above multiple embodiments, in an exemplary implementation scenario, the shape parameters of the multidimensional data disclosed herein include at least one of the following: the size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area of ​​the multidimensional data in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the multidimensional data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

[0028] By utilizing the above-mentioned descriptors included in the data conversion instructions, the scheme of the present disclosure can perform various types of conversion operations on multi-dimensional data, which conversion operations may include but are not limited to data mirroring operations, multi-angle data rotation operations or data transposition operations. Taking three-dimensional data as an example, the scheme of the present disclosure can implement transposition, mirroring or multi-angle (for example, 90° or 180°) rotation operations on three-dimensional data. In an application scenario, when the data to be converted is a matrix to be converted (i.e., a two-dimensional data), the data cache circuit may include a cache storage array for caching the matrix data written or written after the data conversion circuit is written in the storage operation, or for transferring the matrix data to the data conversion circuit in the read operation, so that the data conversion circuit performs appropriate conversion when transferring the matrix data to the external memory or computing unit.

[0029] In one embodiment, when the data to be converted is multi-dimensional data, the data conversion instruction may include a descriptor that includes data volume information and inter-dimensional offset information for the data to be stored and read for each dimension of the multi-dimensional data. In one example scenario, the data volume information may include the number of data to be stored and read in each dimension, and the inter-dimensional offset information may include the address interval to be spanned from the current dimension to the next dimension. In another example scenario, the address interval is determined based on the number of data in the current dimension and the space occupied by each data item.

[0030] As an example, when multidimensional data is data having three dimensions: length, width, and height, then for data in the length or width direction (i.e., one dimension), the data volume information may include information such as the number of data items in the length or width direction, the size, and / or the space occupied by each data item. Furthermore, the inter-dimensional offset information may include inter-dimensional offset information from one-dimensional data consisting of the length or width direction to two-dimensional data consisting of the length and width, or inter-dimensional offset information from two-dimensional data consisting of the length and width to three-dimensional data consisting of the length, width, and height. For example, the inter-dimensional offset information may include the number of data items and / or the address space offset spanned from the previous lower dimension to the next higher dimension.

[0031] In order to facilitate reading and writing multi-dimensional data, the present disclosure also proposes that an M-dimensional counter can be defined based on the descriptor, that is, there are M one-dimensional counters, namely N_1, N_2, N_3, ... N_M. When counting, when the nth counter records a full cycle N_n (for example, from 0 to N_n), the nth counter can be reset to zero, and the n+1th counter +1. Based on the definition of the M-dimensional counter, the present disclosure proposes to maintain an M-dimensional read counter and read pointer, as well as maintain an M-dimensional write counter and write pointer. For the M-dimensional read counter, it can be expressed as: R_cnt(i_1, i_2, i_3...i_M), and the corresponding read pointer can be expressed as: R_p = R_addr + i_1*s_0 + i_2*s_1 + ... + s_M-1*n_M, where R_addr is the read base address. During the reading process, the M-dimensional counter R_cnt is incremented by one each time R_n0 elements are read. Similarly, for an M-dimensional write counter, it can be expressed as: W_cnt(i_1, i_2, i_3…i_M), and the corresponding write pointer can be expressed as: W_p=W_addr+i_1*s_0+i_2*s_1+…+s_M-1*n_M, where W_addr is the write base address.

[0032] Based on the aforementioned M-dimensional read and write counters, the disclosed solution can implement data conversion of the data to be converted by storing R_n0 elements into a data cache circuit via a data conversion circuit, and then reading W_n0 elements from the data cache circuit via the data conversion circuit. For example, the data conversion circuit can utilize the aforementioned data storage and read operations to selectively output partial data, rotate the data by a certain angle, mirror or transpose the data, and so on, based on data conversion instructions.

[0033] For example, in one embodiment, the data conversion instruction disclosed herein may further include the aforementioned write base address information ("W_addr") and read base address information ("R_addr") according to the descriptor, wherein in executing the write and read operations, the data conversion circuit may address the next dimension according to the write base address information and the inter-dimensional offset information to perform the write operation, and address the next dimension according to the read base address information and the inter-dimensional offset information to perform the read operation. It can be seen that by utilizing the base address information, the data conversion circuit can more accurately and efficiently locate the multi-dimensional data that needs to perform write and read operations. Furthermore, by introducing the base address information, the method of locating the multi-dimensional data is also expanded and the addressing space is expanded. In addition, by introducing the base address information and the inter-dimensional offset information, the data processing device disclosed herein can implement various operations on multi-dimensional data based on the data conversion instruction, such as one or more operations of bypass operation, multi-angle rotation operation, mirror operation or sequential transformation operation of multi-dimensional data.

[0034] In an exemplary implementation scenario, when the multi-dimensional data is implemented as a two-dimensional matrix, the data cache circuit of the present disclosure may include a cache memory array. In one embodiment, the size of the cache memory array may be determined based on the number of rows X and columns Y of the matrix to be converted, and the storage space K occupied by the basic elements in the matrix.

[0035] Specifically, based on the number of rows X, the number of columns Y, and the storage space K occupied by the basic elements of the matrix to be transformed, the data processing device disclosed herein may further configure a cache storage array that matches the size of the matrix to be transformed, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y. The aforementioned setting of the size of the cache storage array is intended to ensure that the matrix to be transformed can be stored in the cache storage array according to a preset access method. For example, when X is not equal to Y, the number of rows and columns are interchanged during a transposition operation. The number of rows and columns of the cache storage array formed by the above configuration can support such changes in the number of rows and columns during the matrix transformation process. Of course, when X is equal to Y, the above operation can be achieved if the number of rows of the cache storage array is greater than or equal to either X or Y and the number of columns of the cache storage array is greater than or equal to either X or Y.

[0036] Based on the aforementioned cache storage array, the shape of the matrix to be converted (i.e., two-dimensional data) can be described by the disclosed descriptor as (X, Y). This means that the two parameters indicate that the multi-dimensional data is two-dimensional data, with the first dimension (column) of the multi-dimensional data being Y and the second dimension (row) being X. Using this descriptor, the disclosed data conversion circuit can perform corresponding storage and read operations on the two-dimensional matrix in different scenarios, thereby implementing various operations on the two-dimensional matrix, such as transposition, 270° rotation, 90° rotation, 180° rotation, and mirroring.

[0037] Taking the transposition operation as an example, assuming that the matrix to be converted is an X*Y matrix, X may be equal to Y or not equal to Y. The data conversion circuit may store the first row of the X*Y matrix in the order from the first basic element to the Yth basic element in the first row of the cache storage array, and repeat this operation in a loop from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the first basic element to the Yth basic element in the Xth row of the cache storage array, thereby forming an intermediate matrix (X*Y). The intermediate matrix can be understood as the matrix to be converted being copied to the cache storage array. Then, the data conversion circuit sequentially reads the first basic element of the 1st row to the Xth row of the (X*Y) intermediate matrix, and concatenates the X basic elements read out in this order into one row as the first row of the transposed matrix. This operation is cyclically performed from the 1st basic element to the Yth basic element until the first basic element of the 1st row to the Xth row of the X*Y intermediate matrix is ​​sequentially read out, and the X basic elements read out in this order are concatenated into one row as the Yth row of the transposed matrix, thereby forming a transposed matrix.

[0038] Taking a 270° rotation operation as an example, still assuming that the matrix to be converted is an X*Y matrix, where X may be equal to or not equal to Y. The data conversion circuit may store the first row of the X*Y matrix in the order from the Yth basic element to the first basic element in the first row of the cache storage array, and repeat this operation in a loop from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the Yth basic element to the first basic element in the first basic element to the Yth basic element in the Xth row of the cache storage array, thereby forming an X*Y intermediate matrix. The intermediate matrix can be understood as being formed by performing an intra-row mirroring on each row of the matrix to be converted. Then, the data conversion circuit may sequentially read the first basic element from the 1st row to the Xth row of the X*Y intermediate matrix, and concatenate the X basic elements read out in this order into one row as the first row of the rotated matrix. This operation is repeated in this order from the 1st basic element to the Yth basic element until the Yth basic element from the 1st row to the Xth row of the X*Y intermediate matrix is ​​sequentially read out, and the X basic elements read out in this order are concatenated into one row as the Yth row of the rotated matrix, thereby forming a matrix rotated 270°.

[0039] Taking the mirror operation as an example, still assuming that the matrix to be converted is an X*Y matrix, where X may be equal to or not equal to Y. The conversion processing circuit may store the first row of the X*Y matrix in the order from the Yth basic element to the first basic element in the first row of the cache storage array, and repeat this operation in a loop from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the Yth basic element to the first basic element in the first basic element to the Yth basic element in the Xth row of the cache storage array, thereby forming an X*Y intermediate matrix. The intermediate matrix can be understood as being formed by performing intra-row mirroring on each row of the matrix to be converted. Then, the data conversion circuit can read the Xth row of the X*Y intermediate matrix in the order from the Yth basic element to the 1st basic element as the 1st row of the mirrored matrix, and perform such a loop operation in the order from the Xth row to the 1st row of the intermediate matrix until the 1st row of the X*Y intermediate matrix is ​​read in the order from the Yth basic element to the 1st basic element as the Xth row of the mirrored matrix, thereby forming a mirrored matrix.

[0040] Combination of the above Figure 1The composition and operation of the data processing device disclosed herein are described. Based on the above description, those skilled in the art will understand that the data processing device disclosed herein utilizes data conversion instructions to transform multidimensional data, thereby improving the efficiency of executing multidimensional data conversions. In addition, by utilizing a data conversion circuit to perform various different storage and reading operations on multidimensional data in order to convert the data, the disclosed solution simplifies the complexity of multidimensional data conversion operations and accelerates the progress of multidimensional data conversion. As a result, the disclosed solution also reduces data processing overhead and, in computing scenarios requiring data conversion, improves computing efficiency and reduces computing overhead.

[0041] Figure 2 is a schematic diagram showing a data storage space for multidimensional data according to an embodiment of the present disclosure. As previously mentioned, the data conversion operation of the present disclosure also includes using a descriptor to indicate (or obtain) information related to the shape of the multidimensional data, so as to determine the storage address of the multidimensional data, thereby obtaining and saving the multidimensional data through the aforementioned storage address. In addition, based on the foregoing description, those skilled in the art can also understand that the multidimensional data of the present disclosure can refer to or represent tensor data with a dimension greater than or equal to two dimensions. Therefore, the following description of multidimensional data also applies to tensor data with a dimension greater than or equal to two dimensions.

[0042] In an exemplary implementation, a descriptor may be used to indicate the shape of N-dimensional data, where N is a positive integer greater than or equal to 2, such as N=2 or 3. Multidimensional data may include various forms of data composition, such as a matrix may be considered as 2-dimensional or greater multidimensional data, and the aforementioned data according to the "HWC" dimension may be considered as 3-dimensional multidimensional data. The shape of multidimensional data includes information such as the dimensions of the multidimensional data and the size of each dimension. For example, for multidimensional data:

[0043]

[0044] The shape of the multidimensional data can be described by the descriptor as (2, 4), that is, the two parameters indicate that the multidimensional data is two-dimensional data, and the size of the first dimension (column) of the multidimensional data is 2, and the size of the second dimension (row) is 4. It should be noted that this application does not limit the method of indicating the shape of the multidimensional data by the descriptor.

[0045] In an exemplary implementation, the value of N can be determined based on the dimension (order) of the multidimensional data, or can be set based on the usage requirements of the multidimensional data. For example, when the value of N is 3, the multidimensional data is three-dimensional data, and the descriptor can be used to indicate the shape (e.g., offset, size, etc.) of the three-dimensional data. It should be understood that those skilled in the art can set the value of N based on actual needs, and this disclosure does not limit this.

[0046] In one exemplary implementation, the descriptor may include a descriptor identifier and / or descriptor content. In this case, the descriptor identifier may be used to distinguish the descriptors. For example, the descriptor identifier may be a number; the descriptor content may include at least one shape parameter representing the shape of the multidimensional data. For example, when the multidimensional data is three-dimensional data, the shape parameters of two of the three dimensions of the multidimensional data may remain fixed, while the descriptor content may include a shape parameter representing another dimension of the multidimensional data.

[0047] In one exemplary implementation, the identifier and / or content of the descriptor may be stored in a descriptor storage space (internal memory), such as a register, on-chip static random access memory ("SRAM"), or other media cache. Accordingly, the multi-dimensional data indicated by the descriptor may be stored in a data storage space (internal memory or external memory), such as an on-chip cache or off-chip memory. Given this, the present disclosure does not limit the specific locations of the descriptor storage space and the data storage space.

[0048] In an exemplary implementation, the identifier, content, and multi-dimensional data indicated by the descriptor of the descriptor can be stored in the same area of ​​the internal memory. For example, a continuous area of ​​the on-chip cache can be used to store the relevant content of the descriptor, and its address is, for example, ADDR0-ADDR1023. Among them, the address ADDR0-ADDR63 can be used as a descriptor storage space to store the identifier and content of the descriptor, and the address ADDR64-ADDR1023 can be used as a data storage space to store the multi-dimensional data indicated by the descriptor. In the descriptor storage space, the available addresses ADDR0-ADDR31 can be used to store the identifier of the descriptor, and the addresses ADDR32-ADDR63 can be used to store the content of the descriptor. It should be understood that the address ADDR is not limited to 1 bit or 1 byte, and is used here to represent an address, which is an address unit. Those skilled in the art can determine the descriptor storage space, data storage space, and their specific addresses according to actual conditions, and this disclosure is not limited to this.

[0049] In one exemplary implementation, the descriptor identifier, content, and multi-dimensional data indicated by the descriptor can be stored in different areas of the internal memory. For example, a register can be used as the descriptor storage space to store the descriptor identifier and content, and an on-chip cache can be used as the data storage space to store the multi-dimensional data indicated by the descriptor.

[0050] In one exemplary implementation, when a register is used to store the identifier and content of a descriptor, the register number may be used to represent the identifier of the descriptor. For example, when the register number is 0, the identifier of the descriptor stored therein is set to 0. When the descriptor in the register is valid, an area in the cache space may be allocated for storing the multi-dimensional data based on the size of the multi-dimensional data indicated by the descriptor.

[0051] In one exemplary implementation, the identifier and content of the descriptor may be stored in an internal memory, and the multi-dimensional data indicated by the descriptor may be stored in an external memory. For example, the identifier and content of the descriptor may be stored on-chip, and the multi-dimensional data indicated by the descriptor may be stored off-chip.

[0052] In one exemplary implementation, the data address of the data storage space corresponding to each descriptor can be a fixed address. For example, a separate data storage space can be allocated for multi-dimensional data, with the starting address of each multi-dimensional data in the data storage space corresponding to a descriptor. In this case, the data conversion circuit of the present disclosure can determine the data address of the data corresponding to the operand in the data storage space based on the descriptor.

[0053] In an exemplary implementation, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor can also be used to indicate the address of multidimensional data. In this case, the content of the descriptor can also include at least one address parameter representing the address of the multidimensional data. For example, when the multidimensional data is 3D data, when the descriptor points to the address of the multidimensional data, the content of the descriptor can include an address parameter representing the address of the multidimensional data, such as the starting physical address of the multidimensional data, or can also include multiple address parameters of the address of the multidimensional data. For example, the starting address + address offset of the multidimensional data, or the address parameters of the multidimensional data based on each dimension. Those skilled in the art can set the address parameters according to actual needs, and this disclosure does not limit this.

[0054] In one exemplary implementation, the address parameter of the multi-dimensional data may include a reference address of the data reference point of the descriptor in the data storage space of the multi-dimensional data. The reference address may vary depending on the data reference point. This disclosure does not limit the selection of the data reference point.

[0055] In one exemplary implementation, the reference address may include the starting address of the data storage space. When the data reference point of the descriptor is the first data block in the data storage space, the reference address of the descriptor is the starting address of the data storage space. When the data reference point of the descriptor is data other than the first data block in the data storage space, the reference address of the descriptor is the address of the data block in the data storage space.

[0056] In an exemplary implementation, the shape parameters of the multidimensional data include at least one of the following: the size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the multidimensional data indicated by the descriptor and the data address. The data description position is the mapping position of the point or area in the multidimensional data indicated by the descriptor. For example, when the multidimensional data is 3D data, the descriptor can use three-dimensional space coordinates (x, y, z) to represent the shape of the multidimensional data, and the data description position of the multidimensional data can be the position of the point or area mapped in the three-dimensional space represented by the three-dimensional space coordinates (x, y, z).

[0057] It should be understood that those skilled in the art can select shape parameters representing multi-dimensional data according to actual circumstances, and this disclosure does not limit this. By using descriptors in the data access process, associations between data can be established, thereby reducing the complexity of data access and improving instruction processing efficiency.

[0058] In an exemplary implementation, the content of the descriptor of the multidimensional data can be determined based on the base address of the data base point of the descriptor in the data storage space of the multidimensional data, the size of the data storage space in at least one of the N dimensional directions, the size of the storage area in at least one of the N dimensional directions, and / or the offset of the storage area in at least one of the N dimensional directions.

[0059] like Figure 2In the example shown in FIG, data storage space 21 stores two-dimensional data in a row-major manner, which can be represented by (x, y) (where the X axis is horizontal and rightward, and the Y axis is vertical and downward). The size in the X-axis direction (the size of each row) is ori_x (not shown in the figure), and the size in the Y-axis direction (the total number of rows) is ori_y (not shown in the figure). The starting address PA_start (base address) of data storage space 21 is the physical address of the first data block 22. Data block 23 is part of the data in data storage space 21. Its offset 25 in the X-axis direction is represented by offset_x, its offset 24 in the Y-axis direction is represented by offset_y, its size in the X-axis direction is represented by size_x, and its size in the Y-axis direction is represented by size_y.

[0060] In one exemplary implementation, when a descriptor is used to define data block 23, the first data block in data storage space 21 can be used as the data reference point for the descriptor. The descriptor's reference address can be agreed upon to be the starting address PA_start of data storage space 21. The content of the descriptor for data block 23 can then be determined by combining the X-axis size ori_x and Y-axis size ori_y of data storage space 21, as well as the Y-axis offset offset_y, X-axis offset offset_x, X-axis size size_x, and Y-axis size size_y of data block 23.

[0061] In an exemplary implementation, the following formula (1) may be used to express the content of the descriptor:

[0062]

[0063] It should be understood that although in the above examples, the content of the descriptor represents a two-dimensional space, those skilled in the art can set the specific dimension represented by the content of the descriptor according to actual conditions, and this disclosure does not limit this.

[0064] In one exemplary implementation, a reference address of a data reference point of the descriptor in the data storage space may be agreed upon. Based on this reference address, the content of the descriptor of the multi-dimensional data may be determined based on the positions of at least two vertices located diagonally in N dimensions relative to the data reference point.

[0065] For example, the data reference point of the descriptor can be agreed to be the reference address PA_base in the data storage space. For example, a data (e.g., data at position (2, 2)) can be selected in the data storage space 21 as the data reference point, and the physical address of the data in the data storage space can be used as the reference address PA_base. Then, the position of the two vertices at the diagonal position relative to the data reference point can be used to determine the Figure 2 The contents of the descriptor of data block 23 in the data block 23 are determined. First, the positions of at least two diagonal vertices of data block 23 relative to the data reference point are determined. For example, the positions of the diagonal vertices from the upper left to the lower right relative to the data reference point are used. The relative position of the upper left vertex is (x_min, y_min), and the relative position of the lower right vertex is (x_max, y_max). Then, the contents of the descriptor of data block 23 can be determined based on the reference address PA_base, the relative position of the upper left vertex (x_min, y_min), and the relative position of the lower right vertex (x_max, y_max).

[0066] In an exemplary implementation, the following formula (2) can be used to express the content of the descriptor (the base address is PA_base):

[0067]

[0068] It should be understood that although the vertices at the upper left corner and the lower right corner are used in the above example to determine the content of the descriptor, those skilled in the art can set the specific vertices of at least two diagonal positions according to actual needs, and this disclosure does not limit this.

[0069] In one exemplary implementation, the content of the descriptor for the multi-dimensional data may be determined based on the reference address of the descriptor's data reference point in the data storage space and the mapping relationship between the data description location and the data address of the multi-dimensional data indicated by the descriptor. The mapping relationship between the data description location and the data address may be set based on actual needs. For example, when the multi-dimensional data indicated by the descriptor is three-dimensional spatial data, the function f(x, y, z) may be used to define the mapping relationship between the data description location and the data address.

[0070] In an exemplary implementation, the following formula (3) may be used to express the content of the descriptor:

[0071]

[0072] In an exemplary implementation, the descriptor is further used to indicate the address of the multi-dimensional data, wherein the content of the descriptor further includes at least one address parameter representing the address of the multi-dimensional data. For example, the content of the descriptor may be:

[0073] D:

[0074] Where PA is the address parameter. The address parameter can be a logical address or a physical address. The descriptor parsing circuit can use PA as any vertex, midpoint, or preset point of the vector shape and combine it with the shape parameters in the X and Y directions to obtain the corresponding data address.

[0075] In an exemplary implementation, the address parameter of the multi-dimensional data includes a reference address of a data reference point of the descriptor in a data storage space of the multi-dimensional data, and the reference address includes a starting address of the data storage space.

[0076] In a possible implementation, the descriptor may further include at least one address parameter representing the address of the multi-dimensional data. For example, the content of the descriptor may be:

[0077] D:

[0078] PA_start is the base address parameter and will not be described in detail.

[0079] It should be understood that those skilled in the art can set the mapping relationship between the data description location and the data address according to actual conditions, and this disclosure does not limit this.

[0080] In one exemplary implementation, a predetermined reference address can be set within a task. All descriptors in instructions within this task use this reference address, and the descriptor content can include shape parameters based on this reference address. This reference address can be determined by setting the environment parameters for this task. A description of the reference address and its use can be found in the above embodiments. In this implementation, the descriptor content can be mapped to data addresses more quickly.

[0081] In one exemplary implementation, the base address can be included in the content of each descriptor, and the base address of each descriptor can be different. Compared with the method of using environmental parameters to set a common base address, each descriptor in this method can describe data more flexibly and use a larger data address space.

[0082] In one exemplary implementation, the data address of the data corresponding to the operand of the processing instruction in the data storage space can be determined based on the content of the descriptor. The data address is calculated automatically by hardware, and the method for calculating the data address varies depending on the representation of the descriptor content. This disclosure does not limit the specific method for calculating the data address.

[0083] For example, the content of the descriptor in the operand is expressed using formula (1). The offsets of the multi-dimensional data indicated by the descriptor in the data storage space are offset_x and offset_y, and the size is size_x*size_y. Then, the starting data address PA1 of the multi-dimensional data indicated by the descriptor in the data storage space is (x,y) It can be determined using the following formula (4):

[0084] PA1 (x,y) =PA_start+(offset_y-1)*ori_x+offset_x (4)

[0085] The data starting address PA1 is determined according to the above formula (4) (x,y) , combined with the offsets offset_x and offset_y, and the sizes size_x and size_y of the storage area, the storage area of ​​the multi-dimensional data indicated by the descriptor in the data storage space can be determined.

[0086] In one exemplary implementation, when the operand also includes a data description location for a descriptor, the data address of the data corresponding to the operand in the data storage space can be determined based on the content of the descriptor and the data description location. In this way, partial data (e.g., one or more data) in the multi-dimensional data indicated by the descriptor can be processed.

[0087] For example, the content of the descriptor in the operand is expressed using formula (1). The offsets of the multi-dimensional data indicated by the descriptor in the data storage space are offset_x and offset_y respectively, and the size is size_x*size_y. The data description position for the descriptor included in the operand is (x q ,y q ), then the data address PA2 of the multi-dimensional data indicated by the descriptor in the data storage space (x,y) It can be determined using the following formula (5):

[0088] PA2 (x,y) =PA_start+(offset_y+y q -1)*ori_x+(offset_x+x q ) (5)

[0089] The data starting address PA2 is determined according to the above formula (5) (x,y) , combined with the offsets offset_x and offset_y, and the sizes size_x and size_y of the storage area, the storage area of ​​the multi-dimensional data indicated by the descriptor in the data storage space can be determined.

[0090] In one exemplary implementation, when the operand also includes a data description location for a descriptor, the data address of the data corresponding to the operand in the data storage space can be determined based on the content of the descriptor and the data description location. In this way, partial data (e.g., one or more data) in the multi-dimensional data indicated by the descriptor can be processed.

[0091] For example, the content of the descriptor in the operand is expressed using formula (2). The offsets of the multi-dimensional data indicated by the descriptor in the data storage space are offset_x and offset_y respectively, and the size is size_x*size_y. The data description position for the descriptor included in the operand is (x q ,y q ), then the data address PA2 of the multi-dimensional data indicated by the descriptor in the data storage space (x,y) It can be determined using the following formula (6):

[0092] PA2 (x,y) =PA_start+(offset_y+y q -1)*ori_x+(offset_x+x q ) (6)

[0093] Combination of the above Figure 1 and Figure 2 The data processing device disclosed herein is described. By using data conversion instructions and combining descriptors, the data processing device disclosed herein can significantly improve the access and conversion efficiency of multi-dimensional data and reduce the overhead of multi-dimensional data processing.

[0094] Figure 3-Figure 5 1 and 2 are flow charts respectively illustrating various operations of the data conversion circuit according to an embodiment of the present disclosure.

[0095] In order to execute Figure 3 In the operation 300 shown, the data processing apparatus of the present disclosure may further include an external memory (eg, Figure 6exemplarily shown in the storage circuit 602). Based on the external memory, the data conversion instruction of the present disclosure may include a first descriptor and a second descriptor. In this scenario, at step S302, the data conversion circuit of the present disclosure may be configured to read the multidimensional data from the external memory according to the first descriptor so as to store it in the data cache circuit. Then, at step S304, the data conversion circuit of the present disclosure may be configured to read the multidimensional data in the data cache circuit into the external memory according to the second descriptor. By means of different storage and read operations for the data cache circuit, the scheme of the present disclosure may utilize descriptors to implement the conversion of multidimensional data. For example, the data conversion circuit of the present disclosure may perform a deformation operation on the multidimensional data as a whole or in blocks through the first descriptor, and then output the multidimensional data represented by the second descriptor. According to different conversion scenarios, the aforementioned deformation operation may include but is not limited to operations such as mirroring, 180-degree, 270-degree, 90-degree rotation or transposition of the multidimensional data.

[0096] In one or more embodiments, when the data conversion instruction includes an operation parameter, the data conversion circuit of the present disclosure may be configured to perform data conversion on the multi-dimensional data according to the operation parameter. Figure 4 and Figure 5 The data conversion operations 400 and 500 performed by the data conversion circuit of the present disclosure according to the aforementioned operating parameters are described.

[0097] like Figure 4 As shown in , when the data conversion circuit is configured to perform an operation according to the operating parameters, it can, at step S402, store the multidimensional data in the data cache circuit in the order of the first dimension of the multidimensional data. Then, at step S404, the data conversion circuit of the present disclosure can be configured to read the multidimensional data from the data cache circuit in the order of the second dimension for output. For example, for three-dimensional data in the neural network in the order of "HWC" dimensions (H represents height, W represents width, and C represents channel), the three-dimensional data can be converted into three-dimensional data in the order of "WCH" or "CWH" dimensions by performing operation 400 according to the operating parameters, thereby achieving conversion of the three-dimensional data.

[0098] like Figure 5 As shown in , at step S502, the data conversion circuit is configured to perform data conversion on the multi-dimensional data according to the operating parameters. As an example, the data conversion circuit can perform multiple operations as shown in steps S502-1 to S502-3 according to different operating parameters.

[0099] Specifically, as shown in step S502-1, based on the operating parameters, the data conversion circuit of the present disclosure can be configured to perform write and read operations on one or more portions of the multi-dimensional data in the data cache circuit to achieve data conversion on the one or more portions of the multi-dimensional data. In other words, based on the instructions of the operating parameters, the data conversion circuit of the present disclosure can selectively perform write and read operations on multiple portions of the multi-dimensional data, rather than processing the entire multi-dimensional data.

[0100] As shown in step S502-2, according to the operating parameters, the data conversion circuit of the present disclosure can be configured to splice and output multiple parts of the converted multi-dimensional data read from the data cache circuit. That is to say, in addition to converting by accessing the multi-dimensional data for the data cache circuit, the data conversion circuit of the present disclosure can also perform relevant post-processing operations on the converted multi-dimensional data to facilitate subsequent processing. Specifically, according to the operating parameters, the data conversion circuit can select multiple parts of the specified multi-dimensional data (for example, corresponding to one or more dimensions) and arrange them according to the requirements of subsequent operations (which may include orderly splicing) for subsequent processing. In an exemplary implementation scenario, the subsequent processing can be, for example, performed by Figure 6 The calculation circuit 604 is used to perform the calculation.

[0101] Slightly different from the operation of step S502-2 above, in the operation shown in step S502-3, according to the operating parameters, the data conversion circuit of the present disclosure can be configured to combine multiple parts of the unconverted multi-dimensional data read from the data cache circuit for output. It can be seen that in this case, the data conversion circuit of the present disclosure does not convert the multi-dimensional data by storing and reading the data cache circuit. Instead, it converts the multi-dimensional data into the data before sending it to the subsequent processing unit (e.g. Figure 6 Before the calculation circuit 604 outputs the multi-dimensional data, a combination operation is performed on the unconverted multi-dimensional data. In other words, the data conversion circuit of the present disclosure can support enabling and disabling functions for the data conversion operation portion, and this can be selected based on operating parameters. When the data conversion function is disabled based on the operating parameters, the data conversion circuit of the present disclosure also supports selectively not converting the entire multi-dimensional data, but instead selecting and combining multiple portions thereof (which can also be specified by the operating parameters) for subsequent processing.

[0102] Figure 6 is a schematic diagram illustrating a computing device 600 according to an embodiment of the present disclosure. Figure 6 As shown in FIG, the computing device 600 may include the above-mentioned combination Figure 1The data processing device 100 described in the figure includes a data buffer circuit 102 and a data conversion circuit 104. Figure 1-Figure 5 The data processing device of the present disclosure has been described in detail, and the specific descriptions of the data cache circuit 102 and the data conversion circuit 104 are also applicable to the computing device 200, so the same contents will not be repeated.

[0103] As shown in the figure, the computing device of the present disclosure also includes a storage circuit 602 and a computing circuit 604. Depending on different application scenarios, the computing circuit and the storage circuit here can be implemented in different ways. In one embodiment, the storage circuit can take the form of a memory, for example, a dynamic random access memory ("DRAM") or a double data rate synchronous dynamic random access memory ("DDR SDRAM"), which can be used to store the computing data required for the computing circuit to perform operations, or for data exchanged with an external memory, such as multi-dimensional data according to the present disclosure. When the computing device of the present disclosure is applied to the field of artificial intelligence, the aforementioned computing data or data to be exchanged can be data from various related fields, such as various training data, network model data and parameters in machine learning, and various types of data to be detected (such as three-dimensional or four-dimensional image data, etc.).

[0104] In another embodiment, the computing circuit can take the form of a general or special processor and a general or special processor core, which can include various types of operators and buses (such as data buses, control buses or broadcast buses). When the solution of the present disclosure is applied to the field of artificial intelligence, the computing circuit can be implemented or included in a single-core or multi-core deep learning processor to implement various computing operations for multi-dimensional data. In an application scenario, when the computing circuit is implemented as a processor core, it can be packaged together with a data cache circuit and a data conversion circuit to form a processor. In this case, the data cache circuit can be implemented as a cache of a computing device to save the data (such as multi-dimensional data) and instructions most frequently accessed by the computing circuit in the memory (such as the storage circuit 202), so that the computing circuit does not need to read the required data and instructions from the relatively slow running memory.

[0105] Figure 7 700 is a flow chart showing a method 700 implemented by a data processing device according to an embodiment of the present disclosure. It can be understood that the data processing device herein is the aforementioned combined Figures 1-6 Therefore, the above description of the data processing device also applies to Figure 7 The same contents will not be described again.

[0106] like Figure 7As shown in , at step S702, method 700 uses a data cache circuit to perform caching of multidimensional data. According to different embodiments of the present disclosure, the data here may be multidimensional data, such as a two-dimensional matrix or a three-dimensional or four-dimensional array. At step S704, method 700 uses the data conversion circuit to perform write and read operations on the multidimensional data in the data cache circuit according to the data conversion instruction to achieve data conversion of the multidimensional data. As previously described, in one embodiment, the data conversion instruction may include a descriptor for indicating the shape of the multidimensional data, and the descriptor is used to determine the storage address of the corresponding multidimensional data. In another embodiment, method 700 includes using the data conversion circuit to perform write and read operations on the multidimensional data according to the storage address. Although in Figure 7 It is not shown in the figure, but those skilled in the art will appreciate that the method 700 can be performed in conjunction with Figures 1-6 The various operations of the data processing apparatus are described.

[0107] Figure 8 FIG. 8 is a structural diagram showing a combined processing device 800 according to an embodiment of the present disclosure. Figure 8 As shown in FIG, the combined processing device 800 includes a computing processing device 802, an interface device 804, other processing devices 806, and a storage device 808. According to different application scenarios, the computing processing device may include one or more computing devices 810, which may include the data processing device disclosed herein and may be configured to execute the data processing device disclosed herein in conjunction with the attached Figure 1-7 The described operation.

[0108] In various embodiments, the computing and processing device of the present disclosure may be configured to perform user-specified operations. In exemplary applications, the computing and processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, the computing and processing device of the present disclosure may be considered to have a single-core structure or a homogeneous multi-core structure.

[0109] In exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through interface means, to jointly complete the operation specified by the user. Depending on the difference in implementation, the other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as central processing unit (Central Processing Unit, CPU), graphics processing unit (Graphics Processing Unit, GPU), artificial intelligence processor. These processors may include but are not limited to digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0110] In one or more embodiments, the other processing device may serve as an interface between the computing processing device of the present disclosure and external data and control, performing basic control including but not limited to data transfer, starting and / or stopping the computing device, etc. In other embodiments, the other processing device may also collaborate with the computing processing device to jointly complete computing tasks.

[0111] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it to the storage device (or memory) on the computing and processing device chip. Furthermore, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them to the control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0112] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0113] In some embodiments, the present disclosure also discloses a chip (e.g. Figure 9 In one implementation, the chip is a system on chip (SoC) and integrates one or more components such as Figure 8 The chip can be connected to the external interface device (such as Figure 9 The external interface device 906 shown in the figure is connected to other related components. The related components can be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as video codecs) and / or interface modules (such as DRAM interfaces) can be integrated on the chip. In some embodiments, the present disclosure also discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure also discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 9 The board is described in detail.

[0114] Figure 9 FIG. 1 is a schematic diagram showing the structure of a board 900 according to an embodiment of the present disclosure. Figure 9 As shown in , the board includes a storage device 904 for storing data, which includes one or more storage units 910. The storage device can be connected to the control device 908 and the chip 902 described above and transmit data by means of, for example, a bus. Further, the board also includes an external interface device 906, which is configured for data relay or transfer function between the chip (or the chip in the chip packaging structure) and the external device 912 (such as a server or computer, etc.). For example, the data to be processed can be passed from the external device to the chip through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0115] In one or more embodiments, the control device in the disclosed board can be configured to regulate the state of the chip. To this end, in one application scenario, the control device can include a microcontroller unit (MCU) for regulating the working state of the chip.

[0116] According to the above combination Figure 8 and Figure 9 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0117] According to different application scenarios, the electronic devices or devices disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, Internet of Things terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, vehicles, household appliances, and / or medical equipment. The vehicles include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging (MRI), ultrasound machines and / or electrocardiographs. The electronic devices or devices disclosed herein may also be applied to the Internet, Internet of Things, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, medical care and other fields. Furthermore, the electronic devices or devices disclosed herein may also be used in cloud, edge, terminal and other application scenarios related to artificial intelligence, big data and / or cloud computing. In one or more embodiments, electronic devices or apparatuses with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or apparatuses with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0118] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will understand that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teachings of the present disclosure, those skilled in the art will understand that some of the steps therein can be performed in other orders or simultaneously. Further, those skilled in the art will understand that the embodiments described in the present disclosure can be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the implementation of one or more schemes of the present disclosure. In addition, depending on the different schemes, the description of some embodiments of the present disclosure also has different emphases. In view of this, those skilled in the art will understand that the parts that are not described in detail in a certain embodiment of the present disclosure may also refer to the relevant descriptions of other embodiments.

[0119] In terms of specific implementation, based on the disclosure and teachings of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this document divides them based on the consideration of logical functions, and there may be other ways of division in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. With respect to the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0120] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network elements. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solution described in the embodiments of this disclosure. In addition, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically separately.

[0121] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program code, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0122] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0123] Although a plurality of embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may conceive of many modifications, changes, and alternatives without departing from the ideas and spirit of the present disclosure. It should be understood that in practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The appended claims are intended to define the scope of protection of the present disclosure and therefore cover equivalents or alternatives within the scope of these claims.

[0124] The foregoing content can be better understood in accordance with the following terms:

[0125] Item A1. A data processing device comprising a data cache circuit and a data conversion circuit, wherein:

[0126] The data caching circuit is configured to perform caching of multi-dimensional data; and

[0127] The data conversion circuit is configured to perform storage and reading operations on the multi-dimensional data in the data cache circuit according to the data conversion instruction to achieve data conversion of the multi-dimensional data.

[0128] The data conversion instruction includes a descriptor for indicating the shape of the multi-dimensional data, and the descriptor is used to determine the storage address of the corresponding multi-dimensional data.

[0129] The data conversion circuit is configured to perform storage and reading operations on the multi-dimensional data according to the storage address.

[0130] Item A2. A data processing device according to Item A1, wherein the data conversion instruction includes an identifier of a descriptor and / or the content of the descriptor, and the content of the descriptor includes at least one shape parameter representing the shape of the multidimensional data and at least one address parameter representing the address of the multidimensional data.

[0131] Item A3. A data processing device according to Item A2, wherein the address parameter of the multi-dimensional data includes a reference address of a data reference point of the descriptor in a data storage space of the multi-dimensional data.

[0132] Clause A4. The data processing apparatus of clause A2, wherein the shape parameter of the multidimensional data comprises at least one of the following:

[0133] The size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area of ​​the multi-dimensional data in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the multi-dimensional data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

[0134] Item A5. A data processing device according to Item A2, wherein the data conversion instruction includes data volume information and / or inter-dimensional offset information for performing storage and read operations on each dimension in the multi-dimensional data, and wherein the data volume information and / or inter-dimensional offset information is determined based on the address parameters and / or shape parameters in the descriptor.

[0135] Clause A6. The data processing device according to any one of clauses A1 to A5, wherein the data processing device further comprises an external memory for storing multi-dimensional data, the data conversion instruction comprises a first descriptor and a second descriptor, and the data conversion circuit is configured to:

[0136] Reading the multi-dimensional data from an external memory according to the first descriptor so as to store the data into the data cache circuit; and

[0137] The multi-dimensional data in the data cache circuit is read into the external memory according to the second descriptor.

[0138] Clause A7. The data processing apparatus of any one of clauses A1-A5, wherein the data conversion circuit is configured to perform store and read operations on the multi-dimensional data to perform one of the following conversion operations on the multi-dimensional data:

[0139] Data mirroring operations, multi-angle data rotation operations, or data transposition operations.

[0140] Item A8. A data processing device according to any one of items A1-A5, wherein the data conversion instruction includes an operation parameter, and the data conversion circuit is configured to perform data conversion on the multi-dimensional data according to the operation parameter.

[0141] Clause A9. The data processing apparatus of clause A8, wherein the data conversion circuit is configured to:

[0142] According to the operation parameters, storage and reading operations are performed on one or more parts of the multi-dimensional data in the data cache circuit to implement data conversion on the one or more parts of the multi-dimensional data.

[0143] Clause A10. The data processing apparatus of clause A8, wherein the data conversion circuit is configured to:

[0144] According to the operating parameters, a plurality of parts of the converted multi-dimensional data read from the data cache circuit are spliced ​​for output.

[0145] Clause A11. The data processing apparatus of clause A8, wherein the data conversion circuit is configured to:

[0146] Based on the operating parameters, a plurality of portions of the unconverted multi-dimensional data read from the data cache circuit are combined for output.

[0147] Clause A12. The data processing apparatus of clause A8, wherein the data conversion circuit is configured to perform the following operations based on the operating parameters:

[0148] storing the multi-dimensional data into the data cache circuit in the order of the first dimension of the multi-dimensional data; and

[0149] The multi-dimensional data is read from the data cache circuit in a second dimensional order for output.

[0150] Item A13. An integrated circuit chip comprising the data processing device according to any one of Items A1-A12.

[0151] Item A14. An electronic device comprising the integrated circuit chip according to Item A13.

[0152] Item A15. A board comprising the integrated circuit chip according to Item A13.

[0153] Clause A16. A method implemented by a data processing device, wherein the data processing device includes a data cache circuit and a data conversion circuit, the method comprising:

[0154] Using the data cache circuit to cache multi-dimensional data; and

[0155] Using the data conversion circuit to perform storage and reading operations on the multi-dimensional data in the data cache circuit according to the data conversion instruction, so as to realize data conversion of the multi-dimensional data,

[0156] The data conversion instruction includes a descriptor for indicating the shape of the multi-dimensional data, and the descriptor is used to determine the storage address of the corresponding multi-dimensional data.

[0157] The data conversion circuit is used to perform storage and reading operations on the multi-dimensional data according to the storage address.

[0158] Item A17. A method according to Item A16, wherein the data conversion instruction includes an identifier of a descriptor and / or the content of the descriptor, and the content of the descriptor includes at least one shape parameter representing the shape of the multidimensional data and at least one address parameter representing the address of the multidimensional data.

[0159] Item A18. The method of Item A17, wherein the address parameter of the multi-dimensional data includes a reference address of a data reference point of the descriptor in a data storage space of the multi-dimensional data.

[0160] Clause A19. The method of clause A17, wherein the shape parameter of the multidimensional data comprises at least one of the following:

[0161] The size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area of ​​the multi-dimensional data in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the multi-dimensional data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

[0162] Item A20. A method according to Item A17, wherein the data conversion instruction includes data volume information and / or inter-dimensional offset information for performing storage and read operations on each dimension in the multi-dimensional data, and wherein the data volume information and / or inter-dimensional offset information is determined based on the address parameters and / or shape parameters in the descriptor.

[0163] Clause A21. A method according to any one of clauses A16-A20, wherein the data processing apparatus further comprises an external memory for storing multi-dimensional data, the data conversion instruction comprises a first descriptor and a second descriptor, wherein the method uses the data conversion circuit to perform the following steps:

[0164] Reading the multi-dimensional data from an external memory according to the first descriptor so as to store the data into the data cache circuit; and

[0165] The multi-dimensional data in the data cache circuit is read into the external memory according to the second descriptor.

[0166] Clause A22. The method of any one of clauses A16-A20, wherein the data conversion circuit is used to perform storage and read operations on the multi-dimensional data to perform one of the following conversion operations on the multi-dimensional data:

[0167] Data mirroring operations, multi-angle data rotation operations, or data transposition operations.

[0168] Clause A23. A method according to any one of clauses A16-A20, wherein the data conversion instruction includes an operation parameter, and the method includes using the data conversion circuit to perform data conversion on the multi-dimensional data according to the operation parameter.

[0169] Clause A24. The method of clause A23, wherein the data conversion circuit is used to perform the following steps:

[0170] According to the operation parameters, storage and reading operations are performed on one or more parts of the multi-dimensional data in the data cache circuit to implement data conversion on the one or more parts of the multi-dimensional data.

[0171] Clause A25. The method of clause A23, wherein the data conversion circuit is used to perform the following steps:

[0172] According to the operating parameters, a plurality of parts of the converted multi-dimensional data read from the data cache circuit are spliced ​​for output.

[0173] Clause A26. The method of clause A23, wherein the data conversion circuit is used to perform the following steps:

[0174] Based on the operating parameters, a plurality of portions of the unconverted multi-dimensional data read from the data cache circuit are combined for output.

[0175] Clause A27. The method of clause A23, wherein the data conversion circuit is used to perform the following operations based on the operating parameters:

[0176] storing the multi-dimensional data into the data cache circuit in the order of the first dimension of the multi-dimensional data; and

[0177] The multi-dimensional data is read from the data cache circuit in a second dimensional order for output.

[0178] In the above embodiments of the present disclosure, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A data processing device comprising a data buffer circuit and a data conversion circuit, wherein: The data caching circuit is configured to perform caching of multi-dimensional data; as well as The data conversion circuit is configured to perform storage and reading operations on the multi-dimensional data in the data cache circuit according to the data conversion instruction to achieve data conversion of the multi-dimensional data. The data conversion instruction includes a descriptor for indicating the shape of the multi-dimensional data, and the descriptor is used to determine the storage address of the corresponding multi-dimensional data. wherein the data conversion circuit is configured to perform storage and reading operations on the multi-dimensional data according to the storage address; wherein the data conversion instruction includes an operation parameter, and the data conversion circuit is configured to perform data conversion on the multi-dimensional data according to the operation parameter; The data conversion circuit is configured to perform the following operations according to the operating parameters: storing the multi-dimensional data into the data cache circuit in the order of the first dimension of the multi-dimensional data to form an intermediate matrix; as well as Reading the intermediate matrix from the data cache circuit in order of the second dimension for output; The descriptor includes data amount information and inter-dimensional offset information for performing storage and reading operations on each dimension of multi-dimensional data, and wherein the data amount information and inter-dimensional offset information are determined according to address parameters and shape parameters in the descriptor.

2. A data processing device according to claim 1, wherein the data conversion instruction includes an identifier of a descriptor and / or the content of the descriptor, and the content of the descriptor includes at least one shape parameter representing the shape of the multidimensional data and at least one address parameter representing the address of the multidimensional data. 3 . The data processing apparatus according to claim 2 , wherein the address parameter of the multi-dimensional data comprises a reference address of a data reference point of the descriptor in a data storage space of the multi-dimensional data.

4. The data processing apparatus according to claim 3, wherein the shape parameter of the multi-dimensional data comprises at least one of the following: The size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area of ​​the multi-dimensional data in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the multi-dimensional data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

5. The data processing device according to any one of claims 1 to 4, wherein the data processing device further comprises an external memory for storing multi-dimensional data, the data conversion instruction comprises a first descriptor and a second descriptor, and the data conversion circuit is configured to: Reading the multi-dimensional data from an external memory according to the first descriptor so as to store the data into the data cache circuit; and The multi-dimensional data in the data cache circuit is read into the external memory according to the second descriptor.

6. The data processing device according to any one of claims 1 to 4, wherein the data conversion circuit is configured to perform storage and reading operations on the multi-dimensional data to perform one of the following conversion operations on the multi-dimensional data: Data mirroring operations, multi-angle data rotation operations, or data transposition operations.

7. The data processing apparatus according to claim 1 , wherein the data conversion circuit is configured to: According to the operation parameters, storage and reading operations are performed on one or more parts of the multi-dimensional data in the data cache circuit to implement data conversion on the one or more parts of the multi-dimensional data.

8. The data processing apparatus according to claim 1 , wherein the data conversion circuit is configured to: According to the operating parameters, a plurality of parts of the converted multi-dimensional data read from the data cache circuit are spliced ​​for output.

9. The data processing apparatus according to claim 1 , wherein the data conversion circuit is configured to: Based on the operating parameters, a plurality of portions of the unconverted multi-dimensional data read from the data cache circuit are combined for output.

10. An integrated circuit chip comprising the data processing device according to any one of claims 1 to 9.

11. An electronic device comprising the integrated circuit chip according to claim 10.

12. A board comprising the integrated circuit chip according to claim 10.

13. A method implemented by a data processing device, wherein the data processing device includes a data cache circuit and a data conversion circuit, the method comprising: Using the data cache circuit to cache multi-dimensional data; as well as Using the data conversion circuit to perform storage and reading operations on the multi-dimensional data in the data cache circuit according to the data conversion instruction, so as to realize data conversion of the multi-dimensional data, The data conversion instruction includes a descriptor for indicating the shape of the multi-dimensional data, and the descriptor is used to determine the storage address of the corresponding multi-dimensional data. wherein the data conversion circuit is used to perform storage and reading operations on the multi-dimensional data according to the storage address; wherein the data conversion instruction includes an operating parameter, and the method includes using the data conversion circuit to perform data conversion on the multi-dimensional data according to the operating parameter; The data conversion circuit is used to perform the following operations according to the operating parameters: storing the multi-dimensional data into the data cache circuit in the order of the first dimension of the multi-dimensional data to form an intermediate matrix; as well as Reading the intermediate matrix from the data cache circuit in order of the second dimension for output; The descriptor includes data amount information and inter-dimensional offset information for performing storage and reading operations on each dimension of multi-dimensional data, and wherein the data amount information and inter-dimensional offset information are determined according to address parameters and shape parameters in the descriptor.

14. The method according to claim 13, wherein the data conversion instruction includes an identifier of a descriptor and / or content of the descriptor, and the content of the descriptor includes at least one shape parameter representing the shape of the multidimensional data and at least one address parameter representing the address of the multidimensional data. 15 . The method according to claim 14 , wherein the address parameter of the multi-dimensional data comprises a reference address of a data reference point of the descriptor in a data storage space of the multi-dimensional data.

16. The method according to claim 15, wherein the shape parameter of the multi-dimensional data comprises at least one of the following: The size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area of ​​the multi-dimensional data in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the multi-dimensional data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

17. The method according to any one of claims 13 to 16, wherein the data processing device further comprises an external memory for storing multi-dimensional data, the data conversion instruction comprises a first descriptor and a second descriptor, and the method uses the data conversion circuit to perform the following steps: Reading the multi-dimensional data from an external memory according to the first descriptor so as to store the data into the data cache circuit; and The multi-dimensional data in the data cache circuit is read into the external memory according to the second descriptor.

18. The method according to any one of claims 13 to 16, wherein the data conversion circuit is used to perform storage and reading operations on the multi-dimensional data to perform one of the following conversion operations on the multi-dimensional data: Data mirroring operations, multi-angle data rotation operations, or data transposition operations.

19. The method of claim 13, wherein the data conversion circuit is used to perform the following steps: According to the operation parameters, storage and reading operations are performed on one or more parts of the multi-dimensional data in the data cache circuit to implement data conversion on the one or more parts of the multi-dimensional data.

20. The method of claim 13, wherein the data conversion circuit is used to perform the following steps: According to the operating parameters, a plurality of parts of the converted multi-dimensional data read from the data cache circuit are spliced ​​for output.

21. The method of claim 13, wherein the data conversion circuit is used to perform the following steps: Based on the operating parameters, a plurality of portions of the unconverted multi-dimensional data read from the data cache circuit are combined for output.

Images