Matrix multiplication operation method, electronic device and storage medium

Abstract

A matrix multiplication operation method, device, chip, electronic device and storage medium are applied to the field of data processing technology, including: obtaining data of unconventional data types in data to be subjected to matrix multiplication operation; converting the data of unconventional data types into data of conventional data types; performing matrix multiplication operation on the data of conventional data types instead of the data of unconventional data types. The calculation of unconventional data types such as int15, int31 and int63 can be supported.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a matrix multiplication operation method, an electronic device and a storage medium. Background Art

[0002] Currently, in order to improve the computing performance of the chip, the input data is converted from floating point numbers to fixed point numbers, and the fixed point number bit width is increased to improve the accuracy of chip training. In some chips, since calculations related to conventional data types such as int32 are not supported, unconventional data types such as int24 and int31 are used for related calculations. However, the matrix multiplication operator currently does not support calculation operations of unconventional data types such as int31. Summary of the invention

[0003] Based on this, it is necessary to provide a matrix multiplication method, electronic device and storage medium to address the above technical problems.

[0004] A first aspect of an embodiment of the present disclosure provides a matrix multiplication operation method, including:

[0005] Acquire data to be subjected to matrix multiplication operation, wherein the data includes data of unconventional data types;

[0006] Converting the data of the unconventional data type into data of the conventional data type;

[0007] The data of the regular data type is used to replace the data of the irregular data type to perform a matrix multiplication operation.

[0008] In a possible implementation, the data of the unconventional data type may be converted into an operation of two data of the conventional data type.

[0009] In a possible implementation, the data of the unconventional data type is an integer including a sign bit and a data bit, the data bit of the data of the unconventional data type is n+m bits, and converting the data of the unconventional data type into data of the conventional data type includes:

[0010] The data of the non-conventional data type is split into a data of the conventional data type with the sign bit and n data bits and a data of the conventional data type with the sign bit and m data bits.

[0011] In one possible implementation, the n-bit data of the regular data type with n data bits is the upper n-bit data of the data of the unconventional data type, and the m-bit data of the regular data type with m data bits is the lower m-bit data of the data of the unconventional data type.

[0012] In a possible implementation, the data of the non-conventional data type is I, the data of the conventional data type with the sign bit and n data bits is Ih, and the data of the conventional data type with the sign bit and m data bits is Il, then:

[0013] I=Ih*2 m +Il.

[0014] In a possible implementation, in the matrix multiplication operation, the data type of data in at least one matrix is ​​an unconventional data type.

[0015] In a possible implementation, when the data type of data in a matrix is ​​an unconventional data type, performing a matrix multiplication operation by replacing the data of the unconventional data type with the data of the conventional data type includes:

[0016] An operation of converting data of an unconventional data type in the matrix into two data of a regular data type is performed to replace the data of the unconventional data type with a matrix multiplication operation.

[0017] In a possible implementation, when the data types of the data in the two matrices are both unconventional data types, performing a matrix multiplication operation by replacing the data of the unconventional data type with the data of the conventional data type includes:

[0018] The data of the unconventional data type in the two matrices are respectively converted into two data of the regular data type, and the matrix multiplication operation is performed on the data of the corresponding unconventional data type.

[0019] In a possible implementation, the conventional data types include int8, int16, int32, and int64;

[0020] The unconventional data types include int15, int23, int31, int39, int47, int63, int71, int79, int97 or int127.

[0021] A second aspect of the present disclosure provides an electronic device, including:

[0022] A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the matrix multiplication method provided in the first aspect of the embodiment of the present disclosure when executing the program.

[0023] A third aspect of an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the matrix multiplication method provided by the first aspect of the embodiment of the present disclosure is implemented.

[0024] In an embodiment of the present disclosure, data to be subjected to matrix multiplication operation is obtained, wherein the data includes data of unconventional data types; the data of unconventional data types are converted into data of regular data types, and the data of regular data types are used to replace the data of unconventional data types for matrix multiplication operation, thereby supporting matrix multiplication operation of data of unconventional data types. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A schematic diagram of a processor of a matrix multiplication operation method according to an embodiment of the present disclosure is shown;

[0027] Figure 2 A flowchart of a matrix multiplication operation method provided in one embodiment of the present disclosure;

[0028] Figure 3 A flowchart of a matrix multiplication operation method provided in one embodiment of the present disclosure;

[0029] Figure 4 A flowchart of a matrix multiplication operation method provided in one embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of the structure of a matrix multiplication operation device provided in one embodiment of the present disclosure;

[0031] Figure 6 A schematic diagram of the hardware structure of an electronic device is shown.

[0032] Figure 7a , Figure 7b A schematic diagram showing the structure of a combined processing device according to an embodiment of the present disclosure is shown;

[0033] Figure 8 A schematic structural diagram of a board according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] In order to make the purpose, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0035] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The words "a", "an (kind)" and "the" used herein should also include the meanings of "multiple" and "multiple", unless the context clearly indicates otherwise. In addition, the terms "including", "comprising" and the like used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0036] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0037] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but not be limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but not be limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). Those skilled in the art should also understand that any transitional conjunctions and / or phrases that substantially indicate two or more optional items, whether in the specification, claims, or drawings, should be understood to give the possibility of including one of these items, either of these items, or both of these items. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B", or "A and B".

[0038] Some block diagrams and / or flow charts are shown in the accompanying drawings. It should be understood that some blocks or combinations thereof in the block diagrams and / or flow charts may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that these instructions, when executed by the processor, may create a device for implementing the functions / operations described in these block diagrams and / or flow charts.

[0039] Therefore, the technology of the present disclosure can be implemented in the form of hardware and / or software (including firmware, microcode, etc.). In addition, the technology of the present disclosure can take the form of a computer program product on a computer-readable medium storing instructions, which can be used by an instruction execution system or in combination with an instruction execution system. In the context of the present disclosure, a computer-readable medium can be any medium that can contain, store, transmit, propagate, or transmit instructions. For example, a computer-readable medium can include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, device, or propagation medium. Specific examples of computer-readable media include: magnetic storage devices, such as magnetic tapes or hard disks (HDDs); optical storage devices, such as compact disks (CD-ROMs); memories, such as random access memories (RAMs) or flash memory; and / or wired / wireless communication links.

[0040] In the embodiments provided by the present disclosure, when there are data of unconventional data types in a matrix multiplication operation, the data of the unconventional data types are split into data of regular data types, and then the data of the regular data types are used to replace the data of the unconventional data types to perform a matrix multiplication operation, thereby supporting matrix multiplication operations of the data of unconventional data types.

[0041] The typical application scenario of the following embodiments of the present disclosure is that when two matrices are multiplied in a computer, if there is data of a non-conventional data type in the two matrices, the data of the non-conventional data type is converted into data of a conventional data type for calculation. For a description of the specific technical solution, see the following embodiments.

[0042] The matrix multiplication operation method according to the embodiment of the present disclosure can be applied to a processing device such as a processor, which can be a general-purpose processor, such as a CPU (Central Processing Unit), or an artificial intelligence processor (IPU) for performing artificial intelligence operations. Artificial intelligence operations may include machine learning operations, brain-like operations, etc. Among them, machine learning operations include neural network operations, k-means operations, support vector machine operations, etc. The artificial intelligence processor may, for example, include one or a combination of GPU (Graphics Processing Unit), NPU (Neural-Network Processing Unit), DSP (Digital Signal Process), and Field Programmable Gate Array (Field-Programmable Gate Array, FPGA) chips. The present disclosure does not limit the specific type of processor.

[0043] In a possible implementation, the processor mentioned in the present disclosure may include multiple processing units, each of which can independently run various assigned tasks, such as: computing tasks, pooling tasks or fully connected tasks, etc. The present disclosure does not limit the processing units and the tasks run by the processing units.

[0044] Figure 1 A schematic diagram of a processor of a matrix multiplication operation method according to an embodiment of the present disclosure is shown. Figure 1 As shown, the processor 100 includes a plurality of processing units 101 and a storage unit 102, and the plurality of processing units 101 are used to execute operation instructions, and each processing unit can perform matrix multiplication operations independently, and optionally, the plurality of processing units can also perform matrix multiplication operations in parallel. The storage unit 102 is used to store data, and may include a random access memory (RAM) and a register file, which are used to store data required for matrix operations, including data of conventional data types and data of unconventional data types. The plurality of processing units 101 in the processor 100 can share part of the storage space, such as sharing part of the RAM storage space and the register file, and can also have their own storage space at the same time.

[0045] See also Figure 2 , Figure 2 The present invention provides a flowchart of a matrix multiplication operation method according to an embodiment of the present invention. The method is applied to the above-mentioned processor, and the method mainly includes the following steps:

[0046] Step S201: The processor obtains data to be subjected to matrix multiplication operation, wherein the data includes data of unconventional data types;

[0047] Step S202: The processor converts the data of the unconventional data type into data of the conventional data type;

[0048] Step S203: The processor replaces the data of the unconventional data type with the data of the conventional data type to perform a matrix multiplication operation.

[0049] Matrix multiplication refers to multiplying two matrices. Let A be an i×k matrix and B be a k×j matrix. Then the i×j matrix C is called the product of the matrices A and B, denoted as C=AB. The data in the i-th row and j-th column of the matrix C is: Among them, i, k, and j are all positive integers.

[0050] Optionally, the data to be subjected to matrix multiplication operation may be a one-dimensional matrix, a two-dimensional matrix, or a multi-dimensional matrix, which is not limited in the present disclosure.

[0051] The regular data type refers to a basic data type, and may be, for example, int8, int16, int32, int64, and the like.

[0052] An unconventional data type refers to a data type other than a conventional data type, for example, int15, int23, int31, int39, int47, int63, int71, int79, int97 or int127.

[0053] It is understandable that when both data to be matrix multiplied are of regular data type, the processor can perform matrix multiplication on them normally. When there is data of unconventional data type in the two data to be matrix multiplied, the scheme of the present disclosure can be implemented to realize matrix multiplication of data of unconventional data type.

[0054] According to an embodiment of the present disclosure, when there is data of unconventional data types in a matrix multiplication operation, the processor converts the unconventional data types into regular data types, and uses the data of regular data types to replace the data of unconventional data types to perform matrix multiplication operations, so that matrix multiplication operations of data of unconventional data types can be performed.

[0055] In a possible implementation, the processor may convert the data of the non-conventional data type into two data of the conventional data type, wherein the conventional data types of the two data of the conventional data type may be the same or different.

[0056] According to the embodiment of the present disclosure, the processor can split the data of the unconventional data type into two data of the conventional data type. For example, int15 can be split into two identical conventional data types int8, int23 can be split into two different conventional data types int8 and int24, int31 can be split into two identical conventional data types int16, int47 can be split into two different conventional data types int16 and int31, int63 can be split into two identical conventional data types int32, and so on.

[0057] In this embodiment, any data of an unconventional data type that can be split into two data of a regular data type can be subjected to a matrix multiplication operation using the operation method provided by the present disclosure.

[0058] In a possible implementation, the data of the unconventional data type is an integer including a sign bit and a data bit, and the data bit of the data of the unconventional data type is n+m bits, where n and m are positive integers. Step S202 includes: the processor splits the data of the unconventional data type into a data of the conventional data type with the sign bit and n data bits and a data of the conventional data type with the sign bit and m data bits.

[0059] It can be understood that the sign bits of the two regular data types obtained after the processor splits the data multiplex the sign bits of the data of the irregular data type.

[0060] Optionally, the present disclosure does not limit the number of sign bits of data of unconventional data types, which can be 1 bit, 2 bits, 3 bits, etc., and also does not limit the positive and negative signs represented by the sign bit. For example, when the sign bit is 1 bit, 0 represents positive, 1 represents negative, or 0 represents negative, 1 represents positive. In the present disclosure, a 1-bit sign bit is taken as an example to schematically illustrate the present disclosure.

[0061] According to this embodiment, for example, the number of bits of the data of the unconventional data type int39 is 39, which includes 1 sign bit and 38 data bits. Then the processor can split the data int39 into a data of a conventional data type with 1 sign bit and 31 data bits (32 bits in total) and a data of a conventional data type with 1 sign bit and 7 data bits (8 bits in total), where n is 31 and m is 7, or n is 7 and m is 31. For another example, the number of bits of the data of the unconventional data type int71 is 71, which includes 1 sign bit and 70 data bits. Then it can be split into a data of a conventional data type with 1 sign bit and 63 data bits (64 bits in total) and a data of a conventional data type with 1 sign bit and 7 data bits (8 bits in total), where n is 63 and m is 7, or n is 7 and m is 63. In this way, the operation of converting data of an unconventional data type into data of two regular data types can solve the problem of not supporting related calculation operations of data of unconventional data types.

[0062] In a possible implementation, the n-bit data of the data of the conventional data type with n data bits is the high n-bit data of the data of the unconventional data type, and the m-bit data of the data of the conventional data type with m data bits is the low m-bit data of the data of the unconventional data type. Wherein, the data bits of the data of the unconventional data type are n+m bits, the high n-bit data refers to the high n bits of the data of the unconventional data type, and the low m-bit data refers to the low m bits of the data of the unconventional data type.

[0063] In a possible implementation, let the data of the unconventional data type be I, the data of the conventional data type with the sign bit and n data bits be Ih, and the data of the conventional data type with the sign bit and m data bits be Il, then the processor splits the data of the unconventional data type I into:

[0064] I=Ih*2 m +Il.

[0065] It can be understood that the data of the unconventional data type can be represented by multiplying the converted data of the regular data type (with the high-order data of the unconventional data type) by 2 to the power of the number of low-order data bits of the unconventional data type, and then adding the data of the regular data type with the sign bit and low-order data bits.

[0066] In a possible implementation, in the matrix multiplication operation, the data type of data in at least one matrix is ​​an unconventional data type.

[0067] Exemplarily, let the two matrices to be subjected to matrix multiplication be A and B, then the data in matrix A is of unconventional data type and the data in matrix B is of regular data type, or the data in matrix A is of regular data type and the data in matrix B is of unconventional data type, or the data in both matrix A and matrix B are of unconventional data type.

[0068] In one possible implementation, see Figure 3 When the data type of data in a matrix is ​​an unconventional data type, the step S203 includes: S2031, the processor converts the data of the unconventional data type in the matrix into two data of regular data types, replacing the data of the unconventional data type for matrix multiplication operation.

[0069] Let the matrices of the two data be represented by A and B, and the matrix obtained by performing matrix multiplication operation on the two data be represented by C, C ij Represents the data of the i-th row and j-th column of matrix C, A ik represents the data of the i-th row and k-th column of matrix A, B kj represents the data of the kth row and jth column of matrix B, then:

[0070] When the data type of one matrix A of the two matrices is an unconventional data type and the data type of the other matrix B is a conventional data type:

[0071]

[0072] Among them, because A ik The data of the regular data type with a sign bit and high n1 data bits is Ah. ik , the data of the conventional data type with a sign bit and the lower m1 data bit is Al ik ,but

[0073] When one of the two matrices A ik The data type of the matrix B is a regular data type. kj When the data type is an unconventional data type:

[0074]

[0075] Among them, because B kj The data of the regular data type with a sign bit and high n2 data bits is Bh. ik , the data of the general data type with a sign bit and the lower m2 data bits is Bl ik ,but

[0076] It is understandable that when the data type of one of the two data is an unconventional data type and the data type of the other data is a conventional data type, there are the following possible combinations, but not limited to the following combinations, and the present disclosure does not make any limitation on this. Specifically, the data type of the unconventional data type is any one of int15, int23, int31, int39, int47, int63, int71, int79, int97 or int127, and the data type of the conventional data type is any one of int8, int16, int32 or int64, etc.

[0077] In one possible implementation, see Figure 4 When the data types of the data in the two matrices are both unconventional data types, the step S203 includes: S2032, the processor converts the data of the unconventional data type in the two matrices into two operations of data of regular data types respectively, and replaces the corresponding data of the unconventional data type for matrix multiplication operation.

[0078] Let the matrices of the two data be represented by A and B, and the matrix obtained by performing matrix multiplication operation on the two data be represented by C, C ij Represents the data of the i-th row and j-th column of matrix C, A ik represents the data of the i-th row and k-th column of matrix A, B kj represents the data of the kth row and jth column of matrix B, then:

[0079]

[0080] Among them, because A ik The data of the regular data type with a sign bit and high n1 data bits is Ah. ik , the data of the conventional data type with a sign bit and the lower m1 data bit is Al ik , Because B kj The data of the regular data type with a sign bit and high n2 data bits is Bh. ik , the data of the general data type with a sign bit and the lower m2 data bits is Bl ik ,but

[0081] It is understandable that when the data types of the two data to be multiplied are both unconventional data types, there are the following possible combinations, but are not limited to the following combinations, and the present disclosure does not make any restrictions on this. Specifically, the data types of the two data are any one of int15, int23, int31, int39, int47, int63, int71, int79, int97 or int127, or one of the two data is any one of the above, and the other data is any one of the above.

[0082] In one possible implementation, conventional data types include int8, int16, int32, int64; unconventional data types include int15, int23, int31, int39, int47, int63, int71, int79, int97 or int127.

[0083] Optionally, when there are other conventional data types, such as int128, int256, etc., unconventional data types may also include int135, int143, int159, int191, int254, int263, int271, int287, int319, int383, int511, and int767.

[0084] The present disclosure is not limited to the above-mentioned data for data of conventional data types and data of unconventional data types, and the present disclosure does not make any limitation on this.

[0085] See also Figure 5 , Figure 5 : is a schematic diagram of the structure of a matrix multiplication operation device provided by an embodiment of the present disclosure, and the device mainly includes:

[0086] An acquisition module 501 is used to acquire data to be subjected to matrix multiplication operation, wherein the data includes data of unconventional data types;

[0087] A conversion module 502, configured to convert the data of the unconventional data type into data of the conventional data type;

[0088] The operation module 503 is used to perform a matrix multiplication operation by replacing the data of the unconventional data type with the data of the conventional data type.

[0089] In a possible implementation, the data of the unconventional data type may be converted into an operation of two data of the conventional data type.

[0090] In one possible implementation, the data of the unconventional data type is an integer including a sign bit and a data bit, and the data bits of the data of the unconventional data type are set to n+m bits. The conversion module 502 is specifically used to split the data of the unconventional data type into a data of a regular data type with the sign bit and n data bits and a data of a regular data type with the sign bit and m data bits.

[0091] In one possible implementation, the n-bit data of the regular data type with n data bits is the upper n-bit data of the data of the unconventional data type, and the m-bit data of the regular data type with m data bits is the lower m-bit data of the data of the unconventional data type.

[0092] In a possible implementation, let the data of the non-conventional data type be I, the data of the conventional data type with the sign bit and n data bits be Ih, and the data of the conventional data type with the sign bit and m data bits be Il, then:

[0093] I=Ih*2 m +Il.

[0094] In a possible implementation, in the matrix multiplication operation, the data type of data in at least one matrix is ​​an unconventional data type.

[0095] In one possible implementation, when the data type of data in a matrix is ​​an unconventional data type, the conversion module 502 is specifically used to convert the data of the unconventional data type in the matrix into two data of a regular data type, replacing the data of the unconventional data type for matrix multiplication operation.

[0096] In one possible implementation, when the data types of the data in the two matrices are both unconventional data types, the conversion module 502 is specifically used to convert the data of the unconventional data types in the two matrices into two data of regular data types, respectively, replacing the corresponding data of the unconventional data types for matrix multiplication operations.

[0097] In one possible implementation, the conventional data types include int8, int16, int32, int64; the unconventional data types include int15, int23, int31, int39, int47, int63, int71, int79, int97 or int127.

[0098] It should be noted that Figure 5 For details not shown in the embodiment, please refer to Figures 1 to 4The description of the relevant parts of the illustrated embodiment will not be repeated here.

[0099] It should be understood that the above-mentioned device embodiments are only illustrative, and the device of the present disclosure can also be implemented in other ways. For example, the division of units / modules described in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0100] In addition, unless otherwise specified, each functional unit / module in each embodiment of the present disclosure may be integrated into one unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of a software program module.

[0101] If the integrated unit / module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. Unless otherwise specified, the artificial intelligence processor may be any appropriate hardware processor, such as a CPU, a GPU, an FPGA, a DSP, an ASIC, etc. Unless otherwise specified, the storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory RRAM (Resistive Random Access Memory), a dynamic random access memory DRAM (Dynamic Random Access Memory), a static random access memory SRAM (Static Random-Access Memory), an enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), a high-bandwidth memory HBM (High-Bandwidth Memory), a hybrid memory cube HMC (Hybrid Memory Cube), etc.

[0102] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0103] The embodiment of the present disclosure also provides a chip, which includes the above-mentioned matrix multiplication operation device.

[0104] The disclosed embodiment also provides an electronic device, which includes the above chip. The electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a means of transportation, a household appliance and / or a medical device. The means of transportation include an airplane, a ship and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric lamp, a gas stove, and a range hood; the medical device includes a nuclear magnetic resonance apparatus, a B-ultrasound apparatus and / or an electrocardiograph.

[0105] The present disclosure also provides an electronic device. Figure 6 , Figure 6 The electronic device described in the embodiment of the present disclosure includes: a memory 61, a processor 62, and a computer program stored in the memory 61 and executable on the processor. When the processor executes the program, the aforementioned Figures 2 to 4 The matrix multiplication operation method described in the embodiment shown in the figure. Wherein, the processor 62 can be as follows Figure 1 Processor shown.

[0106] Furthermore, the electronic device also includes:

[0107] At least one input device 63 ; at least one output device 64 .

[0108] The memory 61 , processor 62 , input device 63 and output device 64 are connected via a bus 65 .

[0109] The input device 63 may be a camera, a touch panel, a physical button or a mouse, etc. The output device 64 may be a display screen.

[0110] The memory 61 may be a high-speed random access memory (RAM) memory or a non-volatile memory, such as a disk memory. The memory 61 is used to store a set of executable program codes, and the processor 62 is coupled to the memory 61 .

[0111] The processor 62 may be a general-purpose processor, such as a central processing unit (CPU), or an artificial intelligence processor for performing artificial intelligence operations. Artificial intelligence operations may include machine learning operations, brain-like operations, etc. Among them, machine learning operations include neural network operations, k-means operations, support vector machine operations, etc. The artificial intelligence processor may, for example, include one or a combination of a graphics processing unit, a neural network processing unit, a digital signal processing unit, and a field programmable gate array chip. The present disclosure does not limit the specific type of the processor.

[0112] The present disclosure also provides a computer-readable storage medium. The computer-readable storage medium may be disposed in the electronic device in the above embodiments. The computer-readable storage medium may be the above Figure 6 The electronic device in the embodiment shown. The computer readable storage medium stores a computer program, which, when executed by the processor, implements the aforementioned Figures 2 to 4 The matrix multiplication operation method described in the illustrated embodiment. Further, the computer storage medium may also be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0113] Figure 7a FIG. 2 is a block diagram of a combined processing device according to an embodiment of the present disclosure. Figure 7a As shown, the combined processing device includes the above-mentioned matrix multiplication operation device, a universal interconnection interface and other processing devices. The matrix multiplication operation device interacts with other processing devices to jointly complete the operation specified by the user.

[0114] Other processing devices include one or more types of processors such as central processing unit (CPU), graphics processing unit (GPU), neural network processor, and other general / special processors. There is no limit on the number of processors included in other processing devices. Other processing devices serve as interfaces between the matrix multiplication operation device and external data and control, including data handling, to complete basic control of the matrix multiplication operation device such as starting and stopping; other processing devices can also cooperate with the matrix multiplication operation device to complete the operation task.

[0115] The universal interconnection interface is used to transmit data and control instructions between the matrix multiplication operation device and other processing devices. The matrix multiplication operation device obtains the required input data from other processing devices and writes it into the storage device on the matrix multiplication operation device chip; it can obtain control instructions from other processing devices and write them into the control cache on the matrix multiplication operation device chip; it can also read the data in the storage module of the matrix multiplication operation device and transmit it to other processing devices.

[0116] Figure 7b FIG. 1 is a block diagram of a combined processing device according to an embodiment of the present disclosure. In a possible implementation, Figure 7b As shown, the combined processing device may also include a storage device, which is connected to the matrix multiplication operation device and the other processing device respectively. The storage device is used to store data in the matrix multiplication operation device and the other processing device, and is particularly suitable for data that cannot be fully stored in the internal storage of the matrix multiplication operation device or other processing devices.

[0117] The combined processing device can be used as a SOC chip system for mobile phones, robots, drones, video surveillance equipment and other devices, effectively reducing the core area of ​​the control part, improving the processing speed, and reducing the overall power consumption. In this case, the universal interconnection interface of the combined processing device is connected to certain components of the device. Certain components include cameras, displays, mice, keyboards, network cards, and wifi interfaces.

[0118] The present disclosure provides a machine learning chip, which includes the above-mentioned matrix multiplication operation device or combination processing device.

[0119] The present disclosure provides a machine learning chip packaging structure, which includes the above-mentioned machine learning chip.

[0120] The present disclosure provides a board card. Figure 8 FIG. 2 shows a schematic diagram of the structure of a board according to an embodiment of the present disclosure. Figure 8As shown, the board includes the above-mentioned machine learning chip packaging structure or the above-mentioned machine learning chip. In addition to the machine learning chip 389, the board may also include other supporting components, including but not limited to: a storage device 390, an interface device 391 and a control device 392.

[0121] The memory device 390 is connected to the machine learning chip 389 (or the machine learning chip in the machine learning chip package structure) via a bus for storing data. The memory device 390 may include multiple groups of storage units 393. Each group of storage units 393 is connected to the machine learning chip 389 via a bus. It is understood that each group of storage units 393 may be DDR SDRAM (English: Double Data Rate SDRAM, double rate synchronous dynamic random access memory).

[0122] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

[0123] In one embodiment, the storage device 390 may include 4 groups of storage units 393. Each group of storage units 393 may include multiple DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include 4 72-bit DR4 controllers, 64 bits of the above 72-bit DDR4 controllers are used to transmit data, and 8 hits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units 393, the theoretical bandwidth of data transmission can reach 25600B / s.

[0124] In one embodiment, each group of storage units 393 includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DR can transmit data twice in one clock cycle. A controller for controlling DDR is provided in the machine learning chip 389 to control the data transmission and data storage of each storage unit 393.

[0125] The interface device 391 is electrically connected to the machine learning chip 389 (or the machine learning chip in the machine learning chip packaging structure). The interface device 391 is used to realize data transmission between the machine learning chip 389 and an external device (such as a server or a computer). For example, in one embodiment, the interface device 391 can be a standard PCIE interface. For example, the data to be processed is transmitted from the server to the machine learning chip 289 through the standard PCIE interface to realize data transfer. Preferably, when the PCIE 3.00X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB / s. In another embodiment, the interface device 391 can also be other interfaces. The present disclosure does not limit the specific forms of expression of the above-mentioned other interfaces. The interface device can realize the switching function. In addition, the calculation results of the machine learning chip are still transmitted back to the external device (such as a server) by the interface device.

[0126] The control device 392 is electrically connected to the machine learning chip 389. The control device 392 is used to monitor the state of the machine learning chip 389. Specifically, the machine learning chip 389 and the control device 392 can be electrically connected through an SPI interface. The control device 392 may include a single-chip microcomputer (Micro Controller Unit, MCU). For example, the machine learning chip 389 may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the machine learning chip 389 can be in different working states such as multi-load and light load. The control device can be used to control the working states of multiple processing chips, multiple processing and / or multiple processing circuits in the machine learning chip.

[0127] The above content can be better understood according to the following terms:

[0128] Clause 1. A matrix multiplication method, comprising: obtaining data to be subjected to a matrix multiplication operation, wherein the data includes data of an unconventional data type;

[0129] Converting the data of the unconventional data type into data of the conventional data type;

[0130] The data of the regular data type is used to replace the data of the irregular data type to perform a matrix multiplication operation.

[0131] Clause 2. According to the matrix multiplication method described in Clause 1, the data of the unconventional data type can be converted into an operation of two data of the regular data type.

[0132] Clause 3. According to the matrix multiplication method of Clause 2, the data of the unconventional data type is an integer including a sign bit and a data bit, the data bit of the data of the unconventional data type is n+m bits, and the converting of the data of the unconventional data type into the data of the conventional data type comprises:

[0133] The data of the non-conventional data type is split into a data of the conventional data type with the sign bit and n data bits and a data of the conventional data type with the sign bit and m data bits.

[0134] Clause 4. According to the matrix multiplication method described in Clause 3, the n-bit data of the data of the regular data type with the n-bit data bits is the high n-bit data of the data of the unconventional data type, and the m-bit data of the data of the regular data type with the m-bit data bits is the low m-bit data of the data of the unconventional data type.

[0135] Clause 5. According to the matrix multiplication method described in Clause 4, the data of the non-conventional data type is I, the data of the conventional data type with the sign bit and n data bits is Ih, and the data of the conventional data type with the sign bit and m data bits is Il, then:

[0136] I=Ih*2 m +Il.

[0137] Clause 6. According to the matrix multiplication method described in Clause 2, in the matrix multiplication operation, the data type of the data in at least one matrix is ​​a non-conventional data type.

[0138] Clause 7. According to the matrix multiplication method described in Clause 6, when the data type of data in a matrix is ​​an unconventional data type, performing the matrix multiplication operation by replacing the data of the unconventional data type with the data of the conventional data type comprises:

[0139] An operation of converting data of an unconventional data type in the matrix into two data of a regular data type is performed to replace the data of the unconventional data type with a matrix multiplication operation.

[0140] Clause 8. According to the matrix multiplication method described in Clause 6, when the data types of the data in the two matrices are both unconventional data types, performing the matrix multiplication operation by replacing the data of the unconventional data type with the data of the conventional data type comprises:

[0141] The data of the unconventional data type in the two matrices are respectively converted into two data of the regular data type, and the matrix multiplication operation is performed on the data of the corresponding unconventional data type.

[0142] Clause 9. The matrix multiplication method according to Clause 1, wherein the conventional data types include int8, int16, int32, and int64;

[0143] The unconventional data types include int15, int23, int31, int39, int47, int63, int71, int79, int97 or int127.

[0144] Clause 10. An electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, each step of the matrix multiplication method described in any one of Clauses 1 to 9 is implemented.

[0145] Clause 11. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the computer program implements each step of the matrix multiplication method described in any one of Clauses 1 to 9.

[0146] It should be noted that, for the convenience of description, the aforementioned method embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0147] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0148] The above is a detailed description of the present disclosure. For those skilled in the art, according to the ideas of the embodiments of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A matrix multiplication method, characterized in that: include: Acquire data to be subjected to matrix multiplication operation, wherein the data includes data of unconventional data types; Converting the data of the unconventional data type into data of the conventional data type; The data of the conventional data type is used to replace the data of the unconventional data type to perform a matrix multiplication operation; the data of the unconventional data type can be converted into an operation of two data of the conventional data type, the conventional data type refers to a basic data type, and the unconventional data type refers to a data type other than the conventional data type.

2. The matrix multiplication method according to claim 1, characterized in that: The data of the unconventional data type includes a sign bit and a data bit, and the data bit of the data of the unconventional data type is The converting of the data of the unconventional data type into data of the conventional data type comprises: Split the data of the unconventional data type into a data frame with the sign bit and The conventional data type of data with a bit with the sign bit and Operates on data of regular data type bit by bit.

3. The matrix multiplication method according to claim 2, characterized in that: Said Bit data bits of regular data types The bit data is the high bit of the data of the unconventional data type. bit data, the Bit data bits of regular data types The low bit data is the data of the unconventional data type. bit data.

4. The matrix multiplication method according to claim 3, characterized in that: The data of the unconventional data type is , with the sign bit and The general data type of the bit data is , with the sign bit and The general data type of the bit data is ,but: 。 5. The matrix multiplication method according to claim 1, characterized in that: In the matrix multiplication operation, the data type of data in at least one matrix is ​​an unconventional data type.

6. The matrix multiplication method according to claim 5, characterized in that: When the data type of data in a matrix is ​​an unconventional data type, performing a matrix multiplication operation by replacing the data of the unconventional data type with the data of the conventional data type includes: An operation of converting data of an unconventional data type in the matrix into two data of a regular data type is performed to replace the data of the unconventional data type with a matrix multiplication operation.

7. The matrix multiplication method according to claim 5, characterized in that: When the data types of the data in the two matrices are both unconventional data types, performing a matrix multiplication operation by replacing the data of the unconventional data type with the data of the conventional data type includes: The data of the unconventional data type in the two matrices are respectively converted into two data of the regular data type, and the matrix multiplication operation is performed on the data of the corresponding unconventional data type.

8. The matrix multiplication method according to claim 1, characterized in that: The conventional data types include int8, int16, int32, and int64; The unconventional data types include int15, int23, int31, int39, int47, int63, int71, int79, int97 or int127.

9. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, each step of the matrix multiplication method described in any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step of the matrix multiplication method described in any one of claims 1 to 8 is implemented.

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