A SoC chip simulation verification method, device, equipment and storage medium

Abstract

The present invention discloses a SoC chip simulation verification method, device, equipment and storage medium, the method comprising: in the simulation verification process of the SoC chip, executing a boot loader in the flash memory medium of the SoC chip to realize the simulation verification operation before code relocation; after the simulation verification operation before code relocation is completed, determining that the main memory of the SoC chip has completed initialization during the simulation verification operation before code relocation, migrating the boot loader to the main memory to realize code relocation, executing the boot loader in the main memory, and after enabling the function of the main memory corresponding data Cache by executing the boot loader in the memory, realizing other simulation verification operations after code relocation based on the data Cache. It can be seen that the present application can reduce the time of simulating the boot loader, thereby improving the simulation verification speed of the SoC chip and improving the chip development efficiency of the SoC chip.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and more specifically, to a SoC chip simulation verification method, device, equipment and storage medium. Background Art

[0002] SoC technology integrates key system components onto a single chip, creating a miniaturized system. An SoC chip can include a processor, cache, memory, digital IP cores, analog IP cores, and more. Software and hardware co-design and verification are key technologies in SoC chips. SoC chips run an operating system, most commonly embedded Linux. When an SoC starts up, it first executes the bootloader and then calls the operating system kernel.

[0003] For system-level simulation verification of SoC chips, in order to more comprehensively verify the correctness of SoC startup, the bootloader program is usually placed in the simulation verification environment as a simulation stimulus for verification; however, since the simulation bootloader takes a long time, the simulation verification of the SoC chip is slow, which reduces the chip development efficiency of the SoC chip. Summary of the Invention

[0004] The purpose of the present invention is to provide a SoC chip simulation verification method, device, equipment and storage medium, which can reduce the time of simulating the boot loader, thereby increasing the simulation verification speed of the SoC chip and improving the chip development efficiency of the SoC chip.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A SoC chip simulation verification method, comprising:

[0007] During the simulation verification process of the SoC chip, a boot loader is executed in the flash memory medium of the SoC chip to implement simulation verification operations before code relocation;

[0008] After the simulation verification operation before code relocation is completed, it is determined that the main memory of the SoC chip has been initialized during the simulation verification operation before code relocation, the boot loader is migrated to the main memory to realize code relocation, and the boot loader is executed in the main memory to enable the function of the data cache corresponding to the main memory by executing the boot loader in the internal memory, and then other simulation verification operations after code relocation are realized based on the data cache.

[0009] Preferably, enabling the function of the main memory corresponding to the data cache includes:

[0010] Initialize the data cache and pre-set page table corresponding to the main memory, complete the corresponding page configuration for the main memory and the data cache, open the data cache to realize the use of the data cache, and open the refresh function of the data cache to refresh the data in the data cache to the main memory when needed.

[0011] Preferably, after initializing the data cache corresponding to the main memory, the method further includes:

[0012] Clear the data in the data cache.

[0013] Preferably, opening the data cache includes:

[0014] The ARM CP15 register is operated to enable the data cache function.

[0015] Preferably, executing a boot loader in the flash memory medium of the SoC chip to implement simulation verification operations before code relocation includes:

[0016] Configure the processor of the SoC chip, close the data cache and MMU of the SoC chip, initialize and configure the program running stack of the SoC chip, and initialize and configure the front-end hardware devices including the main memory in the SoC chip.

[0017] Preferably, the boot loader is executed in the main memory to implement other simulation verification operations after code relocation based on the data cache after enabling the function of the data cache, including:

[0018] Initialization configuration of back-end hardware devices in the Soc chip is performed based on the data Cache, and shell operation is entered after the execution of the boot loader is completed.

[0019] Preferably, after the simulation verification operations before and after the code relocation are implemented, the method further includes:

[0020] The information of the simulation verification operation is recorded in the simulation verification log for query use.

[0021] A SoC chip simulation and verification device, comprising:

[0022] A first simulation verification module is configured to: execute a boot loader in a flash memory medium of the SoC chip during a simulation verification process of the SoC chip, so as to implement a simulation verification operation before code relocation;

[0023] The second simulation verification module is used to: after the simulation verification operation before code relocation is completed, determine that the main memory of the SoC chip has been initialized during the simulation verification operation before code relocation, migrate the boot loader to the main memory to realize code relocation, execute the boot loader in the main memory, and after enabling the function of the data cache corresponding to the main memory by executing the boot loader in the internal memory, realize other simulation verification operations after code relocation based on the data cache.

[0024] A SoC chip simulation and verification device, comprising:

[0025] Memory for storing computer programs;

[0026] A processor is used to implement the steps of the SoC chip simulation verification method as described in any one of the above items when executing the computer program.

[0027] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the SoC chip simulation verification method as described in any one of the above items.

[0028] The present invention provides a SoC chip simulation verification method, device, equipment and storage medium, the method comprising: in the simulation verification process of the SoC chip, executing a boot loader in the flash memory medium of the SoC chip to implement the simulation verification operation before code relocation; after the simulation verification operation before code relocation is completed, determining that the main memory of the SoC chip has completed initialization during the simulation verification operation before code relocation, migrating the boot loader to the main memory to implement code relocation, executing the boot loader in the main memory, and enabling the function of the main memory corresponding to the data Cache by executing the boot loader in the memory, and then implementing other simulation verification operations after code relocation based on the data Cache. In the simulation verification process of the SoC chip, the present application first executes the boot loader in the flash memory medium to implement the simulation verification operation before code relocation, then migrates the boot loader to the main memory for execution to implement the simulation verification operation after code relocation, and completes the initialization of the main memory when implementing the simulation verification operation before code relocation for code relocation based on the memory, and first enables the data Cache in the simulation verification operation after code relocation, so as to implement other simulation verification operations based on the data Cache in the subsequent implementation. It can be seen that this application enables data cache after the boot loader is relocated, so that subsequent simulation verification operations can be implemented based on data cache, which can effectively reduce the number of times the main memory is accessed and the time for simulating the boot loader, thereby improving the simulation verification speed of the SoC chip and improving the chip development efficiency of the SoC chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0030] Figure 1 A flowchart of a SoC chip simulation verification method provided by an embodiment of the present invention;

[0031] Figure 2 A flowchart of a process for enabling data caching in a SoC chip simulation verification method provided by an embodiment of the present invention;

[0032] Figure 3 A flowchart of optimizing the bootloader program execution in a SoC chip simulation verification method provided by an embodiment of the present invention;

[0033] Figure 4 A schematic structural diagram of a SoC chip simulation and verification device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] See also Figure 1 , which shows a flow chart of a SoC chip simulation verification method provided by an embodiment of the present invention, which may include:

[0036] S11: During the simulation verification process of the SoC chip, a boot loader is executed in the flash memory medium of the SoC chip to implement simulation verification operations before code relocation.

[0037] The embodiment of the present application is for the system-level simulation verification of SoC (System on Chip, system-level chip), and the bootloader program (boot loader, the first code executed by the embedded system after power-on) is placed in the simulation verification environment as a simulation stimulus for verification. The embodiment of the present application is to specifically explain the part of the SoC chip simulation verification in which the bootloader program is placed in the simulation verification environment as a simulation stimulus for verification. It should be noted that the execution of the bootloader program is mainly divided into two stages, namely before code relocation and after code relocation; before code relocation, the bootloader program is executed by fetching instructions from the flash memory medium (flash), and after code relocation, the main memory (DDR) has been initialized and the bootloader program has been migrated to the main memory for execution. Therefore, the embodiment of the present application first executes the bootloader program in the flash memory medium of the SoC chip to realize the simulation verification operation before code relocation, including initializing the main memory of the SoC chip, etc.; then the bootloader program is migrated to the main memory to realize code relocation, and the bootloader program is executed in the main memory to realize the simulation verification operation after code relocation.

[0038] S12: After the simulation verification operation before code relocation is completed, it is determined that the main memory of the SoC chip has been initialized during the simulation verification operation before code relocation, the boot loader is migrated to the main memory to realize code relocation, and the boot loader is executed in the main memory to enable the function of the main memory corresponding data cache by executing the boot loader in the memory, and then other simulation verification operations after code relocation are realized based on the data cache.

[0039] During the execution of the bootloader program in the main memory, the data cache corresponding to the main memory (the high-speed cache memory between the processor and the main memory) will be enabled first, so that the data cache can provide the corresponding cache function, and then other subsequent simulation verification operations will be implemented based on the data cache; specifically, when the bootloader program implements other subsequent simulation verification operations based on the data cache, if it needs to access the main memory, it will first access the data cache. When the data cache contains the data that needs to be accessed, the corresponding access operation will be implemented based on the data cache without accessing the main memory again. When the data cache does not contain the data that needs to be accessed, the main memory will be accessed to implement the corresponding access operation, and the data in the accessed main memory will be stored in the data cache for subsequent access. Compared with frequent access to the main memory, the method of prioritizing access to the data cache can effectively improve the data reading and writing speed, improve the execution speed of the bootloader program, and thus improve the simulation verification speed of the SoC chip.

[0040] During the simulation verification process of the SoC chip, the present application first executes the boot loader in the flash memory to implement the simulation verification operation before the code is relocated, and then migrates the boot loader to the main memory for execution to implement the simulation verification operation after the code is relocated. When implementing the simulation verification operation before the code is relocated, the main memory is initialized for implementing the code relocation based on the memory, and the simulation verification operation after the code is relocated is first enabled for the data cache to subsequently implement other simulation verification operations based on the data cache. It can be seen that the present application enables the data cache after the boot loader is relocated, so that the subsequent simulation verification operations can be implemented based on the data cache, which can effectively reduce the number of main memory accesses and the time for simulating the boot loader, thereby improving the simulation verification speed of the SoC chip and improving the chip development efficiency of the SoC chip.

[0041] An embodiment of the present invention provides a SoC chip simulation verification method that enables the function of a data cache corresponding to a main memory, and may include:

[0042] Initialize the data cache corresponding to the main memory and the pre-set page table, complete the corresponding page configuration for the main memory and data cache, turn on the data cache to use it, and turn on the refresh function of the data cache to refresh the data in the data cache to the main memory when needed.

[0043] After initializing the data cache corresponding to the main memory, it can also include:

[0044] Clear the data in the data cache.

[0045] Enable data cache, which can include:

[0046] Operate the ARM CP15 register to enable the data cache function.

[0047] refer to Figure 2The workflow for enabling data cache can be divided into five stages: (1) Data cache initialization: including completing data cache initialization operations, clearing data cache and TLB (Translation LookasideBuffer, translation backup buffer) to avoid invalid data in the data cache affecting the function; (2) Page table initialization: The page table is a special data structure that implements the conversion between logical addresses and physical addresses. In a computer system with a 32-bit address space, there is a total of 4GB of space. A page table entry is 4Byte, representing 1MB of address space. Therefore, 4GB of space requires 4096 page table entries, and 16KB of space needs to be reserved in the main memory as a page table. The function of page table initialization is to configure the initial value of this 16KB of memory space; (3) Main memory page table configuration: When the page table is initialized, all spaces are configured with initial values. For the main memory, the page table block of the main memory part needs to be configured according to the actual main memory hardware information, and the main memory space size is mapped to the page table. This part requires the configuration of the data cache allocation strategy, which can be configured as write-back or write-through to enable operations such as data cache access; (4) Data cache enablement: After the page table initialization and main memory page table configuration are completed, the data cache can be opened through commands. Taking the ARM processor as an example, by operating the ARM The CP15 register enables the data cache function; (5) Data cache refresh: At this point, the data cache is enabled. Subsequent read and write operations to the main memory will first be performed in the data cache. Therefore, a data cache refresh function is required to refresh the data in the data cache to the main memory so that the data in the cache and main memory are consistent. Thus, the above steps can effectively and conveniently enable the data cache, so that subsequent simulation verification operations can be performed based on the data cache.

[0048] An embodiment of the present invention provides a SoC chip simulation verification method, which executes a boot loader in a flash memory medium of the SoC chip to implement simulation verification operations before code relocation, and may include:

[0049] Configure the processor of the SoC chip, close the data cache and MMU of the SoC chip, initialize and configure the program running stack of the SoC chip, and initialize and configure the front-end hardware devices including main memory in the SoC chip.

[0050] Executing the boot loader in the main memory to implement other simulation verification operations after code relocation based on the data cache after enabling the data cache function may include:

[0051] Initialize and configure the back-end hardware devices in the Soc chip based on the data cache, and enter the shell operation after the boot loader is executed.

[0052] refer to Figure 3 , which is the optimized bootloader program execution process. The execution of the bootloader program is mainly divided into two stages, namely before code relocation and after code relocation; before code relocation, the bootloader program adopts a standard process, which is mainly divided into four stages: (1) Enable the processor SVC32 mode, configure the processor to privileged mode, and perform several processor configurations; (2) Close the data cache and MMU (Memory Management Unit). In the initial operation stage of the program, since the main memory has not been configured, the data cache and MMU must be closed to avoid data prefetching exceptions; (3) Stack initialization, perform initialization configuration of the program running stack; (4) Front-end initialization, perform initialization configuration of several hardware devices, including the initialization of the main memory (DDR). Code relocation is the process of migrating the bootloader code program from the flash medium (flash) to the main memory (DDR) for execution after the main memory (DDR) initialization is completed.

[0053] After code relocation, the data cache enablement function is added. This is mainly divided into three stages: (1) Data Cache Enablement: Data Cache initialization, MMU configuration, page table configuration, main memory page table configuration, cache refresh, etc.; (2) Backend Initialization: Initialization and configuration of several hardware devices; (3) Main Loop: Bootloader operation ends and enters shell operation. The bootloader process after code relocation occupies most of the running time. Therefore, after enabling data cache, the running of this part of the program can be significantly slowed down. SoC chip accelerated simulation verification also plays a role in this part.

[0054] In addition, after the simulation verification operations before and after code relocation are performed, the process may further include recording information about the simulation verification operations in a simulation verification log for querying. Specifically, the simulation verification operation information is recorded in a pre-set simulation verification log, so that the simulation verification operation status can be queried when needed later, facilitating operations such as information analysis.

[0055] Since most of the bootloader program is executed in the main memory, involving frequent reading and writing of the main memory, the bus interface between the processor and the main memory is the main performance bottleneck and the main reason for the long simulation time of the bootloader program. Based on this, the present application enables data cache in the bootloader program. When the main memory is needed for program execution, the data cache can reduce the number of times the processor accesses the main memory. The instructions and data and other information accessed by the processor may be accessed multiple times in the future. Therefore, when any information is accessed for the first time, it is copied to the data cache. When the arbitrary information is accessed in the future, it does not need to be retrieved from the main memory, but from the data cache, thereby accelerating the process. Therefore, the present application can utilize the cache function to accelerate, thereby avoiding frequent reading and writing of the main memory, further accelerating the execution of the program, and significantly shortening the time required for simulation verification; that is, the SoC chip simulation verification method provided by the present application utilizes the locality principle of the cache memory and accelerates the simulation verification of the SoC chip through optimized bootloader program design; experimental testing shows that in a 30 million gate SoC chip, the simulation verification time using this method is less than 44 hours, which is 51% shorter than the original time, with a significant acceleration effect. Furthermore, this application adds a data cache enabling function within the existing bootloader program framework, effectively accelerating the operation of the bootloader program while also being compatible with the existing bootloader environment, enabling seamless porting. Furthermore, this application is not limited to bootloader programs or ARM processor architectures but can also be extended to similar bare-metal program emulation, kernel program emulation, and so on, all within the scope of protection of the present invention.

[0056] The embodiment of the present invention also provides a SoC chip simulation verification device, such as Figure 4 Specifically, it may include:

[0057] The first simulation verification module 11 is used to: execute a boot loader in the flash memory medium of the SoC chip during the simulation verification process of the SoC chip to implement simulation verification operations before code relocation;

[0058] The second simulation verification module 12 is used to: after the simulation verification operation before code relocation is completed, determine that the main memory of the SoC chip has been initialized during the simulation verification operation before code relocation, migrate the boot loader to the main memory to realize code relocation, execute the boot loader in the main memory, and enable the function of the main memory corresponding data cache by executing the boot loader in the internal memory, and then realize other simulation verification operations after code relocation based on the data cache.

[0059] In an embodiment of the present invention, a SoC chip simulation and verification device is provided, wherein the second simulation and verification module may include:

[0060] The enabling unit is used to: initialize the data cache corresponding to the main memory and the pre-set page table, complete the corresponding page configuration for the main memory and the data cache, turn on the data cache to realize the use of the data cache, and turn on the refresh function of the data cache to refresh the data in the data cache to the main memory when needed.

[0061] In an SoC chip simulation verification device provided by an embodiment of the present invention, the enabling unit can also be used to: clear data in the data cache after initializing the data cache corresponding to the main memory.

[0062] An embodiment of the present invention provides a SoC chip simulation and verification device, wherein the enabling unit may include:

[0063] Open the unit to operate the ARM CP15 register to enable the data cache function.

[0064] An embodiment of the present invention provides a SoC chip simulation and verification device, wherein the first simulation and verification module may include:

[0065] The first simulation verification unit is used to: configure the processor of the SoC chip, close the data cache and MMU of the SoC chip, initialize and configure the program running stack of the SoC chip, and initialize and configure the front-end hardware devices including the main memory in the SoC chip.

[0066] In an embodiment of the present invention, a SoC chip simulation and verification device is provided, wherein the second simulation and verification module may include:

[0067] The second simulation verification unit can be used to: perform initialization configuration of the back-end hardware device in the Soc chip based on the data Cache, and enter the shell operation after the boot loader is executed.

[0068] An embodiment of the present invention provides a SoC chip simulation and verification device, which may further include:

[0069] The recording module is used to: after the simulation verification operation before and after the code relocation is implemented, record the information of the simulation verification operation into the simulation verification log for query use.

[0070] An embodiment of the present invention further provides a SoC chip simulation and verification device, which may include:

[0071] Memory for storing computer programs;

[0072] A processor is used to implement the steps of any of the above SoC chip simulation verification methods when executing a computer program.

[0073] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of any of the above SoC chip simulation verification methods can be implemented.

[0074] It should be noted that for the description of the relevant parts of the SoC chip simulation verification device, equipment, and storage medium provided in the embodiment of the present invention, please refer to the detailed description of the corresponding parts in the SoC chip simulation verification method provided in the embodiment of the present invention, and no further details will be given here. In addition, the parts of the above-mentioned technical solutions provided in the embodiment of the present invention that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail to avoid excessive elaboration.

[0075] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be construed in the widest manner consistent with the principles and novel features disclosed herein.

Claims

1. A SoC chip simulation verification method, characterized in that: include: During the simulation verification process of the SoC chip, a boot loader is executed in the flash memory medium of the SoC chip to implement simulation verification operations before code relocation; After the simulation verification operation before code relocation is completed, determining that the main memory of the SoC chip has been initialized during the simulation verification operation before code relocation, migrating the boot loader to the main memory to implement code relocation, executing the boot loader in the main memory, enabling a function of a data cache corresponding to the main memory by executing the boot loader in the main memory, and then implementing other simulation verification operations after code relocation based on the data cache; The boot loader is executed in the flash memory medium of the SoC chip to implement simulation verification operations before code relocation, including: Configure the processor of the SoC chip, disable the data cache and MMU of the SoC chip, initialize and configure the program execution stack of the SoC chip, and initialize and configure the front-end hardware devices including main memory in the SoC chip; Executing the boot loader in the main memory to implement other simulation verification operations after code relocation based on the data cache after enabling the function of the data cache, including: Initialization configuration of back-end hardware devices in the Soc chip is performed based on the data Cache, and shell operation is entered after the execution of the boot loader is completed.

2. The method according to claim 1, characterized in that Enabling the main memory corresponding data cache function includes: Initialize the data cache and pre-set page table corresponding to the main memory, complete the corresponding page configuration for the main memory and the data cache, open the data cache to realize the use of the data cache, and open the refresh function of the data cache to refresh the data in the data cache to the main memory when needed.

3. The method according to claim 2, characterized in that After initializing the data cache corresponding to the main memory, the process further includes: Clear the data in the data cache.

4. The method according to claim 3, characterized in that Opening the data cache includes: The ARM CP15 register is operated to enable the data cache function.

5. The method according to claim 4, characterized in that After the simulation verification operations before and after code relocation are implemented, the following steps are also included: The information of the simulation verification operation is recorded in the simulation verification log for query use.

6. A SoC chip simulation verification device, characterized in that: include: A first simulation verification module is configured to: execute a boot loader in a flash memory medium of the SoC chip during a simulation verification process of the SoC chip, so as to implement a simulation verification operation before code relocation; A second simulation verification module is configured to: after the simulation verification operation before code relocation is completed, determine that the main memory of the SoC chip has been initialized during the simulation verification operation before code relocation, migrate the boot loader to the main memory to implement code relocation, execute the boot loader in the main memory, enable the function of the data cache corresponding to the main memory by executing the boot loader in the main memory, and then implement other simulation verification operations after code relocation based on the data cache; Wherein, the first simulation verification module includes: The first simulation verification unit is used to: configure the processor of the SoC chip, disable the data cache and MMU of the SoC chip, initialize and configure the program execution stack of the SoC chip, and initialize and configure the front-end hardware devices including the main memory in the SoC chip; The second simulation verification module includes: The second simulation verification unit can be used to: perform initialization configuration of the back-end hardware device in the Soc chip based on the data Cache, and enter the shell operation after the execution of the boot loader is completed.

7. A SoC chip simulation verification device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the SoC chip simulation verification method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the SoC chip simulation verification method according to any one of claims 1 to 5.

Images