A dynamic time series analysis method for aging and fluctuation perception

Abstract

The present invention discloses an aging and fluctuation-aware dynamic timing analysis method, which belongs to the field of integrated circuit design automation. This method is based on event-propagation dynamic timing analysis, and uses an event propagation algorithm to calculate the delay of a circuit per cycle under a specified input. The present invention modifies the traditional event propagation algorithm to support gate-level aging models and gate-level fluctuation models, so that the final dynamic delay is the delay distribution after aging rather than a deterministic value. The present invention can analyze the dynamic delay of a digital circuit after actual load degradation and the fluctuation of the dynamic delay, and thus can calculate the probability of circuit timing errors after aging, which can help designers accurately estimate the impact of aging and random process fluctuations on timing information and avoid performance loss due to over-design.

Description

Technical Field

[0001] The present invention relates to an aging- and variation-aware dynamic timing analysis method, and belongs to the field of integrated circuit design automation. Background Art

[0002] As microelectronics processes continue to scale down, non-ideal effects such as random process variation and transistor aging become increasingly severe, leading to increasing fluctuations in circuit performance. To ensure the lifespan of circuits, designers generally use static timing analysis to estimate the circuit's worst-case corner delay (i.e., all transistors are at the worst-case corner and experience the greatest degradation). This is then used as a constraint to design the circuit's operating voltage and frequency, leading to circuit over-design. This over-design increases as the process scales down, resulting in significant device performance improvements between each process generation, but ultimately, circuit performance does not improve proportionally.

[0003] To improve circuit performance at advanced nodes, new design methods have been proposed in recent years, such as dynamic frequency / voltage scaling and approximate computing. Dynamic frequency / voltage scaling dynamically adjusts the operating frequency or voltage based on the real-time operating scenario, rather than using fixed operating frequencies and voltages. This can achieve better performance or higher energy efficiency. Approximate computing allows circuit errors and leverages the inherent fault tolerance of programs or algorithms to tolerate these hardware errors, thereby trading computational accuracy for performance or energy efficiency. These new design methods can break free from the pessimistic limitations of static analysis, but require dynamic information, such as dynamic delay per cycle, to guide these optimization strategies.

[0004] Traditional dynamic timing analysis methods utilize gate-level simulation with delay back-annotation. The delay back-annotation file contains the per-cell delays derived from graph-based static timing analysis. This approach has two major drawbacks: inaccurate delay calculations and the neglect of the effects of aging and fluctuations on delay information.

[0005] The first flaw can be addressed by event-based dynamic analysis. However, since they ignore the effects of aging and fluctuations, they must add a guardband to the final calculation results to prevent circuit failure. However, this guardband is calculated based on the worst-case scenario, resulting in an overestimation of delay. This overestimation in dynamic timing analysis prevents these new dynamic optimization strategies from fully realizing their effectiveness.

[0006] Therefore, an aging- and fluctuation-aware dynamic timing analysis method is very important for circuit optimization strategies at advanced nodes. Summary of the Invention

[0007] The present invention aims to propose an aging- and fluctuation-aware dynamic timing analysis method. This method analyzes the dynamic delay and dynamic delay fluctuations of digital circuits after actual load degradation, and thus calculates the probability of circuit timing errors after aging. This method can help designers accurately estimate the impact of aging and random process fluctuations on timing information, avoiding performance losses caused by over-design.

[0008] The technical solutions provided by the present invention are as follows:

[0009] An aging and fluctuation-aware dynamic timing analysis method is characterized by being divided into two parts: the first part is gate-level aging and fluctuation analysis, and the second part is dynamic timing analysis based on event propagation, wherein:

[0010] Gate-level aging and fluctuation analysis: Gate-level aging analysis calculates the delay of each gate-level unit after actual aging, expressed as an increase in delay. Gate-level fluctuation analysis calculates the delay fluctuation of each gate-level unit due to random process fluctuations, expressed as the standard deviation of the delay.

[0011] Dynamic timing analysis based on event propagation: A signal flip on a circuit node is defined as an event. After the timing diagram is established, the timing analysis of each cycle begins. The timing analysis of each cycle includes: generating input events, propagating input events to the timing endpoint, and reporting the dynamic delay and triggering path of this cycle.

[0012] Furthermore, the gate-level fluctuation analysis adopts an industry-standard fluctuation cell library model, which stores the delay mean and standard deviation of each standard cell under different input slope and output load combinations.

[0013] Furthermore, the gate-level aging analysis is divided into two parts: the first part is workload analysis, which is used to calculate the degradation value of each transistor; the second part is gate-level aging model, which is used to calculate the delay of each gate-level unit after degradation.

[0014] Furthermore, the workload analysis is specifically as follows: first, the duty cycle and flip rate of each node inside the circuit are obtained through zero-delay gate-level circuit simulation; then, based on the internal connection topology of the corresponding gate-level unit, the duty cycle of each transistor is analytically calculated; finally, the degradation value of this transistor is calculated based on the device aging model of the corresponding process node.

[0015] Furthermore, the generating of input events is specifically as follows: first, the input event on the input node is determined according to the input vector, and the input vector of the current cycle is compared with the input vector of the previous cycle. If there is a difference in one bit, it means that an input event will occur on the corresponding input node.

[0016] Furthermore, the gate-level aging model is as follows:

[0017] delay aged =delay fresh +∑a i ×ΔV thi

[0018] tr aged =tr fresh +∑b i ×ΔV thi

[0019] where a i ,b i is the sensitivity coefficient, which is related to the input slope and output load, ΔV thi It is the threshold voltage drift of each transistor due to degradation.

[0020] Furthermore, the propagation of input events to the timing end point is specifically as follows: after all input events are generated, the events will be propagated on the lines and gate-level units in sequence, and the gate-level units will generate output events according to all input events until the timing end point.

[0021] Furthermore, the newly generated event arrival time mean is equal to the arrival time of the input event plus the mean of the gate-level unit delay and the delay increase caused by aging, and the standard deviation of the output event arrival time is equal to the square root of the sum of the squares of the standard deviation of the input event arrival time and the standard deviation of the gate-level unit delay.

[0022] Furthermore, the specific reporting delay and triggering path is as follows: after the event propagation of each level is completed, all timing endpoints are traversed to find the maximum arrival time, which is the delay of this cycle. Based on this event, reverse search for the event that triggered it, and the path triggered by this cycle can be found.

[0023] This invention uses an event propagation-based dynamic timing analysis to calculate the per-cycle delay of a circuit under specified input conditions. This invention modifies the traditional event propagation algorithm to support gate-level aging and fluctuation models, ensuring that the final dynamic delay is a distribution of the delay after aging rather than a deterministic value. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0025] The present invention proposes a dynamic time series analysis method for aging and fluctuation perception. Figure 1 As shown below, we will combine Figure 1 Provide a detailed and clear description of each part of the process. The process of aging- and fluctuation-aware dynamic timing analysis is mainly divided into two parts: the first part is gate-level aging and fluctuation analysis, and the second part is event propagation-based dynamic timing analysis.

[0026] Gate-level aging and fluctuation analysis: The purpose of gate-level aging analysis is to calculate the delay of each gate-level unit after actual aging, which is expressed as the increase in delay (Δdelay). Gate-level fluctuation analysis is to calculate the delay fluctuation of each gate-level unit due to random process fluctuations, which is expressed as the standard deviation of delay (σ delay ).

[0027] Gate-level fluctuation analysis utilizes an industry-standard fluctuation cell library model (LVF cell library), which stores the mean and standard deviation of delay for each standard cell under different combinations of input slew and output load. These values must be calculated in advance using SPICE-level simulation.

[0028] Gate-level aging analysis is divided into two parts: the first part is workload analysis, which aims to calculate the degradation value (ΔV th ); The second part is the gate-level aging model, which aims to calculate the delay and output conversion time of each gate-level unit after degradation.

[0029] The first part of the workload analysis first obtains the duty cycle and flip rate of each node in the circuit through zero-delay gate-level circuit simulation. Then, based on the internal connection topology of the corresponding gate-level unit, the duty cycle of each transistor is analytically calculated. Finally, the degradation value of this transistor is calculated based on the device aging model of the corresponding process node.

[0030] The second part is the gate-level aging model, which calculates the delay and output transition time (tr) of each gate-level unit after degradation. The model is as follows:

[0031] delay aged =delay fresh +∑a i ×ΔV thi

[0032] tr aged =tr fresh +∑b i ×ΔV thi

[0033] where a i ,b i is the sensitivity coefficient, which is also related to the input slew and output load, and is calculated using the following formula:

[0034] a i =a i0 +α ai ×slew+β ai ×load

[0035] b i =b i0 +α bi ×slew+β bi ×load

[0036] where a i0 ,α ai ,β ai ,b i0 ,α bi ,β bi , is the fitting parameter, ΔV thi It is the threshold voltage drift of each transistor due to degradation.

[0037] This model also requires SPICE simulation to calculate parameters in advance at each process node.

[0038] Dynamic timing analysis based on event propagation: The purpose of dynamic timing analysis is to calculate the dynamic delay of the circuit in each cycle. The present invention uses a method based on event propagation rather than a method based on timing diagrams. A signal flip on a circuit node is defined as an event. An event has at least three properties: transition time, mean (μ) and standard deviation (σ) of arrival time. The maximum dynamic delay of a circuit in a certain cycle is determined by the event with the largest arrival time at all timing endpoints in this cycle. The main advantage of the event propagation-based method is that the delay calculation of event propagation on each gate-level unit is based on the switching time of the input event, so the delay calculation of the gate-level unit is accurate and there is no pessimistic estimate.

[0039] After establishing the timing diagram, dynamic timing analysis based on event propagation begins analyzing cycle-by-cycle latency. This analysis consists of three steps: generating input events, propagating the input events to the timing endpoints, and reporting the dynamic latency and triggering paths for the cycle.

[0040] (1) Generating Input Events: The first step is to determine the input events on the input nodes based on the input vector. The program compares the input vector of the current cycle with the input vector of the previous cycle. If there is a difference in one bit, it means that an input event will occur on the corresponding input node. The arrival time and switching time of the input event are defined by the user.

[0041] (2) Event Propagation: After all input events are generated, the program begins to propagate the input events on these input nodes step by step until the timing ends. Events will be propagated on the lines and gate-level units in sequence. Propagation on the lines only increases the arrival time. At the gate-level unit, the gate-level unit will generate output events based on all input events.

[0042] The present invention modifies the event propagation algorithm for gate-level units. While the gate-level unit's output event generation remains unchanged, the method for calculating gate-level unit delay changes. Gate-level unit delay is calculated using the aforementioned gate-level aging model and gate-level fluctuation model, forming a distribution. Therefore, the mean arrival time of a newly generated event is equal to the arrival time of the input event plus the mean gate-level unit delay and the delay increase due to aging. The standard deviation of the output event arrival time is equal to the square root of the sum of the standard deviation of the input event arrival time and the standard deviation of the gate-level unit delay.

[0043] (3) Reporting delays and triggered paths: After each level of event propagation is complete, traverse all timing endpoints and find the maximum arrival time, which is the delay for this cycle. Based on this event, reversely search for the event that triggered it to find the path that triggered this cycle.

[0044] The embodiments described above are not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A dynamic time series analysis method for aging and fluctuation perception, characterized in that: It is divided into two parts. The first part is gate-level aging and fluctuation analysis, and the second part is dynamic timing analysis based on event propagation, where: Gate-level aging and fluctuation analysis: Gate-level aging analysis calculates the delay of each gate-level unit after actual aging, expressed as an increase in delay. Gate-level fluctuation analysis calculates the delay fluctuation of each gate-level unit due to random process fluctuations, expressed as the standard deviation of the delay. Dynamic timing analysis based on event propagation: A signal flip at a circuit node is defined as an event. After the timing diagram is established, the delay of each cycle is analyzed one by one. The timing analysis of each cycle includes generating input events, propagating the input events to the timing endpoint, and reporting the dynamic delay and triggered path of this cycle. The propagation of input events to the timing endpoint is specifically as follows: after all input events are generated, the events will be propagated in sequence on the lines and gate-level units, and the gate-level units will generate output events based on all input events until the timing endpoint; the mean arrival time of the newly generated events is equal to the arrival time of the input events plus the mean gate-level unit delay and the delay increase caused by aging, and the standard deviation of the output event arrival time is equal to the square root of the sum of the standard deviation of the input event arrival time and the standard deviation of the gate-level unit delay; The specific reporting delay and triggering path is as follows: after each level of event propagation is completed, all timing endpoints are traversed to find the maximum arrival time, which is the delay of this cycle. Based on this event, reverse search for the event that triggered it to find the path triggered by this cycle.

2. The dynamic time series analysis method for aging and fluctuation perception according to claim 1, characterized in that: The gate-level fluctuation analysis adopts an industry-standard fluctuation cell library model, in which the delay mean and standard deviation of each standard cell under different input slope and output load combinations are stored.

3. The dynamic time series analysis method for aging and fluctuation perception according to claim 1, characterized in that: The gate-level aging analysis is divided into two parts: the first part is workload analysis, which is used to calculate the degradation value of each transistor; the second part is gate-level aging model, which is used to calculate the delay of each gate-level unit after degradation.

4. The dynamic time series analysis method for aging and fluctuation perception according to claim 3, characterized in that: Specifically, the workload analysis involves first obtaining the duty cycle and flip rate of each node within the circuit through zero-delay gate-level circuit simulation, then analytically calculating the duty cycle of each transistor based on the internal connection topology of the corresponding gate-level unit, and finally calculating the degradation value of this transistor based on the device aging model of the corresponding process node.

5. The dynamic time series analysis method for aging and fluctuation perception according to claim 3, characterized in that: The gate-level aging model is as follows: delay aged =delay fresh +∑a i ×ΔV thi tr aged =tr fresh +∑b i ×ΔV thi where a i ,b i is the sensitivity coefficient, which is related to the input slope and output load, ΔV thi It is the threshold voltage drift of each transistor due to degradation.

6. The dynamic time series analysis method for aging and fluctuation perception according to claim 1, wherein: The generating of input events is specifically as follows: firstly, the input event on the input node is determined according to the input vector, and the input vector of the current cycle is compared with the input vector of the previous cycle. If there is a difference in one bit, it means that an input event will occur on the corresponding input node.

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