A source code segmentation method and system for FPGA
Through the FPGA source code segmentation method based on Module instance, the consumption of RTL level instantiation tree and computing resource is analyzed, and the problem of poor FPGA source code segmentation performance and effect in the prior art is solved, and more efficient segmentation and improved timing performance are achieved.
Patent Information
- Application Number
- CN202210001037.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-01-04
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2042-01-04
AI Technical Summary
The existing FPGA source code segmentation method has poor performance and effect, especially in complex SoC designs, and it is difficult to ensure that the design logic functions after segmentation are correct and performance meet the standards.
The FPGA source code segmentation method based on Module instance is used to analyze the RTL hierarchical instantiation tree, and the resource consumption and input and output delay of each Module instance are calculated, and clustering and iterative optimization are performed to ensure that the segmentation results meet the FPGA resource constraints.
It realizes more efficient FPGA source code segmentation, reduces segmentation IO, reduces line delay, and improves the timing performance of logic design.
Smart Images
Figure CN114282472B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of FPGAs, and particularly to a source code segmentation method and system for an FPGA. Background Art
[0002] With the increasing complexity of modern SoC designs and the growing scale of transistors, it has also become difficult to verify the designs. Currently, using Emulation for simulation verification acceleration has become the mainstream direction for large and extra-large integrated circuit designs. This design uses multiple FPGAs interconnected and cascaded to accelerate the verification of user logic designs. Users need to find a way to divide a large design into several small designs, configure them into multiple FPGAs, and at the same time ensure that the logical functions of the entire design are correct and the performance meets the standards during operation. The existing method for dividing the logic of the user logic DUT is to use traditional algorithms for relatively simple and crude segmentation, and even manual segmentation of the logic design is required. And most of the segmentation is based on the gate-level netlist for segmentation, with poor performance and effects. Summary of the Invention
[0003] The object of the present invention is to provide a source code segmentation method and system for an FPGA based on Module instance to address the deficiencies of poor performance and effects in the existing source code segmentation method for FPGAs.
[0004] In an embodiment of the present invention, a source code segmentation method for an FPGA is proposed, which includes:
[0005] Analyze the entire RTL logic project to obtain an RTL hierarchical instantiation tree;
[0006] Calculate the resource consumption of each Module instance in the RTL hierarchical instantiation tree;
[0007] Analyze the input and output delays of each Module instance and sort them in descending order;
[0008] According to the FPGA resource constraint conditions, use multiple Module instances with relatively high input and output delay rankings as initial seeds, and cluster them with their interconnected Module instances respectively to obtain multiple clusters;
[0009] Move the Module instance with the smallest input and output delay in each cluster to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraint conditions. Repeat this iterative process to find the cluster combination with the least IO between clusters, and use the cluster combination at this time as the segmentation result.
[0010] In the embodiments of the present invention, the resource consumption of each Module instance includes LUT, FF, RAM, and IO quantity resources.
[0011] In the embodiments of the present invention, the input-output delay of a Module instance is the sum of the input delay and the output delay of the Module instance. The input delay of the Module instance is the delay from the input of the Module instance to the first register, and the delay from the last register to the output of the Module instance.
[0012] In the embodiments of the present invention, moving the Module instance with the minimum input-output delay in each cluster to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraint conditions includes:
[0013] Moving the Module instance with the minimum input-output delay in a certain cluster to other clusters interconnected with it, and then calculating the quantity of IO between clusters. If the quantity of IO between clusters increases, return to the state before the movement, and then move the Module instance with the minimum input-output delay in the next cluster; if the quantity of IO between clusters decreases, use the cluster obtained at this time as a new cluster.
[0014] In the embodiments of the present invention, there is also provided a source code segmentation system for an FPGA, which includes:
[0015] An RTL analysis module for analyzing the entire RTL logic project to obtain an RTL hierarchical instantiation tree;
[0016] A resource calculation module for calculating the resource consumption of each Module instance in the RTL hierarchical instantiation tree;
[0017] A delay analysis module for analyzing the input-output delay of each Module instance and performing a descending order sorting;
[0018] A clustering module for clustering multiple Module instances with relatively high input-output delay sorting as initial seeds according to the FPGA resource constraint conditions, respectively with the Module instances interconnected with them to obtain multiple clusters;
[0019] A segmentation module for moving the Module instance with the minimum input-output delay in each cluster to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraint conditions, repeating this iterative process, finding the cluster combination with the least IO between clusters, and using the cluster combination at this time as the segmentation result.
[0020] In the embodiments of the present invention, the resource consumption of each Module instance includes LUT, FF, RAM, and IO quantity resources.
[0021] In the embodiments of the present invention, the input-output delay of a Module instance is the sum of the input delay and the output delay of the Module instance. The input delay of the Module instance is the delay from the input of the Module instance to the first internal register, and the output delay of the Module instance is the delay from the last internal register to the output of the Module instance.
[0022] In the embodiments of the present invention, moving the Module instance with the minimum input-output delay in each cluster to other clusters interconnected therewith to form multiple new clusters that meet the FPGA resource constraint conditions includes:
[0023] Moving the Module instance with the minimum input-output delay in a certain cluster to other clusters interconnected therewith, and then calculating the quantity of IO between clusters. If the quantity of IO between clusters increases, then revert to the state before the movement, and then move the Module instance with the minimum input-output delay in the next cluster; if the quantity of IO between clusters decreases, then use the cluster obtained at this time as a new cluster.
[0024] Compared with the prior art, in the technical solution of the present invention, logical segmentation is performed with the Module instance as the basic unit, simplifying the segmentation complexity; considering the delay between Module instances, and only analyzing the delay from the input of the instance to the register and the delay from the register to the output, driving the segmentation by timing. The final segmentation result is that the segmented IO is as small as possible, and at the same time, the wire delay of the segmentation is as low as possible, improving the timing performance of the logical design. Description of the Drawings
[0025] Figure 1 is a flowchart of the source code segmentation method for the FPGA in the embodiments of the present invention.
[0026] Figure 2 is a schematic diagram of the RTL-level instantiation tree in the embodiments of the present invention.
[0027] Figure 3 is a schematic diagram of the resource calculation in the embodiments of the present invention.
[0028] Figure 4 is a schematic diagram of the delay of the module instance in the embodiments of the present invention.
[0029] Figure 5 It is a schematic structural diagram of the source code segmentation system of the FPGA provided by the embodiment of the present invention. Specific embodiments
[0030] As Figure 1 shown, in the embodiment of the present invention, a source code segmentation method for FPGA is proposed, which includes steps S1-S5. The following will be described separately.
[0031] Step S1: Analyze the entire RTL logic project to obtain the RTL hierarchical instantiation tree.
[0032] As Figure 2 shown, the RTL hierarchical instantiation tree is composed of multiple tree-shaped distributed Module instance nodes. Each Module instance node is associated with at least one other Module instance node.
[0033] Step S2: Calculate the resource consumption of each Module instance in the RTL hierarchical instantiation tree.
[0034] The resource consumption of each Module instance includes the number of resources of LUT (look up table), FF (FlipFlop), RAM (random access memory), and IO (Input Output).
[0035] For example, Figure 3 the resources of the adder Module instance in
[0036] Look-up table LUT: 0
[0037] Full adder Adder: 7
[0038] Flip-flop FF: 7
[0039] RAM: 0
[0040] IO: 20.
[0041] Step S3: Analyze the input and output delays of each Module instance and sort them in descending order.
[0042] As Figure 4As shown in the figure, the input-output delay of a Module instance is the sum of the input delay and the output delay of the Module instance. The input delay of the Module instance is the delay from the input of the Module instance to the first internal register, and the output delay of the Module instance is the delay from the last internal register to the output of the Module instance. For a large number of connections between Instances, the specific calculation method is to calculate the average delay of all other input connections except the clock line as the input delay, and calculate the average delay of all other output connections as the output delay. During the partitioning process, the higher the delay of a path, the lower the partitioning probability.
[0043] Step S4: According to the FPGA resource constraint conditions, use multiple Module instances with relatively high input-output delay rankings as initial seeds, and cluster them with the interconnected Module instances respectively to obtain multiple clusters.
[0044] It should be noted that since during the partitioning process, the higher the delay of a path, the lower the partitioning probability, multiple Module instances with relatively high input-output delay rankings can be used as initial seeds to generate multiple clusters.
[0045] Step S5: Move the Module instance with the minimum input-output delay in each cluster to other clusters to form multiple new clusters that meet the FPGA resource constraint conditions. Repeat this process to find the situation with the least number of IOs between different clusters, and use the clusters at this time as the partitioning result.
[0046] It should be noted that the multiple clusters generated in Step S4 are not the optimal clusters, so fine-tuning is required. Move the Module instance with the minimum input-output delay in each cluster to other clusters to form multiple new clusters that meet the FPGA resource constraint conditions, specifically including:
[0047] Move the Module instance with the minimum input-output delay in a certain cluster to other clusters interconnected with it, and then calculate the number of IOs between the clusters. If the number of IOs between the clusters increases, return to the state before the move, and then move the Module instance with the minimum input-output delay in the next cluster; if the number of IOs between the clusters decreases, use the clusters obtained at this time as new clusters, repeat this iterative process until the situation with the least number of IOs between the clusters is found, use the clusters at this time as the partitioning result, and output multiple configurations to the HDL files in the FPGA according to the partitioning result.
[0048] Such asFigure 5 As shown in Figure 5 , corresponding to the source code segmentation method of the above FPGA, in an embodiment of the present invention, a source code segmentation system for an FPGA is further provided, which includes an RTL analysis module 1, a resource calculation module 2, a delay analysis module 3, a clustering module 4, and a segmentation module 5.
[0049] The RTL analysis module 1 is configured to analyze the entire RTL logic project to obtain an RTL hierarchical instantiation tree.
[0050] The resource calculation module 2 is configured to calculate the resource consumption of each Module instance in the RTL hierarchical instantiation tree.
[0051] The delay analysis module 3 is configured to analyze the input and output delays of each Module instance and perform a descending order sorting.
[0052] The clustering module 4 is configured to, according to the FPGA resource constraint conditions, use multiple Module instances with relatively high input and output delay sorting as initial seeds, and cluster them with their interconnected Module instances respectively to obtain multiple clusters.
[0053] The segmentation module 5 is configured to move the Module instance with the minimum input and output delay in each cluster to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraint conditions, find the cluster combination with the least number of IOs between clusters, and use the cluster combination at this time as the segmentation result.
[0054] In summary, in the technical solution of the present invention, logical segmentation is performed with the Module instance as the basic unit, simplifying the segmentation complexity; considering the delay between Module instances, and only analyzing the delay from the instance input to the register and the delay from the register to the output, and driving the segmentation by timing. The final segmentation result is that the segmentation IO is as small as possible, and at the same time the wire delay of the segmentation is as low as possible, improving the timing performance of the logical design.
[0055] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A source code segmentation method for FPGA, characterized in that, including: Analyze the entire RTL logic project to obtain the RTL-level instantiation tree; Calculate the resource consumption of each Module instance in the RTL-level instantiation tree; Analyze the input and output delays of each Module instance and sort them in descending order; According to the FPGA resource constraint conditions, use multiple Module instances with relatively high input and output delay sorting as initial seeds, and cluster them with their interconnected Module instances respectively to obtain multiple clusters; Move the Module instance with the minimum input and output delay in each cluster to other clusters interconnected with this Module instance to form multiple new clusters that meet the FPGA resource constraint conditions. Repeat this iterative process to find the cluster combination with the least number of inter-cluster IOs, and use the cluster combination at this time as the segmentation result.
2. The source code segmentation method for FPGA according to claim 1, characterized in that, The resource consumption of each Module instance includes LUT, FF, RAM, and IO quantity resources.
3. The source code segmentation method for FPGA according to claim 1, characterized in that, The input and output delay of a Module instance is the sum of the input delay and output delay of the Module instance. The input delay of a Module instance is the delay from the input of the Module instance to the first internal register, and the output delay of a Module instance is the delay from the last internal register to the output of the Module instance.
4. The source code segmentation method for FPGA according to claim 1, characterized in that, Move the Module instance with the minimum input and output delay in each cluster to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraint conditions, including: Move the Module instance with the minimum input and output delay in a certain cluster to other clusters interconnected with it, and then calculate the number of inter-cluster IOs. If the number of inter-cluster IOs increases, return to the state before the move, and then move the Module instance with the minimum input and output delay in the next cluster; if the number of inter-cluster IOs decreases, use the cluster obtained at this time as the new cluster.
5. A source code segmentation system for FPGA, characterized in that, including: An RTL analysis module for analyzing the entire RTL logic project to obtain the RTL-level instantiation tree; A resource calculation module for calculating the resource consumption of each Module instance in the RTL-level instantiation tree; A delay analysis module for analyzing the input and output delays of each Module instance and sorting them in descending order; A clustering module for clustering multiple Module instances with relatively high input and output delay sorting as initial seeds according to the FPGA resource constraint conditions and their interconnected Module instances respectively to obtain multiple clusters; The splitting module is used to move the Module instance with the minimum input-output delay in each cluster to other clusters interconnected with this Module instance, forming multiple new clusters that meet the FPGA resource constraint conditions. Repeat this iterative process to find the cluster combination with the minimum number of inter-cluster IOs, and use the cluster combination at this time as the splitting result.
6. The source code segmentation system for FPGA according to claim 5, characterized in that, The resource consumption of each Module instance includes LUT, FF, RAM, and IO quantity resources.
7. The source code segmentation system for FPGA according to claim 5, characterized in that, The input-output delay of a Module instance is the sum of the input delay and the output delay of the Module instance. The input delay of a Module instance is the delay from the input of the Module instance to the first internal register, and the output delay of a Module instance is the delay from the last internal register to the output of the Module instance.
8. The source code segmentation system for FPGA according to claim 5, characterized in that, Moving the Module instance with the minimum input-output delay in each cluster to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraint conditions includes: Moving the Module instance with the minimum input-output delay in a certain cluster to other clusters interconnected with it, and then calculating the number of inter-cluster IOs. If the number of inter-cluster IOs increases, return to the state before the move, and then move the Module instance with the minimum input-output delay in the next cluster; if the number of inter-cluster IOs decreases, use the cluster obtained at this time as the new cluster.
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