Chip, layout design system and layout design method

Abstract

The chip of the present invention includes a first circuit system and a second circuit system. The first circuit system includes a plurality of first circuits, wherein the first circuit has a first power consumption at a point in time. The second circuit system includes a plurality of second circuits, wherein the second circuit has a second power consumption at the point in time, and the first power consumption is higher than the second power consumption. At least one of the first circuits is interleaved with at least one of the second circuits to reduce the operating temperature of the first circuit at the point in time.

Description

Technical Field

[0001] The invention relates to a chip, in particular to a chip with a built-in radiator, a layout design system and a layout design method thereof. Background Art

[0002] In the layout of existing integrated circuits, multiple circuits with the same function are usually placed together. In practical applications, if multiple circuits with the same function operate at the same time, the temperature of the chip will be too high locally, which may cause damage to the chip. To avoid damage, an additional heat sink is required to reduce the chip temperature. This will result in additional cost expenditure. Summary of the invention

[0003] In some embodiments, the chip includes a first circuit system and a second circuit system. The first circuit system includes a plurality of first circuits, wherein the first circuit has a first power consumption at a point in time. The second circuit system includes a plurality of second circuits, wherein the second circuit has a second power consumption at the point in time, and the first power consumption is higher than the second power consumption. At least one of the first circuits is interleaved with at least one of the second circuits to reduce the operating temperature of the first circuit at the point in time.

[0004] In some embodiments, the layout design system includes at least one memory circuit and at least one processor circuit. The at least one memory circuit is used to store at least one program code, a temperature threshold and application data. The at least one processor circuit is used to execute the at least one program code to: select a plurality of first layout patterns and a plurality of second layout patterns according to the application data, wherein the first layout pattern corresponds to a plurality of first circuits of a first circuit system, and the second layout pattern corresponds to a plurality of second circuits of a second circuit system; alternately arrange at least one of the first layout patterns and at least one of the second layout patterns to generate a first layout data corresponding to a chip; confirm whether an operating temperature of the chip is lower than the temperature threshold according to the first layout data; and if the operating temperature is lower than the temperature threshold, manufacture the chip according to the first layout data.

[0005] In some embodiments, a layout design method includes the following operations: selecting a plurality of first layout patterns and a plurality of second layout patterns according to an application data, wherein the first layout pattern corresponds to a plurality of first circuits of a first circuit system, and the second layout pattern corresponds to a plurality of second circuits of a second circuit system; alternating at least one of the first layout patterns with at least one of the second layout patterns to generate a first layout data corresponding to a chip; confirming whether an operating temperature of the chip is lower than a temperature critical value according to the first layout data; and if the operating temperature is lower than the temperature critical value, manufacturing the chip according to the first layout data.

[0006] The technical features, practical operations and effects of the present invention are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of a chip according to some embodiments of the present invention is drawn;

[0008] Figure 2A According to some embodiments of the present invention, Figure 1 A schematic diagram of a first operation condition of a chip;

[0009] Figure 2B According to some embodiments of the present invention, Figure 1 A schematic diagram of a second operation condition of the chip;

[0010] Figure 2C To draw a schematic diagram of functional layout and operating temperature according to some related technologies;

[0011] Figure 2D According to some embodiments of the present invention, Figure 1 A schematic diagram of operating temperatures of a chip in a first operating condition and a second operating condition;

[0012] Figure 3 A schematic diagram of a layout design system according to some embodiments of the present invention is drawn;

[0013] Figure 4 A flow chart of a layout design method according to some embodiments of the present invention is drawn; and

[0014] Figure 5 According to some embodiments of the present invention, Figure 4 A conceptual diagram of multiple operations in . DETAILED DESCRIPTION

[0015] All words used in this application have their ordinary meanings. The definitions of the above words in commonly used dictionaries and the use examples of any words discussed herein in the context of the present invention are merely illustrative and should not limit the scope and meaning of the present invention. Similarly, the present invention is not limited to the various embodiments shown in this specification.

[0016] As used in this application, "coupled" or "connected" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used in this application, the term "circuitry" may be a single system formed by at least one circuit, and the term "circuit" may be a device that is connected in a certain manner by at least one transistor and / or at least one active and passive component to process signals.

[0017] As used in this application, the term "and / or" includes any combination of one or more of the listed associated items. In this application, the words first, second, third, etc. are used to describe and distinguish each component. Therefore, the first component in this application can also be referred to as the second component without departing from the original intention of the present invention. For ease of understanding, the same components in each figure will be designated by the same reference numeral.

[0018] Figure 1 A schematic diagram of a chip 100 is drawn according to some embodiments of the present invention. The chip 100 includes a circuit system 110 and a circuit system 120. The circuit system 110 includes a plurality of circuits 111-118 (drawn in solid lines), and the circuit system 120 includes a plurality of circuits 121-124 (drawn in dotted lines). In some embodiments, the plurality of circuits 111-118 have a first power consumption (e.g., Figure 2A or Figure 2B P1 shown), the plurality of circuits 121-124 have a second power consumption (eg, Figure 2A or Figure 2B P2 as shown), and the first power consumption is different from (for example, higher than) the second power consumption.

[0019] In some embodiments, the circuit system 110 is a receiver circuit system for connecting to the transmission interface 101, the circuit system 120 is a receiver circuit system for connecting to the transmission interface 102, and the transmission interface 101 is different from the transmission interface 102. For example, the transmission interface 101 is a V-by-One interface, and the plurality of circuits 111-118 can be respectively coupled to a plurality of lanes 00-07 in the transmission interface 101 to receive images via the V-by-One interface. The transmission interface 102 is a high definition multimedia interface (HDMI), and the plurality of circuits 121-124 can be respectively coupled to a plurality of lanes 0-3 in the transmission interface 102 to receive images and / or audio via HDMI.

[0020] In some embodiments, the chip 100 may have two operating states. Figure 2A , Figure 2A According to some embodiments of the present invention, Figure 1 FIG. 1 is a schematic diagram of a first operating condition of the chip 100. In the first operating condition, the chip 100 is configured to receive an image from an external resource (not shown) via the transmission interface 101. In this case, the plurality of circuits 111 to 118 operate (represented by dots) at a time point T1 to receive an image from an external resource via the transmission interface 101. In some embodiments, the time point T1 may be any time point in the process of the plurality of circuits 111 to 118 receiving an image from an external resource. In contrast, the plurality of circuits 121 to 124 do not operate at the time point T1. Accordingly, it should be understood that in the first operating condition, the power consumption P1 of the plurality of circuits 111 to 118 at the time point T1 is higher than the power consumption P2 of the plurality of circuits 121 to 124 at the time point T1.

[0021] Figure 2B According to some embodiments of the present invention, Figure 1 FIG. 1 is a schematic diagram of a second operating condition of the chip 100. In the second operating condition, the chip 100 is configured to receive images and / or audio from an external resource via the transmission interface 102. In this case, the plurality of circuits 121 to 124 operate (represented by dots) at a time point T1 to receive images and / or audio from an external resource via the transmission interface 102. In some embodiments, the time point T1 may be any time point in the process of the plurality of circuits 121 to 124 receiving images and / or audio from an external resource. In contrast, the plurality of circuits 111 to 118 do not operate at the time point T1. Accordingly, it should be understood that in the second operating condition, the power consumption P2 of the plurality of circuits 121 to 124 at the time point T1 is higher than the power consumption P1 of the plurality of circuits 111 to 118 at the time point T1.

[0022] Continue to refer to Figure 1 In some embodiments, at least one of the plurality of circuits 111-118 and at least one of the plurality of circuits 121-124 are arranged in an interlaced manner. For example, circuit 111, circuit 121, plurality of circuits 112-113, circuit 122, plurality of circuits 114-115, circuit 123, plurality of circuits 116-117, circuit 124, and circuit 118 are arranged in sequence along direction X.

[0023] Thus, when the plurality of circuits 111 to 118 are operating (for example, Figure 2A In the first operation case shown in FIG. 1 , the plurality of circuits 121 to 124 that are not in operation can be operated as heat sinks for the plurality of circuits 111 to 118 to reduce the operating temperature of the plurality of circuits 111 to 118. Similarly, when the plurality of circuits 121 to 124 are in operation (e.g., Figure 2B In the second operation condition shown in FIG. 1 , the plurality of circuits 111 - 118 that are not in operation may be operated as heat sinks for the plurality of circuits 121 - 124 to reduce the operating temperature of the plurality of circuits 121 - 124 .

[0024] Figure 2C A schematic diagram of functional layout and operating temperature is drawn according to some related technologies. In some related technologies, the layout design of the chip is mainly based on functionality. In these technologies, multiple circuits with the same function are all arranged together (ie, arranged adjacent to each other).

[0025] For example, Figure 2C As shown, multiple circuits 111-118 with the same function are all arranged together, and multiple circuits 121-124 with the same function. In these technologies, when multiple circuits 111-118 are in operation and multiple circuits 121-124 are not in operation (i.e., the first operation scenario mentioned above), the heat energy generated by the multiple circuits 111-118 will be concentrated at the locations of the multiple circuits 111-118. As a result, the operating temperature of the chip will exceed the temperature threshold TH, which may cause the reliability of the chip to decrease. In some embodiments, the temperature threshold TH is the upper limit of the temperature at which the chip can operate effectively. Similarly, in these technologies, when multiple circuits 121-124 are in operation and multiple circuits 111-118 are not in operation (i.e., the second operation scenario mentioned above), the heat energy generated by the multiple circuits 121-124 will be concentrated at the locations of the multiple circuits 121-124. As a result, the operating temperature of the chip will exceed the temperature threshold TH, which may cause the reliability of the chip to decrease. In order to avoid reliability degradation, these technologies require the use of additional heat sinks to cool the chip, which results in additional cost expenditure.

[0026] Figure 2D According to some embodiments of the present invention, Figure 1Schematic diagram of the operating temperature of the chip 100 in the first operating condition and the second operating condition. Compared with the above-mentioned related art, through the staggered arrangement, when the multiple circuits 111~118 are in operation and the multiple circuits 121~124 are not in operation (i.e. the aforementioned first operating condition), the heat energy generated by the multiple circuits 111~118 can be transferred to the adjacent multiple circuits 121~124, so that the operating temperature of the chip 100 can be lower than the temperature threshold TH. Similarly, when the multiple circuits 121~124 are in operation and the multiple circuits 111~118 are not in operation (i.e. the aforementioned second operating condition), the heat energy generated by the multiple circuits 121~124 can be transferred to the adjacent multiple circuits 111~118, so that the operating temperature of the chip 100 can be lower than the temperature threshold TH. In this way, the chip 100 can operate within a suitable temperature range without using an additional heat sink.

[0027] The above types of the circuit system 110, the circuit system 120, the transmission interface 101, and the transmission interface 102 are used for examples, and the present invention is not limited thereto. Various types of circuit systems 110, circuit systems 120, transmission interfaces 101, and transmission interfaces 102 are all within the scope of the present invention. The above numbers of the multiple circuits 111-118, the multiple circuits 121-124, the multiple channels 00-07, and the multiple channels 0-3 are used for examples, and the present invention is not limited thereto. Various numbers of circuits and channels are all within the scope of the present invention.

[0028] The first operation condition and the second operation condition are for example only, and the present invention is not limited thereto. FIG. 2A to FIG. 2D The circuit system 110 and the circuit system 120 in FIG. 1 are both operating at the time point T1, and the power consumption P1 of the circuit system 110 at the time point T1 is higher (or may be lower) than the power consumption P2 of the circuit system 120 at the time point T1. In this way, the circuit system 110 (or 120) with lower power consumption can operate as a heat sink for the circuit system 120 (or 110) with higher power consumption at the time point T1.

[0029] Figure 3 A schematic diagram of a layout design system 300 is drawn according to some embodiments of the present invention. The layout design system 300 includes at least one processor circuit 310, at least one memory circuit 320, and at least one input / output interface 330.

[0030] At least one processor circuit 310 is coupled to at least one memory circuit 320 and at least one input / output interface 330. In various embodiments, at least one processor circuit 310 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a multi-core processor circuit, a distributed processing system, etc. Various circuits or systems that can be used to implement at least one processor circuit 310 are within the scope of the present invention.

[0031] At least one memory circuit 320 stores at least one program code PP for assisting in designing the layout of the integrated circuit. At least one processor circuit 310 can execute at least one program code PP and generate operations (e.g., Figure 4 Multiple operations S410, S420, S430, S440 and S450) in the process may be automatically performed.

[0032] In some embodiments, at least one memory circuit 320 further stores a temperature threshold TH, application data SD, and a layout pattern database LD. The application data SD includes predictable operation information of the chip 100, which can be generated in advance through circuit simulation. For example, the application data SD includes power consumption information D1, power consumption information D2, and operation information D3. The power consumption information D1 is used to indicate the power consumption P1 of the circuit system 110 at the time point T1. The power consumption information D2 is used to indicate the power consumption P2 of the circuit system 120 at the time point T1. The operation information D3 is used to indicate the operating conditions of the circuit system 110 and the circuit system 120 (for example, Figure 2A The first operation scenario is Figure 2B For example, the operation information D3 may indicate that when one of the circuit system 110 (i.e., the plurality of circuits 111-118) and the circuit system 120 (i.e., the plurality of circuits 121-124) operates at the time point T1, the other of the circuit system 110 and the circuit system 120 does not operate at the time point T1. Alternatively, in other embodiments, the operation information D3 may indicate that both the circuit system 110 (i.e., the plurality of circuits 111-118) and the circuit system 120 (i.e., the plurality of circuits 121-124) operate at the time point T1.

[0033] The layout pattern database LD stores a plurality of layout patterns corresponding to the plurality of circuits 111 to 118, a plurality of layout patterns corresponding to the plurality of circuits 121 to 124, and / or a plurality of layout patterns corresponding to other circuits (such as the following layout patterns). Figure 5). At least one processor circuit 310 may select a suitable layout pattern from the layout pattern database LD according to the power consumption information D1, the power consumption information D2, and the operation information D3, and set the selected layout pattern according to the temperature threshold TH to generate the first layout data DL (or at least one second layout data DL') that can meet the temperature requirement. In other embodiments, at least one memory circuit 320 may also store other layout constraint information. In this way, at least one processor circuit 310 may automatically generate the suitable first layout data DL (or at least one second layout data DL') according to these layout constraints. For example, other layout constraints may be (but not limited to) area, lower temperature limit, etc.

[0034] In some embodiments, at least one memory circuit 320 is a non-transitory computer-readable storage medium that stores a plurality of programs for executing Figure 4 In some embodiments, the non-transitory computer readable storage medium may be an electrical, magnetic, optical, infrared and / or semiconductor system. For example, the non-transitory computer readable storage medium includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory, read-only memory, hard disk and / or optical disk. In other embodiments, the non-transitory computer readable storage medium includes a read-only memory compact disk, a rewritable compact disk and / or a digital laser video disk.

[0035] At least one input-output interface 330 receives a plurality of inputs or commands from various control devices, wherein the control devices may be controlled by a circuit designer or a layout designer. Accordingly, the layout design system 300 may be controlled based on the commands received by the at least one input-output interface 330. In some embodiments, the at least one input-output interface 330 includes a screen configured to display the state of program code execution and / or the aforementioned first layout data DL (or at least one second layout data DL'). In some embodiments, the at least one input-output interface 330 includes a graphical user interface. In other embodiments, the at least one input-output interface 330 includes a keyboard, a numeric keypad, a mouse, a trackball, a touch screen, a cursor arrow key, or a combination thereof, to communicate information and a plurality of commands to the at least one processor circuit 310.

[0036] Figure 4 A flow chart of a layout design method 400 is drawn according to some embodiments of the present invention. In some embodiments, the layout design method 400 may be (but not limited to) Figure 3In operation S410, a plurality of first layout patterns and a plurality of second layout patterns are selected according to application data, wherein the first layout patterns correspond to a plurality of first circuits of a first circuit system, and the second layout patterns correspond to a plurality of second circuits of a second circuit system.

[0037] In operation S420 , at least one of the first layout patterns and at least one of the second layout patterns are alternately arranged to generate layout data corresponding to a chip (eg, first layout data DL).

[0038] In operation S430, it is confirmed whether the operating temperature of the chip is lower than the temperature threshold value according to the layout data. If the operating temperature is lower than the temperature threshold value TH, operation S450 is performed. Alternatively, if the operating temperature is not lower than the temperature threshold value TH, operation S420 is re-performed to reset at least a portion of the first layout data and at least a portion of the second layout pattern to generate new layout data (e.g., at least one second layout data DL'). In operation S440, if the chip operating temperatures corresponding to all layout data (e.g., the first layout data DL and at least one second layout data DL') are not lower than the temperature threshold value TH, the layout data corresponding to the lowest chip operating temperature is selected from all layout data.

[0039] In operation S450, the layout data is output to manufacture a chip according to the layout data.

[0040] To illustrate the layout design method 400, refer to Figure 5 ,and Figure 5 According to some embodiments of the present invention, Figure 4 A conceptual diagram of multiple operations in . Figure 5 As shown, the layout pattern database LD stores layout patterns corresponding to a plurality of circuits, including layout patterns corresponding to a plurality of circuits 111 to 118 (represented by horizontal stripes), layout patterns corresponding to a plurality of circuits 121 to 124 (represented by vertical stripes), and layout patterns corresponding to other circuits (represented by oblique lines). In some embodiments, each of the layout patterns of the plurality of circuits may be an integrated circuit layout diagram that represents structures such as metal layers, semiconductor layers, isolation layers, contacts, and vias (VIA) in planar geometric shapes. In some embodiments, the layout patterns of the plurality of circuits may be pre-designed and stored in Figure 3 At least one memory circuit 320.

[0041] According to the power consumption information D1, the power consumption information D2, and the operation information D3, at least one processor circuit 310 can know that at the time point T1, one of the circuit system 110 and the circuit system 120 has high power consumption and the other of the circuit system 110 and the circuit system 120 has low power consumption. Therefore, at least one processor circuit 310 selects layout patterns corresponding to the plurality of circuits 111-118 (i.e., the circuit system 110) and layout patterns corresponding to the plurality of circuits 121-124 (i.e., the circuit system 120) from the layout pattern database LD (i.e., operation S410).

[0042] Next, at least one processor circuit 310 may alternately arrange layout patterns corresponding to the plurality of circuits 111-118 and layout patterns corresponding to the plurality of circuits 121-124. For example, the layout pattern corresponding to circuit 111, the layout pattern corresponding to circuit 121, the layout pattern corresponding to the plurality of circuits 112-113, the layout pattern corresponding to circuit 122, the layout pattern corresponding to the plurality of circuits 114-115, the layout pattern corresponding to circuit 123, the layout pattern corresponding to the plurality of circuits 116-117, the layout pattern corresponding to circuit 124, and the layout pattern corresponding to circuit 118 are sequentially arranged along Figure 5 The corresponding relationship between the above-mentioned plurality of layout patterns and the plurality of circuits 111 to 118 and 121 to 124 can be referred to Figure 1 or Figure 2D In some embodiments, after the above-mentioned plurality of layout patterns are set, at least one processor circuit 310 may execute an automatic routing procedure according to the set layout patterns to generate initial layout data (e.g., first layout data DL). In some embodiments, the above-mentioned operation may be referred to as an automatic planning procedure.

[0043] Furthermore, at least one processor circuit 310 performs simulation according to the first layout data DL to confirm whether the operating temperature of the chip 100 is lower than the temperature threshold TH (i.e., operation S430). For example, at least one processor circuit 310 may perform a post-layout simulation according to the first layout data DL to confirm whether the operating temperature of the chip 100 is lower than the temperature threshold TH. Figure 5 As shown, if the operating temperature is lower than the temperature threshold TH, at least one processor circuit 310 may output the first layout data DL to manufacture the chip 100 according to the first layout data DL (i.e., operation S450). For example, at least one processor circuit 310 may store the first layout data DL in at least one memory circuit 320. The semiconductor manufacturing plant may produce the chip 100 according to the first layout data DL.

[0044] On the contrary, if the operating temperature is not lower than the temperature threshold TH, at least one processor circuit 310 may reset the layout pattern to generate at least one second layout data DL'. At least one processor circuit 310 performs simulation again according to at least one second layout data DL' to confirm whether the operating temperature of the chip 100 is lower than the temperature threshold TH. For example, at least one processor circuit 310 may set more layout patterns corresponding to low power circuits between multiple layout patterns corresponding to high power circuits to generate at least one second layout data DL'. In this way, more low power circuits can dissipate heat for high power circuits to achieve the effect of lowering the temperature. In some embodiments, if the chip operating temperature corresponding to all at least one second layout data DL' is not lower than the temperature threshold TH, at least one processor circuit 310 selects a layout data corresponding to the lowest operating temperature from the first layout data DL and at least one second layout data DL' (such as operation S440), and manufactures the chip 100 according to this layout data (i.e., operation S450). In this way, the number of heat sinks that may be required for the chip 100 can be reduced.

[0045] In some embodiments, the layout design system 300 and / or the layout design method 400 can be used with common auxiliary design tools in the industry to generate the first layout data DL or the second layout data DL'. For example, the auxiliary design tools include (but are not limited to) Synopsys IC Compiler, Cadence Innovus, etc.

[0046] The description of the multiple operations of the above-mentioned layout design method 400 can refer to the above-mentioned multiple embodiments, so it will not be repeated here. The above-mentioned multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present invention, the various operations under the layout design method 400 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, one or more operations under the layout design method 400 can be performed simultaneously or partially simultaneously.

[0047] In summary, the chip, layout design system and method in some embodiments of the present invention can automatically generate a chip floor plan based on layout constraints such as temperature thresholds and operating conditions. In this way, part of the circuit in the chip can be operated as a heat sink in actual applications to prevent the chip from operating at too high a temperature and reduce the number of additional heat sinks.

[0048] Although the embodiments of the present invention are described above, the embodiments are not intended to limit the present invention. Personnel with ordinary knowledge in the technical field may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All such changes may fall within the scope of protection required by the present invention.

[0049] Description of reference numerals:

[0050] 0~3,00~07: Channel

[0051] 100: Chip

[0052] 101,102: Transmission interface

[0053] 110,120: Circuit system

[0054] 111~118,121~124: Circuit

[0055] X: Direction

[0056] P1, P2: Power consumption

[0057] 300:Layout Design System

[0058] 310: At least one processor circuit

[0059] 320: At least one memory circuit

[0060] 330: At least one input and output interface

[0061] D1, D2: Power consumption information

[0062] D3: Operational Information

[0063] DL: First layout data

[0064] DL': at least one second layout data

[0065] LD: Layout Pattern Database

[0066] PP: At least one program code

[0067] SD: Application Data

[0068] TH: Temperature threshold

[0069] 400:Layout Design Method

[0070] S410, S420, S430, S440, S450: Operation

Claims

1. A chip, comprising: A first circuit system, comprising a plurality of first circuits, wherein the first circuits have a first power consumption at a time point; as well as a second circuit system, comprising a plurality of second circuits, wherein the second circuit has a second power consumption at the time point, and the first power consumption is higher than the second power consumption, At least one of the first circuits is interleaved with at least one of the second circuits to reduce the operating temperature of the first circuit at the time point.

2. The chip according to claim 1, characterized in that: When the first circuit system operates at the time point, the second circuit system does not operate at the time point, or both the first circuit system and the second circuit system operate at the time point.

3. The chip according to claim 1, characterized in that: When the first circuit operates at the time point, the second circuit operates as a heat sink of the first circuit at the time point.

4. The chip according to claim 1, characterized in that: The first circuit system is a first receiver circuit system for connecting to a first transmission interface, the second circuit system is a second receiver circuit system for connecting to a second transmission interface, and the first transmission interface is different from the second transmission interface.

5. The chip according to claim 4, characterized in that: The first circuits are respectively coupled to a plurality of channels in the first transmission interface, and the second circuits are respectively coupled to a plurality of channels in the second transmission interface.

6. The chip according to claim 4, characterized in that: One of the first transmission interface and the second transmission interface is a V-by-One interface, and the other of the first transmission interface and the second transmission interface is a high-definition multimedia interface.

7. A layout design system, comprising: At least one memory circuit for storing at least one program code, a temperature threshold value and an application data; as well as At least one processor circuit is used to execute the at least one program code to: selecting a plurality of first layout patterns and a plurality of second layout patterns according to the application data, wherein the first layout patterns correspond to a plurality of first circuits of a first circuit system, and the second layout patterns correspond to a plurality of second circuits of a second circuit system; Alternately arranging at least one of the first layout patterns and at least one of the second layout patterns to generate a first layout data corresponding to a chip; confirming whether an operating temperature of the chip is lower than the temperature threshold according to the first layout data; as well as If the operating temperature is lower than the temperature threshold, the chip is manufactured according to the first layout data.

8. The layout design system according to claim 7, characterized in that: The application data includes a first power consumption information and a second power consumption information, wherein the first power consumption information indicates a first power consumption of the first circuit at a time point, and the second power consumption information indicates a second power consumption of the second circuit at the time point, and the first power consumption is higher than the second power consumption.

9. The layout design system according to claim 7, characterized in that: The at least one processor circuit is further configured to: If the operating temperature is not lower than the temperature threshold, resetting the first layout pattern and the second layout pattern to generate at least one second layout data corresponding to the chip; as well as If the operating temperatures of the chip corresponding to all of the at least one second layout data are not lower than the temperature threshold, the chip is manufactured according to one of the first layout data and the at least one second layout data corresponding to a lowest operating temperature.

10. A layout design method, comprising: selecting a plurality of first layout patterns and a plurality of second layout patterns according to an application data, wherein the first layout patterns correspond to a plurality of first circuits of a first circuit system, and the second layout patterns correspond to a plurality of second circuits of a second circuit system; Alternately arranging at least one of the first layout patterns and at least one of the second layout patterns to generate a first layout data corresponding to a chip; confirming whether an operating temperature of the chip is lower than a temperature threshold according to the first layout data; as well as If the operating temperature is lower than the temperature threshold, the chip is manufactured according to the first layout data.

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