Reliability testing method, device, electronic device and storage medium for flash memory chip

Abstract

The present invention relates to the technical field of semiconductor integrated circuits, and specifically discloses a reliability test method, device, electronic equipment and storage medium for a flash memory chip, wherein the method comprises the following steps: dividing the storage area of ​​a flash memory chip into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division units; repeatedly and sequentially performing a, n*a and m*a cycle operations on the lightly erased area, the medium erased area and the heavily erased area respectively, until the heavily erased area completes a preset number of cycle operations; obtaining the erasure time of the heavily erased area in the cycle operation; the method can simulate the characteristics of different degrees of operation in different areas when the chip is actually used, so that the erasure time finally obtained is used to identify the durability and data retention capability of the flash memory chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit technology, and in particular to a reliability testing method, device, electronic device and storage medium for a flash memory chip. Background Art

[0002] The service life of storage cells is one of the key performance indicators of flash memory chip products, and the reliability testing of flash memory chips is becoming increasingly important.

[0003] The industry usually selects some storage units of the memory chip for cycle operation to evaluate the reliability of its service life and verify the differences between the sectors\blocks in the test area.

[0004] The existing testing method generally performs 100k cycle operations on some sectors to obtain the corresponding erase time to evaluate the reliability of flash memory chips. This method performs read, write and erase operation addresses in sequence on the same area, which cannot fully simulate the actual usage scenarios of customers, resulting in excessive use of a single sector area and cannot reflect the impact of the usage of other storage areas on the storage area.

[0005] There is currently no effective technical solution to the above problems. Summary of the invention

[0006] The purpose of the present application is to provide a reliability testing method, device, electronic device and storage medium for a flash memory chip, so as to simulate the characteristics of different degrees of operation in different areas when the chip is actually used, so as to achieve better testing results.

[0007] In a first aspect, the present application provides a reliability testing method for a flash memory chip, for testing the flash memory chip to obtain data that can be used to identify the durability and data retention capability of the flash memory chip, the method comprising the following steps:

[0008] The flash memory chip storage area is divided into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division unit;

[0009] Repeating and sequentially performing a, n*a, and m*a cycle operations on the lightly erased area, the medium erased area, and the heavily erased area, respectively, until the heavily erased area completes a preset number of cycle operations, wherein a, n, and m are all positive integers, and m>n;

[0010] Get the erasure time of the heavy erase area in the cycle operation.

[0011] The reliability test method of a flash memory chip of the present application performs cycle operations of different degrees on a lightly erased area, a medium erased area, and a heavily erased area to simulate the characteristics of different degrees of operation in different areas when the chip is actually used, so as to achieve better test results and more accurately reflect the reliability of the flash memory chip.

[0012] A reliability testing method for a flash memory chip, wherein the erase time is a first total erase time accumulated when the heavy erase area completes a preset number of cycle operations, or includes a second total erase time accumulated when the heavy erase area completes a preset interval number of cycle operations, or includes a maximum erase time, a minimum erase time and an intermediate erase time when the heavy erase area completes a preset interval number of cycle operations.

[0013] The reliability test method of a flash memory chip, wherein the step of dividing the flash memory chip storage area into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division unit comprises the following sub-steps:

[0014] Dividing the flash memory chip storage area into a plurality of test groups by taking sectors or blocks as the minimum division units;

[0015] Each of the test groups is divided into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area based on the minimum division unit.

[0016] In a reliability test method for a flash memory chip in this example, each test group is divided into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area, so that the method can test one or more test groups.

[0017] The reliability test method of a flash memory chip, wherein, in the same test group, the heavily erased area, the moderately erased area, the lightly erased area and the non-erased area are arranged adjacent to each other in sequence.

[0018] In this example, a reliability test method for a flash memory chip is used to divide the smallest division units in a test group into a heavily erased area, a moderately erased area, a lightly erased area, and an unerased area in an adjacent order, which can better simulate the actual use of the flash memory chip.

[0019] The reliability testing method of a flash memory chip further comprises the following steps:

[0020] The threshold voltages of the heavily erased area, the moderately erased area, the lightly erased area, and the non-erased area are respectively obtained.

[0021] The reliability testing method of a flash memory chip further comprises the following steps:

[0022] Obtaining the erasure time of the medium erasure area and / or the light erasure area in the cycle operation.

[0023] A reliability testing method for a flash memory chip, wherein the number of the minimum division units occupied by the lightly erased area is greater than the number of the minimum division units occupied by the moderately erased area, and the number of the minimum division units occupied by the moderately erased area is greater than the number of the minimum division units occupied by the heavily erased area.

[0024] In a second aspect, the present application also provides a flash memory chip reliability testing device, which is used to test the flash memory chip to obtain data that can be used to identify the durability and data retention capability of the flash memory chip, and the device includes:

[0025] A partition module is used to divide the flash memory chip storage area into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division unit;

[0026] an operation module, configured to repeatedly and sequentially perform a, n*a, and m*a cycle operations on the lightly erased area, the medium erased area, and the heavily erased area, respectively, until the heavily erased area completes a preset number of cycle operations, wherein a, n, and m are all positive integers, and m>n;

[0027] The acquisition module is used to obtain the erasure time of the heavy erase area in the cycle operation.

[0028] The reliability test device of a flash memory chip of the present application divides the storage area of ​​the flash memory chip into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area by using a partition module, and performs cycle operations of different degrees on the lightly erased area, the medium erased area and the heavily erased area by using an operation module to simulate the characteristics of different degrees of operation in different areas when the chip is actually used, so that the erase time finally obtained for identifying the durability and data retention ability of the flash memory chip can make the test effect better and more accurately reflect the reliability of the flash memory chip.

[0029] In a third aspect, the present application further provides an electronic device, comprising a processor and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method provided in the first aspect are executed.

[0030] In a fourth aspect, the present application further provides a storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps in the method provided in the first aspect are executed.

[0031] As can be seen from the above, the present application provides a reliability testing method, device, electronic device and storage medium for a flash memory chip, wherein the method divides the storage area of ​​the flash memory chip into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area, and performs different degrees of cycle operations on the lightly erased area, the medium erased area and the heavily erased area to simulate the characteristics of different degrees of operation in different areas during actual use of the chip, so that the erasure time finally obtained for identifying the durability and data retention capability of the flash memory chip can make the test effect better and more accurately reflect the reliability of the flash memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flowchart of a reliability testing method for a flash memory chip provided in an embodiment of the present application.

[0033] Figure 2 A schematic diagram of the structure of a reliability testing device for a flash memory chip provided in an embodiment of the present application.

[0034] Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0036] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0037] The existing flash memory chip reliability test method includes the following steps:

[0038] 1. Select the sector address to be operated;

[0039] 2. Erase, check, write data, and verify data on the sector (i.e., one cycle operation), and record the erasure time;

[0040] 3. Execute step 2 100k times in a loop and calculate the erasing time.

[0041] This testing method has the following defects:

[0042] Only some sectors in the chip array were selected for operation. The test area was insufficient to fully cover the entire chip. In addition, the obtained reliability data was insufficient to support the evaluation of the actual performance of the product.

[0043] It cannot fully simulate the actual usage scenarios of customers, and only performs excessive operations on a single sector area. It cannot reflect the impact of operations in other areas on this area, nor can it reflect the impact of this area on other areas.

[0044] First, please refer to Figure 1 , Figure 1 A reliability testing method for a flash memory chip in some embodiments of the present application is used to test the flash memory chip to obtain data that can be used to identify the durability and data retention capability of the flash memory chip. The method includes the following steps:

[0045] S1, dividing the flash memory chip storage area into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division unit;

[0046] Specifically, the flash memory chip storage area is composed of a plurality of sectors or a plurality of blocks, and the flash memory chip storage area is divided according to sectors or blocks, so that the method of the embodiment of the present application takes sectors or blocks as the minimum operation unit, that is, the read, write and erase operation commands in the test process take sectors or blocks as the minimum operation unit, ensuring that the entire operation can be executed smoothly and efficiently; in addition, sectors and blocks have certain regional characteristics, and the flash memory chip storage area can be divided according to regions, so that the erase time obtained by subsequent operations can reflect the mutual influence between different regions; in the embodiment of the present application, it is preferred to divide the flash memory chip storage area with sectors as the minimum division unit, so that the lightly erased area, the medium erased area, the heavily erased area and the non-erased area each contain at least one sector.

[0047] More specifically, the method of the embodiment of the present application sets the lightly erased area, the medium erased area, and the heavily erased area as areas for performing test operations of different degrees or times, respectively, and the unerased area is an area where no test operations are performed. This division method is used to simulate the characteristics of different degrees of operations in different areas during actual use of the chip, so that the method of the embodiment of the present application can accurately obtain the test results, making the test results more reliable.

[0048] S2, repeatedly and sequentially perform a, n*a, and m*a cycle operations on the lightly erased area, the medium erased area, and the heavily erased area, respectively, until the heavily erased area completes a preset number of cycle operations, wherein a, n, and m are all positive integers, and m>n;

[0049] Specifically, this step sequentially performs a, n*a, and m*a cycle operations on the lightly erased area, the medium erased area, and the heavily erased area, respectively, and repeats this operation process until the heavily erased area completes a preset number of cycle operations. If it is repeated b times (i.e., the preset number is b*m*a), the lightly erased area, the medium erased area, and the heavily erased area perform b*a, b*n*a, and b*m*a cycle operations, respectively, so that the heavily erased area performs the largest number of cycle operations and the lightly erased area performs the least number of cycle operations, thereby simulating the characteristics of different degrees of operation in different areas during actual chip use.

[0050] More specifically, the flash memory chip test needs to perform a certain number of cycle operations to obtain data reflecting the reliability of the flash memory chip, so a preset number of heavily erased areas is set as the upper limit of the number of cycle operations. For example, if the preset number is 100k times, the heavily erased area will no longer be cycled after performing 100k cycle operations.

[0051] More specifically, the cycle operation is a plurality of operation commands that are commonly used and can be repeatedly executed during chip testing, which includes four operations of erasing, checking for blanks, writing data, and verifying data that are executed in sequence.

[0052] S3. Obtain the erasure time of the heavily erased area in the cycle operation.

[0053] Specifically, step S2 can record the time consumed by the erasing operation in each cycle operation when executing the operation, and step S3 is to obtain these times in the heavily erased area, which can reflect the data of the time consumed by the erasing operation in the heavily erased area when completing the cycle operation; the heavily erased area is the area with the most erase operations, and the erase time of this area can effectively reflect the reliability of the flash memory chip.

[0054] More specifically, after obtaining the erase time of the heavily erased area in the cycle operation, the data can be compared with existing data or corresponding data or process parameters of other products to analyze and identify the durability and data retention capability of the flash memory chip.

[0055] More specifically, in one cycle of step S2, the lightly erased area performs a cycle operation, the medium erased area performs n*a cycle operations, and the heavily erased area performs m*a cycle operations, which can simulate that when a certain storage area performs the maximum number of erase and programming operations, its nearby storage areas perform erase and programming operations to varying degrees; the method of the embodiment of the present application sets a lightly erased area and a medium erased area and performs a certain degree of cycle operations on the lightly erased area and the medium erased area, and the erasure time of the heavily erased area in the cycle operation finally obtained in step S3 reflects to a certain extent the influence of the different degrees of cycle operations on the erase time of other storage areas, making the test result more representative.

[0056] A reliability testing method for a flash memory chip in an embodiment of the present application divides the storage area of ​​the flash memory chip into a lightly erased area, a medium erased area, a heavily erased area, and a non-erased area, and performs cycle operations of different degrees on the lightly erased area, the medium erased area, and the heavily erased area to simulate the characteristics of different degrees of operation in different areas when the chip is actually used, so that the erasure time finally obtained for identifying the durability and data retention capability of the flash memory chip can make the test effect better and more accurately reflect the reliability of the flash memory chip.

[0057] In some preferred embodiments, the preset number is 100k times, which is the number of cycle operations commonly used in flash memory chip reliability testing. The erase time obtained by performing 100k cycle operations on the heavily erased area can effectively characterize the reliability of the chip and can be compared and analyzed with some existing test results.

[0058] Specifically, assuming that the number of repetitions of step S2 is b, then m*a=100k / b, thereby determining the number of times the cycle operation is performed in each cycle of the heavily erased area.

[0059] Preferably, in the embodiment of the present application, a=1, n=10, m=100, so step S2 is:

[0060] The lightly erased area, the medium erased area, and the heavily erased area are repeatedly and sequentially subjected to 1, 10, and 100 cycle operations respectively, until the heavily erased area completes 100k cycle operations.

[0061] By adopting the above design method, in one cycle, the lightly erased area performs one cycle operation, the medium erased area performs 10 cycle operations, and the heavily erased area performs 100 cycle operations. When the test is finally completed, the lightly erased area, the medium erased area, and the heavily erased area have completed 1k, 10k, and 100k cycle operations respectively. The erasing time finally obtained can reflect the influence of the erasing operations of the lightly erased area and the medium erased area on the erasing time of the heavily erased area.

[0062] In some preferred implementations, the write data operation in the cycle operation is to write one type of programming data among 55, aa, a5, 5a, CKBD, and ICKBD, and the type of programming data can be set according to test requirements.

[0063] In some preferred embodiments, the programming data is preferably CKBD (checkerboard data), which is expressed as alternating 0 and 1 data, that is, each data 1 has data 0 on all four sides, and each data 0 has data 1 on all four sides. This data design can more closely simulate the characteristics of random writing, and each minimum division unit has an equal amount of data 0 and data 1. The time spent on erasing such data in a cycle operation can better characterize the change in the threshold voltage of the storage unit.

[0064] In some preferred embodiments, the erase time is the first total erase time accumulated for the heavy erase area to complete a preset number of cycle operations; specifically, the first total erase time can represent the cumulative time taken for the heavy erase area to perform 100k cycle operations, i.e., erase 100k times, and the cumulative time can reflect the durability and data retention capability of the flash memory chip. Combined with the light erase area, medium erase area and non-erased area designed by the method of the embodiment of the present application, the first total erase time simulates and represents the erase time actually consumed by the flash memory chip for 100k erase and write operations, and reflects the reliability of the flash memory chip from the overall usage result.

[0065] In some preferred embodiments, the erase time includes a second total erase time accumulated each time a preset number of cycle operations are completed in the heavy erase area; specifically, the second total erase time can represent the time consumed for each heavy erase operation to execute a certain number of erase operations. According to the change rule of the second total erase time, it can reflect the changes in the durability and data retention ability of the flash memory chip when the number of erase times gradually increases. Combined with the light erase area, medium erase area and non-erased area designed by the method of the embodiment of the present application, the second total erase time simulates and represents the changes in the erase time consumed by the flash memory chip for 100k erase and write operations, reflecting the reliability of the flash memory chip from the entire use process.

[0066] More specifically, the preset interval number is preferably 500 times, that is, the second total erasing time is the total time consumed by the erasing operation in every 500 cycle operations of the heavy erasing area.

[0067] In some preferred embodiments, the erasure time includes the maximum erasure time, the minimum erasure time and the intermediate erasure time in each cycle operation in which a preset number of intervals are completed in the heavy erasure area; specifically, the maximum erasure time, the minimum erasure time and the intermediate erasure time can represent the longest time, the shortest time and the intermediate time in the time consumed for each certain number of erasure operations of the heavy erasure. According to the change law of the maximum erasure time, the minimum erasure time and the intermediate erasure time, the durability and data retention ability of the flash memory chip can be reflected as the erasure efficiency of different storage units therein gradually increases when the number of erasures increases. Combined with the lightly erased area, the medium erased area and the non-erased area designed by the method of the embodiment of the present application, the maximum erasure time, the minimum erasure time and the intermediate erasure time simulate and represent the change of the erasure time consumed by different storage units when the flash memory chip is actually used for 100k erase and write operations, that is, it can represent the time for erasing different storage units at different stages, reflecting the reliability of the flash memory chip from the entire use process.

[0068] More specifically, the preset interval number is preferably 500 times, that is, the maximum erase time, the minimum erase time and the middle erase time are the longest time, the shortest time and the middle time of the time consumed by the erase operation in every 500 cycle operation of the heavy erase area.

[0069] In some preferred embodiments, the step of dividing the flash memory chip storage area into a lightly erased area, a medium erased area, a heavily erased area, and a non-erased area with sectors or blocks as the minimum division unit includes the following sub-steps:

[0070] S11, dividing the flash memory chip storage area into multiple test groups with sectors or blocks as the minimum division units;

[0071] Specifically, by dividing the storage area of ​​the flash memory chip into multiple test groups and then performing multiple tests, the method of the embodiment of the present application can perform reliability tests on multiple areas of the same flash memory chip, so that the test results can more accurately reflect the durability and data retention capability of the flash memory chip.

[0072] S12. Divide each test group into a lightly erased area, a medium erased area, a heavily erased area, and a non-erased area based on the smallest division unit.

[0073] Specifically, each test group is divided into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area, so that steps S2 and S3 can test one or more test groups.

[0074] In some preferred implementations, in the same test group, the heavy-erasure area, the medium-erasure area, the light-erasure area, and the non-erasure area are arranged adjacent to each other in sequence.

[0075] Specifically, when flash memory chips are used, erase and write operations often cluster. Therefore, dividing the smallest division units in the test group into heavily erased areas, moderately erased areas, lightly erased areas, and non-erased areas in an adjacent order can better simulate the actual use of flash memory chips.

[0076] In some preferred embodiments, the method further comprises the following steps:

[0077] S3', respectively obtaining the threshold voltages of the heavily erased area, the medium erased area, the lightly erased area and the unerased area.

[0078] Specifically, step S3' can be executed before step S3 or after step S3. The acquired threshold voltage can reflect the degree of change of the threshold voltage in the area of ​​the flash memory chip with different erase times. The threshold voltage can also reflect the data retention ability of the flash memory chip after different degrees of erase operations, and can also be used to analyze the threshold voltage consistency of storage cells in different erase areas after different degrees of erase operations (whether they are concentrated in a certain threshold voltage range).

[0079] In some preferred embodiments, the method further comprises the following steps:

[0080] S3'', obtaining the erasing time of the medium erasing area and / or the light erasing area in the cycle operation.

[0081] Specifically, S3'' can be executed before step S3 or after step S3 or simultaneously with step S3. The erasing time of the medium erase area and the light erase area can reflect the reliability of the flash memory chip after different degrees of erasure operations, and can be used as a secondary identification item for reliability testing.

[0082] In some preferred embodiments, the number of minimum division units occupied by the heavily erased area, the moderately erased area, the lightly erased area and the unerased area may be the same or different. In the present application, they are preferably different to simulate storage units with different degrees of erase covering areas of different sizes during actual use of different flash memory chips.

[0083] In some preferred embodiments, the number of minimum division units occupied by the lightly erased area is greater than the number of minimum division units occupied by the moderately erased area, the number of minimum division units occupied by the moderately erased area is greater than the number of minimum division units occupied by the heavily erased area, and the remaining storage areas are all non-erased areas.

[0084] Specifically, when the flash memory chip is actually used, the deeper the degree of erasure, the fewer the number of storage units. Therefore, the number of minimum division units contained in the heavily erased area, the moderately erased area, and the lightly erased area in the embodiment of the present application is set incrementally, so that the method of the embodiment of the present application can better simulate the actual use of the flash memory chip during testing, that is, it can fully simulate the actual use scenario of the customer, so that the erase time obtained by the test can better reflect the reliability of the flash memory chip.

[0085] Second, please refer to Figure 2 , Figure 2 A flash memory chip reliability test device provided in some embodiments of the present application is used to test the flash memory chip to obtain data that can be used to identify the durability and data retention capability of the flash memory chip. The device includes:

[0086] The partition module 201 is used to divide the flash memory chip storage area into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division units;

[0087] An operation module 202 is used to repeatedly and sequentially perform a, n*a, and m*a cycle operations on the lightly erased area, the medium erased area, and the heavily erased area, respectively, until the heavily erased area completes a preset number of cycle operations, wherein a, n, and m are all positive integers, and m>n;

[0088] The acquisition module 203 is used to acquire the erasure time of the heavily erased area in the cycle operation.

[0089] A reliability testing device for a flash memory chip in an embodiment of the present application utilizes a partitioning module 201 to divide the storage area of ​​the flash memory chip into a lightly erased area, a medium erased area, a heavily erased area, and a non-erased area, and performs cycle operations of different degrees on the lightly erased area, the medium erased area, and the heavily erased area through an operation module 202 to simulate the characteristics of different degrees of operation in different areas when the chip is actually used, so that the erasure time finally obtained for identifying the durability and data retention capability of the flash memory chip can achieve better test results and more accurately reflect the reliability of the flash memory chip.

[0090] In some preferred embodiments, the reliability testing device for a flash memory chip is used to execute the reliability testing method for a flash memory chip provided in the first aspect.

[0091] In some preferred implementations, the acquisition module 203 is further configured to respectively acquire the threshold voltages of the heavily erased area, the moderately erased area, the lightly erased area, and the non-erased area.

[0092] In some preferred implementations, the acquisition module 203 is further configured to acquire the erasure time of the medium-erasure area and / or the light-erasure area in the cycle operation.

[0093] Third, please refer to Figure 3 , Figure 3 This is a structural diagram of an electronic device provided in an embodiment of the present application. The present application provides an electronic device 3, including: a processor 301 and a memory 302. The processor 301 and the memory 302 are interconnected and communicate with each other via a communication bus 303 and / or other forms of connection mechanisms (not shown). The memory 302 stores a computer program executable by the processor 301. When the electronic device 3 is running, the processor 301 executes the computer program to execute the method in any optional implementation of the above-mentioned embodiment.

[0094] In a fourth aspect, an embodiment of the present application provides a storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method in any optional implementation of the above embodiment is executed. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory.

[0095] Example 1

[0096] This embodiment uses a 32-bit single-chip microcomputer STM32 MCU to execute the method provided in the first aspect to perform reliability testing on a spi-norflash flash memory chip, where the capacity of the flash memory chip is 64Mbit, that is, it has 1024 sectors.

[0097] The test process is as follows:

[0098] A1. Erase the entire flash memory chip, check for blanks, write CKBD data, and perform data verification;

[0099] A2. Addresses are equally grouped by sector size into 32 test groups, each test group having 32 sectors; each test group is divided into a heavily erased area, a moderately erased area, a lightly erased area and a non-erased area in sequence, wherein the heavily erased area, the moderately erased area, the lightly erased area and the non-erased area occupy 1 sector, 4 sectors, 15 sectors and 12 sectors respectively, the number of cycles i is set to 1, one or more test groups are set to be tested, and all test groups are tested in this embodiment;

[0100] A3, perform one cycle operation on the lightly erased area, and jump to step A10 when an error occurs in the blank check or data verification, and if no error occurs, calculate and obtain the accumulated erasure time in the cycle operation of the lightly erased area;

[0101] A4, perform 10 cycle operations on the medium erase area, and jump to step A10 when there is an error in the blank check or data verification. If there is no error, calculate and obtain the accumulated erase time in the cycle operation of the medium erase area;

[0102] A5. Perform 100 cycle operations on the heavily erased area. If an error occurs in the blank check or data verification, jump to step A10. If no error occurs, calculate and obtain the accumulated erase time in the cycle operation of the heavily erased area.

[0103] A6. Determine whether the number of loops i is less than 1000. If yes, set i=i+1 and return to A3. Otherwise, execute A7.

[0104] A7, respectively read and output the first threshold voltage when all data in the heavily erased area, the medium erased area, the lightly erased area and the non-erased area are read as 0;

[0105] A8, respectively read and output the second threshold voltage when all data in the heavily erased area, the medium erased area, the lightly erased area and the non-erased area are read as 1;

[0106] A9. Obtain and output the accumulated erasure time of the heavy erasure area, the medium erasure area, and the light erasure area respectively, and end the test.

[0107] A10, read the threshold voltage of the erroneous storage unit and print the error information, the error information includes the cycle number, address and data change of the erroneous storage unit, and return to A9.

[0108] In summary, the embodiments of the present application provide a reliability testing method, device, electronic device and storage medium for a flash memory chip, wherein the method divides the storage area of ​​the flash memory chip into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area, and performs cycle operations of different degrees on the lightly erased area, the medium erased area and the heavily erased area to simulate the characteristics of different degrees of operation in different areas during actual use of the chip, so that the erasure time finally obtained for identifying the durability and data retention capability of the flash memory chip can make the test effect better and more accurately reflect the reliability of the flash memory chip.

[0109] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0110] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0111] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0112] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0113] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A reliability testing method for a flash memory chip, for testing the flash memory chip to obtain data that can be used to identify the durability and data retention capability of the flash memory chip, characterized in that: The method comprises the following steps: The flash memory chip storage area is divided into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division unit; Repeat and sequentially perform a cycle operation on the lightly erased area, n*a cycle operations on the medium erased area, and m*a cycle operations on the heavily erased area, until the heavily erased area completes a preset number of cycle operations, where a, n, and m are all positive integers, and m>n; Get the erasure time of the heavy erase area in the cycle operation.

2. A reliability testing method for a flash memory chip according to claim 1, characterized in that: The erasing time is a first total erasing time accumulated when the heavy erasing area completes the preset number of cycle operations, or includes a second total erasing time accumulated when the heavy erasing area completes a preset interval number of cycle operations, or includes a maximum erasing time, a minimum erasing time and an intermediate erasing time when the heavy erasing area completes the preset interval number of cycle operations.

3. A reliability testing method for a flash memory chip according to claim 1, characterized in that: The step of dividing the flash memory chip storage area into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division unit comprises the following sub-steps: Dividing the flash memory chip storage area into a plurality of test groups by taking sectors or blocks as the minimum division units; Each of the test groups is divided into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area based on the minimum division unit.

4. A reliability testing method for a flash memory chip according to claim 3, characterized in that: In the same test group, the heavily erased area, the medium erased area, the lightly erased area and the non-erased area are arranged adjacent to each other in sequence.

5. The reliability testing method of a flash memory chip according to claim 1, characterized in that: The method further comprises the following steps: The threshold voltages of the heavily erased area, the moderately erased area, the lightly erased area, and the non-erased area are respectively obtained.

6. The reliability testing method of a flash memory chip according to claim 1, characterized in that: The method further comprises the following steps: Obtaining the erasure time of the medium erasure area and / or the light erasure area in the cycle operation.

7. A flash memory chip reliability testing method according to claim 1, characterized in that: The number of the minimum division units occupied by the lightly erased area is greater than the number of the minimum division units occupied by the medium erased area, and the number of the minimum division units occupied by the medium erased area is greater than the number of the minimum division units occupied by the heavily erased area.

8. A reliability testing device for a flash memory chip, used for testing a flash memory chip to obtain data that can be used to identify the durability and data retention capability of the flash memory chip, characterized in that: The device comprises: A partition module is used to divide the flash memory chip storage area into a lightly erased area, a medium erased area, a heavily erased area and a non-erased area with sectors or blocks as the minimum division unit; an operation module, used to repeatedly and sequentially perform a cycle operation on the lightly erased area, n*a cycle operations on the medium erased area, and m*a cycle operations on the heavily erased area, until the heavily erased area completes a preset number of cycle operations, wherein a, n and m are all positive integers, and m>n; The acquisition module is used to obtain the erasure time of the heavy erase area in the cycle operation.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the steps in the method according to any one of claims 1 to 7 are executed.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are executed.

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