Semiconductor device and method of forming the same and method of adjusting wafer bow

Abstract

The application provides a semiconductor device and a method for forming the same, and a method for adjusting wafer warpage. The method for adjusting wafer warpage comprises: forming a stress layer and a light-absorbing layer in contact with each other on one side of a wafer; dividing the wafer into at least one wafer part and a remaining wafer part according to warpage of the wafer in different directions, wherein warpage of the at least one wafer part is greater than that of the remaining wafer part; and irradiating a laser beam to a region of the light-absorbing layer corresponding to the at least one wafer part to reduce a difference in warpage between the at least one wafer part and the remaining wafer part.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor. Specifically, the present application relates to a semiconductor device and a method for forming the same, and a method for adjusting wafer warpage. BACKGROUND

[0002] In the process of forming a semiconductor structure on a wafer, the wafer may be warped in different directions to different degrees due to lattice mismatch, thermal mismatch, etc. between thin films and the wafer and between thin films. If the warpage of the wafer is too large, the wafer cannot be flattened and thus cannot be put into a machine. In addition, if the warpage of the wafer in different directions is too different, it will affect the process of bonding the semiconductor structure formed thereon, which requires a high degree of flatness of the wafer.

[0003] It should be understood that the background section is intended to provide useful background information for understanding the technology, however, the content of this section does not necessarily constitute prior art that is already known or is suggested in the prior art to a person skilled in the art. SUMMARY

[0004] One aspect of the present application provides a method for forming a semiconductor device, the semiconductor device comprising a wafer, wherein the warpage of at least a portion of the wafer is greater than that of the remaining portion of the wafer, the method comprising: forming a stress layer and a light-absorbing layer in contact with each other on one side of the wafer; and irradiating a laser beam to a region of the light-absorbing layer corresponding to the at least a portion of the wafer to reduce the difference in warpage between the at least a portion and the remaining portion of the wafer.

[0005] In one embodiment of the present application, the light-absorbing layer has a light absorption rate greater than that of the stress layer.

[0006] In one embodiment of the present application, the light-absorbing layer has a light absorption rate of 0.5-8, and the stress layer has a light absorption rate less than 0.5.

[0007] In one embodiment of the present application, the light-absorbing layer has an absorption coefficient greater than that of the stress layer.

[0008] In one embodiment of the present application, the light-absorbing layer has an absorption coefficient of 0.01 nm-1-1 nm-1, and the stress layer has an absorption coefficient of 1x10-4 nm-1-1x10-2 nm-1. -1 -10 -3 -1

[0009] In one embodiment of the present application, the stress layer comprises at least one of silicon nitride and amorphous aluminum oxide, and the light-absorbing layer comprises at least one of tungsten and titanium nitride.​​​​

[0010] In one embodiment of the present application, the method further comprises forming a bonding layer in contact with the stress layer or the light-absorbing layer on one side of the wafer.

[0011] In one embodiment of the present application, the method further comprises forming a first semiconductor structure on another side of the wafer opposite to the one side; and bonding a second semiconductor structure on the first semiconductor structure.

[0012] Another aspect of the present application provides a method for adjusting warpage of a wafer, comprising: forming a stress layer and a light-absorbing layer in contact with each other on one side of the wafer; dividing the wafer into at least one wafer portion and a remaining wafer portion according to warpage of the wafer in different directions, wherein warpage of the at least one wafer portion is greater than warpage of the remaining wafer portion; and irradiating a laser beam to a region of the light-absorbing layer corresponding to the at least one wafer portion to reduce a difference in warpage between the at least one wafer portion and the remaining wafer portion.

[0013] In one embodiment of the present application, the light-absorbing layer has a light-absorbing rate greater than that of the stress layer.

[0014] In one embodiment of the present application, the light-absorbing layer has a light-absorbing coefficient greater than that of the stress layer.

[0015] In one embodiment of the present application, the stress layer comprises at least one of silicon nitride and amorphous aluminum oxide, and the light-absorbing layer comprises at least one of tungsten and titanium nitride.

[0016] Still another aspect of the present application provides a semiconductor device, comprising: a wafer; at least one stress layer on one side of the wafer, at least one stress portion of the stress layer having a stress different from that of a remaining stress portion of the stress layer; and a light-absorbing layer on the one side of the wafer and in contact with the stress layer.

[0017] In one embodiment of the present application, the semiconductor device comprises at least two stress layers, wherein the light-absorbing layer is located between adjacent stress layers.

[0018] In one embodiment of the present application, the at least one stress portion comprises a crystalline portion, and the remaining stress portion comprises an amorphous portion.

[0019] In one embodiment of the present application, the at least one stress portion comprises crystalline aluminum oxide, and the remaining stress portion comprises amorphous aluminum oxide.

[0020] In one embodiment of the present application, the light-absorbing layer includes at least one of tungsten or titanium nitride.

[0021] In one embodiment of the present application, the semiconductor device further includes a bonding layer located on one side of the wafer and in contact with the stress layer or the light-absorbing layer.

[0022] In one embodiment of the present application, the semiconductor device includes a first semiconductor structure located on another side of the wafer opposite to the one side, and a second semiconductor structure bonded to the first semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0023] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings. In the drawings,

[0024] Figure 1 and Figure 2 A schematic diagram of a wafer in the related art showing a warped shape due to uneven stress distribution.

[0025] Figure 3 A schematic diagram of a wafer in the related art showing a warped shape due to uneven stress distribution.

[0026] Figure 4 A schematic diagram of a wafer in the related art showing a warped shape due to uneven stress distribution.

[0027] Figures 5-9 A schematic diagram of a wafer in the related art showing a warped shape due to uneven stress distribution.

[0028] Figure 10 A schematic diagram of a wafer in the related art showing a warped shape due to uneven stress distribution.

[0029] Figure 11 A schematic diagram of a wafer in the related art showing a warped shape due to uneven stress distribution. DETAILED DESCRIPTION

[0030] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the detailed description is merely exemplary of the application and is not intended to limit the scope of the application solely to these exemplary embodiments. Throughout the specification, like reference numerals will be understood to refer to like parts throughout the specification and the figures.

[0031] Note that reference to "one implementation," "an implementation," "one example implementation," "some implementations," etc., in the specification indicates that the feature, structure, or characteristic being described can be included in one or more implementations of the application. The appearances of the phrase "in one implementation" in various places in the specification are generally not necessarily referring to the same implementation.

[0032] Generally, terminology can be understood at least in part from usage in context. For example, terms, such as "a" or "an," can be understood to convey a singular usage or to convey a plural usage, at least in part depending on context. In addition, terms, such as "another" or "one or more," can be understood to convey a singular usage or to convey a plural usage, at least in part depending on context.

[0033] It should be readily understood that the terms "on," "above," and "upper" are used most broadly here to include not only the meanings of "directly on" or "directly above" but also the meaning of "on" or "above," having intervening features or layers therebetween. Similarly, the terms "under," "beneath," "below," and "lower" are used most broadly here to include not only the meanings of "directly under" or "directly below" but also the meaning of "under" or "below," having intervening features or layers therebetween.

[0034] In addition, spatially relative terms, such as "under," "below," "lower," "over," "upper" and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures.

[0035] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. In addition, a layer can be a region of a continuous structure that is uniform or non-uniform, having a thickness that is less than the thickness of the continuous structure. A layer can include a single sublayer or multiple sublayers.

[0036] In the drawings, which are not necessarily drawn to scale, the thicknesses of the layers, regions, or sections can be exaggerated for the purpose of illustration and description. The terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, unless in particular contexts otherwise indicated, and are intended to account for the tolerance inh

[0037] It should also be understood that the words "comprise," "comprising," "include," "including," and / or "has," "having," when used in this specification, specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or groups thereof. Furthermore, when describing the application, the use of "or" means "and / or" unless clearly indicated otherwise. Moreover, the words "exemplary" and / or "example" are used herein to mean "an example of" or "an example," unless explicitly stated otherwise.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0039] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other, without conflict. In addition, unless specifically limited or clearly contradicted by context, the specific steps of the methods described in the present application need not be limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0040] In the manufacturing process of semiconductor devices (e.g., memory), the formation of each film layer on a wafer and the processing of each film layer are mostly accompanied by a heat release process. For memory, with the requirements of smaller memory size and larger memory capacity, 3D NAND memory is increasingly concerned. In the 3D NAND manufacturing process, for example, in the heat release process of depositing different film layers on a wafer (also referred to as "semiconductor substrate"), etching different film layers, and annealing, etc., different film layers have elongation or shrinkage characteristics due to different thermal expansion coefficients, so in the same heat release process, some film layers exhibit tensile stress and some film layers exhibit compressive stress, which eventually leads to different degrees of warping of the wafer. When the stresses in each direction of the wafer are matched, the wafer will bend towards the same direction (towards the front surface of the wafer or the back surface of the wafer), as shown in Figure 1 In some examples, as shown in

[0041] In some examples, as shown in Figure 2As shown, the wafer 200 has different warping directions and warping degrees, for example, in the X radial direction, the wafer 200 is curved towards its front surface, in the Y radial direction perpendicular to the X direction, the wafer 200 is curved towards its back surface, and the wafer 200 has different warping degrees in the X and Y directions, and presents a saddle shape.

[0042] Due to the limitation of the semiconductor processing machine, if the warping degree of the wafer 100 is too large or the wafer 200 has a large difference in warping degree in different directions, the wafer may not be able to be processed on the same machine, increasing the cost of device manufacturing.

[0043] In some examples of improving the warping degree of the wafer, as shown in Figure 3 As shown, a stress film 520 can be deposited on at least one of the opposite surfaces of the wafer 500 to balance the stress of the wafer 500, thereby reducing the warping degree of the wafer 500. Optionally, the stress film 520 can also be annealed to further balance the stress distribution of the wafer 500. However, since the formation of the stress film 520 is a uniform deposition process, the stress film 520 changes the stress of the wafer 500 in all directions uniformly. When the wafer 500 has a saddle shape as shown, even if the stress film 520 is deposited on one side of the wafer 500 and the stress film 520 is annealed, it is difficult to adjust the stress of the wafer 500 in different directions, which will affect the process of the semiconductor structure (for example, the array structure 440 as shown) formed on the wafer 500, which has a high requirement for the flatness of the wafer 500. Figure 2 As shown, a stress film 520 can be deposited on at least one of the opposite surfaces of the wafer 500 to balance the stress of the wafer 500, thereby reducing the warping degree of the wafer 500. Optionally, the stress film 520 can also be annealed to further balance the stress distribution of the wafer 500. However, since the formation of the stress film 520 is a uniform deposition process, the stress film 520 changes the stress of the wafer 500 in all directions uniformly. When the wafer 500 has a saddle shape as shown, even if the stress film 520 is deposited on one side of the wafer 500 and the stress film 520 is annealed, it is difficult to adjust the stress of the wafer 500 in different directions, which will affect the process of the semiconductor structure (for example, the array structure 440 as shown) formed on the wafer 500, which has a high requirement for the flatness of the wafer 500. Figure 11 As shown, a stress film 520 can be deposited on at least one of the opposite surfaces of the wafer 500 to balance the stress of the wafer 500, thereby reducing the warping degree of the wafer 500. Optionally, the stress film 520 can also be annealed to further balance the stress distribution of the wafer 500. However, since the formation of the stress film 520 is a uniform deposition process, the stress film 520 changes the stress of the wafer 500 in all directions uniformly. When the wafer 500 has a saddle shape as shown, even if the stress film 520 is deposited on one side of the wafer 500 and the stress film 520 is annealed, it is difficult to adjust the stress of the wafer 500 in different directions, which will affect the process of the semiconductor structure (for example, the array structure 440 as shown) formed on the wafer 500, which has a high requirement for the flatness of the wafer 500.

[0044] Some embodiments of the present application provide a method for improving the warping degree of a wafer to address at least one of the above problems, as shown in Figure 4 As shown, the method 300 for improving the warping degree of the wafer is a flowchart.

[0045] As shown, the method 300 includes operation S310, in which a stress layer and a light-absorbing layer can be formed on one side of the wafer in contact with each other. As shown in Figure 4 As shown, the method 300 includes operation S310, in which a stress layer and a light-absorbing layer can be formed on one side of the wafer in contact with each other. As shown in Figure 5 As shown, in some embodiments, a stress layer 420 and a light-absorbing layer 430 can be formed on one side of the wafer 400 in contact with each other.

[0046] Optionally, the wafer 400 can be a semiconductor substrate to provide a semiconductor structure (for example, the array structure 440 as shown) formed thereon. Figure 11The array structure 440) is shown to be structurally supported. In some examples, the semiconductor substrate 400 described above can include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, a III-V compound semiconductor, or any combination thereof.

[0047] Optionally, a semiconductor structure, for example, including an array structure of memory (e.g., a 3D NAND) can be formed on the surface of the opposite side of the wafer 400 prior to forming the stress layer 420 and the light-absorbing layer 430. Figure 11 The array structure 440) and CMOS device structure are shown to include, for example, a 3D NAND. Optionally, the semiconductor structure described above can not be formed on the surface of the opposite side of the wafer 400 prior to forming the stress layer 420 and the light-absorbing layer 430, which is not limited in the present application.

[0048] In some examples, at least two stress layers 420 and one light-absorbing layer 430 located between adjacent stress layers 420 can be formed on the surface of one side of the wafer 400 by, for example, a suitable thin film deposition process such as CVD, PVD, ALD, etc. Figure 6 In other examples as shown, one stress layer 420 can be deposited on one side of the wafer 400 first, and then one light-absorbing layer 430 in contact with the stress layer 420 can be deposited on the stress layer 420. Figure 7 In examples as shown, one light-absorbing layer 430 can be deposited on one side of the wafer 400 first, and then one stress layer 420 in contact with the light-absorbing layer 430 can be deposited on the light-absorbing layer 430. The present application does not limit the order and number of layers of the stress layer 420 and the light-absorbing layer 430 described above.

[0049] In some examples, the stress layer 420 includes, for example, at least one heat-sensitive material such as silicon nitride and amorphous aluminum oxide, which can shrink after being heated, so that the warpage of the wafer 400 can be improved by changing the stress of the stress layer 420.

[0050] Optionally, the light absorption rate K1 of the stress layer 420 can be less than 0.5. Optionally, the light absorption coefficient a1 of the stress layer 420 is, for example, 1 x 10 -10 nm -1 ~ 1 x 10 -3 nm -1 . Optionally, the light absorption coefficient a1 of the stress layer 420 is, for example, 1 x 10 -8 nm -1 ~ 1 x 10 - 4 nm -1 .

[0051] In some examples, the light-absorbing layer 430 may, for example, include at least one light-absorbing sensitive material of titanium nitride and tungsten. Optionally, the light-absorbing rate K2 of the light-absorbing layer 430 is greater than the light-absorbing rate K1 of the stress layer 420, and the light-absorbing rate K2 of the light-absorbing layer 430 is, for example, 0.5-8.

[0052] Optionally, the light-absorbing coefficient a2 of the light-absorbing layer 430 is greater than the light-absorbing coefficient a1 of the stress layer 420. Optionally, the light-absorbing coefficient a2 of the light-absorbing layer 430 is, for example, 0.01 nm -1 -1 nm -1 . Optionally, the light-absorbing coefficient a of the light-absorbing layer 430 is, for example, 0.02 nm -1 -0.3 nm -1 .

[0053] In comparison, when light with certain energy and intensity respectively irradiates the stress layer 420 and the light-absorbing layer 430, the light-absorbing layer 430 has better light-absorbing capability than the stress layer 420.

[0054] In some examples, the thickness of the light-absorbing layer 430 ranges from 10 nm to 50 nm. Optionally, the thickness of the light-absorbing layer 430 ranges from 20 nm to 40 nm.

[0055] In some examples in which the wafer 400 includes silicon, due to the poor bonding force of the stress layer 420 (for example, silicon nitride) with silicon, a bonding layer 410 with relatively good bonding force with the wafer 400 may, for example, be deposited on the surface of one side of the wafer 400 by a suitable thin film deposition process such as CVD, PVD, ALD, etc. before forming the stress layer 420, and the material of the bonding layer 410 may, for example, include silicon oxide.

[0056] Back to Figure 4 The method 300 further includes: S320, dividing the wafer into at least one wafer part and the remaining wafer part according to the warping degrees of the wafer in different directions, wherein the warping degree of the at least one wafer part is greater than the warping degree of the remaining wafer part.

[0057] In some embodiments, the warping degrees of the wafer 400 in different directions may, for example, be measured by a flatness tester by measuring the heights of multiple points of the wafer 400 in different directions, and in some examples, the warping degrees of the wafer 400 in two directions perpendicular to each other along the radial direction of the wafer 400 (for example, Figure 1 and Figure 2 the X and Y directions shown) may, for example, be measured. Through the warping degree measurement, the warping direction of the wafer 400 and the difference in warping degrees in different directions may, for example, be determined.

[0058] Referring to Figure 7 and Figure 8 wherein, Figure 7 is Figure 8A schematic cross-sectional view along line AA. In some examples, wafer 400 can be divided into at least one wafer portion (e.g., a first wafer portion 401 and a second wafer portion 402) and the remaining wafer portion 403 based on the warpage in different directions (e.g., perpendicular radials X and Y, respectively). In some examples, the warpage of the first wafer portion 401 and the second wafer portion 402 may be greater than that of the remaining wafer portion 403. Optionally, wafer 400 may warp in a direction away from stress layer 420, and the warpage of wafer 400 along the Y direction may be greater than that along the X direction, as measured by a flattening instrument.

[0059] In some examples, the cross-sectional profiles of the first wafer portion 401 and the second wafer portion 402 along the XY direction can be regular shapes such as square or circle. In other examples, the cross-sectional profiles of the first wafer portion 401 and the second wafer portion 402 along the XY direction can also be irregular shapes.

[0060] like Figure 7 As shown, in some examples, the stress layer 420 can be divided into a first stress portion 421, a second stress portion 422, and remaining stress portions 423 corresponding to the first wafer portion 401, the second wafer portion 402, and the remaining wafer portions 403. Optionally, the bonding layer 410 can be correspondingly divided into a first bonding portion 411, a second bonding portion 412, and remaining bonding portions 413.

[0061] In other examples, the light-absorbing layer 430 can be divided into a first light-absorbing region 431, a second light-absorbing region 432, and other light-absorbing regions 433 that are in contact with the first stress portion 421, the second stress portion 422, and the remaining stress portions 423 respectively.

[0062] Refer again Figure 4 Method 300 includes operation S330, wherein a laser beam can be irradiated onto a region of the light-absorbing layer corresponding to at least one wafer portion to reduce the difference in warpage between at least one wafer portion and the remaining wafer portions.

[0063] Continue to refer to Figure 7 In some examples, a laser beam can be used to irradiate the first light-absorbing region 431 and the second light-absorbing region 432 of the light-absorbing layer 430, corresponding to the first wafer portion 401 and the second wafer portion 402, using a laser pulse method. Optionally, the laser beam spot shape can be a regular shape such as square or circular. Optionally, the laser beam spot size can be at the millimeter or micrometer level. Optionally, the laser beam energy can be 1J to 10J. Optionally, the pulse duration can be 100ns to 500ns. Under the above laser pulse conditions, the depth to which the laser beam can irradiate can be at least approximately the same as the thickness of the light-absorbing layer 430.

[0064] In other examples, a mask (not shown) having openings corresponding to the first light-absorbing region 431 and the second light-absorbing region 432 can be employed to achieve the patterned laser beam irradiation. When the first light-absorbing region 431 and the second light-absorbing region 432 are irradiated by the laser beam, the mask can be used as a shield, and the first light-absorbing region 431 and the second light-absorbing region 432 can be irradiated by the laser beam through the openings in the mask, while the rest of the light-absorbing region 433 can not be irradiated by the laser beam.

[0065] Since the light-absorbing layer 430 is a light-absorbing sensitive material, after the first light-absorbing region 431 and the second light-absorbing region 432 receive the irradiation of the laser beam, the energy of the absorbed light is converted into internal molecular thermal motion, and then conducted to the corresponding first stress portion 421 and the second stress portion 422 in the form of heat. The first stress portion 421 and the second stress portion 422 shrink under the heat, and the shrunk first stress portion 421 and the second stress portion 422 have different stresses from the rest of the stress portion 423, so as to be able to compensate for the stresses of the first wafer portion 401 and the second wafer portion 402, reduce the warpage of the first wafer portion 401 and the second wafer portion 402, and thus reduce the difference in warpage between the first wafer portion 401 and the second wafer portion 402 and the rest of the wafer portion 403, so as to achieve the directional warpage adjustment.

[0066] In the example where the stress layer 420 includes silicon nitride, the silicon nitride contains a large number of Si-H bonds and N-H bonds, and the heat conducted through the first light-absorbing region 431 and the second light-absorbing region 432 causes the Si-H bonds and the N-H bonds in the first stress portion 421 and the second stress portion 422 to obtain the energy for bond breaking, and recombine in the form of more stable H-H bonds and Si-N bonds. The newly generated Si-N bonds can cause the first stress portion 421 and the second stress portion 422 to obtain a stronger tensile stress than the rest of the stress portion 423, so as to stretch the first wafer portion 401 and the second wafer portion 402 towards the direction close to the stress layer 420, and make them more flat.

[0067] In the example where the stress layer 420 includes amorphous aluminum oxide, the heat conducted through the first light-absorbing region 431 and the second light-absorbing region 432 causes the amorphous aluminum oxide included in the first stress portion 421 and the second stress portion 422 to crystallize into crystalline aluminum oxide. The first stress portion 421 and the second stress portion 422 are, for example, crystallized into Figure 9 the first crystalline portion 421' and the second crystalline portion 422' shown, and the rest of the stress portion 423 is, for example, an amorphous portion. Since the atoms or ions in the first crystalline portion 421' and the second crystalline portion 422' are arranged more regularly and closely, the first crystalline portion 421' and the second crystalline portion 422' shrink to generate a stronger tensile stress than the rest of the stress portion 423.

[0068] In some embodiments of this application, although the stress of the stress layer 420 is prone to change after heating, the light absorption of the stress layer 420 is low. In the example where the stress layer 420 includes silicon nitride, silicon nitride is a light-transmitting material with a light absorption rate close to 0 and an absorption coefficient of approximately 7 × 10⁻⁶. -7 nm -1 In the example where stress layer 420 comprises amorphous alumina, the amorphous alumina is a light-transmitting material with an absorbance of approximately 0.02 and an absorption coefficient of approximately 4 × 10⁻⁶. -4 nm -1 Therefore, in examples where the stress layer 420 comprises at least one of silicon nitride and amorphous aluminum oxide, the stress layer 420 absorbs almost no light energy or intensity. Directional warpage adjustment using direct laser beam irradiation of the stress layer 420 will be limited.

[0069] Some embodiments of this application form a light-absorbing layer 430 with strong light-absorbing capacity that is in contact with the stress layer 420. This allows the light-absorbing regions (e.g., first light-absorbing region 431 and second light-absorbing region 432) of the light-absorbing layer 430 corresponding to the high warp portions (e.g., the first wafer portion 401 and the second wafer portion 402) of the wafer 400 to be irradiated by a laser beam. Through photothermal conversion of the light-absorbing layer 430, the stress portions (e.g., the first stress portion 421 and the second stress portion 422) corresponding to the stress layer 420 receive energy conducted in the form of heat, thereby changing the stress, for example, generating stronger tensile stress, thereby achieving directional warp adjustment.

[0070] Other embodiments of this application also provide a method for forming a semiconductor device, such as... Figure 10 The diagram shows a flow chart of a semiconductor device formation method 600. Method 600 includes: S610, forming a first semiconductor structure on a side of a wafer opposite to one of its components; S620, forming a stress layer and a light-absorbing layer in contact on one side of the wafer; S630, irradiating a laser beam onto a region of the light-absorbing layer corresponding to at least a portion of the wafer to reduce the difference in warpage between the at least a portion and the remaining wafer portions; and S640, bonding a second semiconductor structure onto the first semiconductor structure.

[0071] It is understood that the structure and construction of the wafer 400, stress layer 420, and light-absorbing layer 430, as well as the laser beam irradiation process, described in the above description of method 300, can be fully or partially applied to the wafer described in method 600, and therefore related or similar content will not be repeated.

[0072] In some examples, the first semiconductor structure includes, for example, an array structure of memory, optionally, the first semiconductor structure can further include a CMOS device structure, the memory including, for example, 3D NAND. As shown in Figure 11 The array structure 440 can include a first region 441 and a second region 442, for example, as shown in FIG. 4B, where the first region 441 can be provided with the through-via contacts 425 for electrically leading out the array structure 440 and its bonded second semiconductor structure 450 (FIG. 4A) to connect with the backside interconnect structure for transmission of electrical signals. Figure 11

[0073] In some examples, the array structure 440 includes a stack structure (not shown) formed by alternatingly arranging dielectric layers 448 and conductor layers 446 on the wafer 400, where a dielectric layer 448 and an adjacent conductor layer 446 form a dielectric / conductor pair. The number of pairs can be selected according to various application scenarios. For example, the number of pairs can be 32, 64, 96, 128, 160, 192, 224, 256, or more.

[0074] In some embodiments, the conductor layers 446 can include, for example, a conductor material of W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicide (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. The dielectric layers 448 can include, for example, an insulating material of silicon oxide, silicon nitride, silicon oxynitride, or the like. In one example, the conductor layers 446 can be tungsten, and the dielectric layers 448 can be silicon oxide.

[0075] In some examples, the second region 442 can include a core region 444 and a step region 443 located at least one side of the core region, where the step region 443 can form a step structure. The first region 441 can be located at a side of the step region 443 away from the core region 444. In some examples, the array structure 440 further includes an insulating planar layer 426 covering the step region 443 and filling the first region 441 for supporting the through-via contacts 425.

[0076] In some embodiments, the array structure 440 further includes a channel structure 424 extending through the stack structure and into the wafer 400. The channel structure 424 can include, for example, a blocking layer (not shown), a charge storage layer (not shown), a tunneling layer, and a channel layer (not shown) arranged in sequence from outside to inside. The blocking layer can include, for example, a material of silicon oxide, the charge storage layer can include, for example, a material of silicon nitride, the tunneling layer can include, for example, a material of silicon oxide, and the channel layer can include, for example, a material of polysilicon.

[0077] ​In some embodiments, the stepped region 443 of the array structure 440 can be configured to provide word line contacts 427 in contact with each of the conductor layers 446 for electrical connection to the second semiconductor structure 450. In some embodiments, the array structure 440 further includes line gap structures 428 extending through the stack and into the wafer 400, which can include, for example, an insulating material, for electrically isolating adjacent conductor layers 446.

[0078] In some embodiments, the array structure 440 further includes a first interconnect structure 445 disposed on a side of the wafer 400 opposite the array structure 440.

[0079] Returning to Figure 10 For operation S640, with an example of forming a second semiconductor structure on the array structure 440, reference is made to Figure 11 The second semiconductor structure 450 can be, for example, a peripheral circuit structure. In some embodiments, the peripheral circuit structure 450 is configured to control and sense the array structure 440. The peripheral circuit structure 450 can include CMOS transistors (not shown).

[0080] In some embodiments, the peripheral circuit structure can further include a second interconnect structure 455. Optionally, the second interconnect structure 455 is bonded to the first interconnect structure 445 when the array structure 440 and the peripheral circuit structure 450 are hybrid bonded face-to-face. Since the stress layer 420 and the light absorbing layer 430 are formed on a side of the wafer 400, the warpage of the wafer 400 can be improved and the difference in warpage in different directions can be reduced, so that the flatness of the wafer 400 can meet the bonding process requirements when the array structure 440 and the peripheral circuit structure 450 are bonded.

[0081] In some embodiments, the wafer 400 can be removed at an appropriate stage after the array structure 440 and the peripheral circuit structure 450 are bonded, and then a semiconductor layer (not shown) can be formed on the surface exposed by the removal of the wafer 400, which can be in contact with the channel layer of the channel structure 424.

[0082] Some embodiments of the present disclosure further provide a semiconductor device, and since the content (including structures, configurations, and materials) involved in the above-described methods 300 and 600 can be fully or partially applicable to the semiconductor device described herein, the related or similar content will not be repeated.

[0083] Although the semiconductor device and its exemplary manufacturing method and the semiconductor structure in some stages of forming a three-dimensional memory are described herein, it can be understood that one or more features can be omitted, replaced, or added from the three-dimensional memory and the semiconductor structure. In addition, the example layers and their materials are merely exemplary.

[0084] The specific embodiments described above are further explained in connection with the purposes, technical solutions and beneficial effects of the present application. It should be understood that the above is only a specific embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for forming a semiconductor device, said semiconductor device comprising a wafer, wherein, The warpage of at least a portion of the wafer is greater than the warpage of the remaining wafer portions, characterized in that the method comprises: A stress layer and a light-absorbing layer are formed in contact with each other on one side of the wafer, the light-absorbing layer being located between the stress layers of adjacent layers; and A laser beam is irradiated onto the region of the light-absorbing layer corresponding to at least a portion of the wafer, causing at least a portion of the stress layer to exert a stronger tensile stress on the wafer than the remaining stress portions, thereby reducing the difference in warpage in different directions between the at least a portion and the remaining wafer portions.

2. The method according to claim 1, wherein, The light absorption rate of the light-absorbing layer is greater than that of the stress layer.

3. The semiconductor device according to claim 2, wherein, The light absorption rate of the light-absorbing layer is 0.5 to 8, and the light absorption rate of the stress layer is less than 0.

5.

4. The method according to claim 1, wherein, The light absorption coefficient of the light-absorbing layer is greater than that of the stress layer.

5. The method according to claim 4, wherein, The light absorption coefficient of the light-absorbing layer is 0.01 nm. -1 ~1nm -1 The light absorption coefficient of the stress layer is 1×10⁻⁶. -10 nm -1 ~1×10 -3 nm -1 .

6. The method according to claim 1, wherein, The stress layer comprises at least one of silicon nitride and amorphous aluminum oxide, and the light-absorbing layer comprises at least one of tungsten and titanium nitride.

7. The method according to claim 1, further comprising: A bonding layer is formed on one side of the wafer, which is in contact with the stress layer or the light-absorbing layer.

8. The method according to claim 1, further comprising: A first semiconductor structure is formed on the opposite side of the wafer to the first side; as well as A second semiconductor structure is bonded to the first semiconductor structure.

9. A method for adjusting wafer warpage, comprising: A stress layer and a light-absorbing layer are formed in contact with each other on one side of the wafer, wherein the light-absorbing layer is located between the stress layers of adjacent layers; Based on the warpage of the wafer in different directions, the wafer is divided into at least one wafer portion and the remaining wafer portions, wherein the warpage of the at least one wafer portion is greater than the warpage of the remaining wafer portions; as well as A laser beam is irradiated onto the region of the light-absorbing layer corresponding to the at least one wafer portion, causing at least a portion of the stress portion of the stress layer to exert a stronger tensile stress on the wafer than the remaining stress portions, thereby reducing the difference in warpage between the at least one wafer portion and the remaining wafer portions in different directions.

10. The method according to claim 9, wherein, The light absorption rate of the light-absorbing layer is greater than that of the stress layer.

11. The method according to claim 9, wherein, The light absorption coefficient of the light-absorbing layer is greater than that of the stress layer.

12. The method according to claim 9, wherein, The stress layer comprises at least one of silicon nitride and amorphous aluminum oxide, and the light-absorbing layer comprises at least one of tungsten and titanium nitride.

13. Semiconductor devices, including: wafers; At least two stress layers are located on one side of the wafer, and the stress of at least one stress portion and the remaining stress portions of the stress layers have stress differences in different directions; as well as A light-absorbing layer is located on one side of the wafer and in contact with the stress layer, the light-absorbing layer being located between the stress layers of adjacent layers.

14. The semiconductor device according to claim 13, wherein, The at least one stress portion includes a crystalline portion, and the remaining stress portions include amorphous portions.

15. The semiconductor device according to claim 13, wherein, The at least one stress portion comprises crystalline alumina, and the remaining stress portions comprise amorphous alumina.

16. The semiconductor device according to claim 13, wherein, The light-absorbing layer includes at least one of tungsten or titanium nitride.

17. The semiconductor device of claim 13, further comprising: A bonding layer is located on one side of the wafer and is in contact with the stress layer or the light-absorbing layer.

18. The semiconductor device of claim 13, further comprising: A first semiconductor structure is located on the opposite side of the wafer from the first side; as well as The second semiconductor structure is bonded to the first semiconductor structure.

Images