Three-dimensional memory, method of making three-dimensional memory, and memory system

Abstract

The application relates to a three-dimensional memory, a manufacturing method of the three-dimensional memory and a storage system, which comprises the following steps: forming a substrate; forming a first stack structure with a first channel hole on the substrate, the first stack structure comprising first gate sacrificial layers and first insulating layers which are alternately and multilayerly arranged in a direction perpendicular to the substrate, and the first stack structure being provided with the first gate sacrificial layer at an end far from the substrate; forming a second stack structure with a second channel hole on the first stack structure, the first channel hole being communicated with the second channel hole; and forming a channel structure in the first channel hole and the second channel hole, so that the problem of electric leakage between gate layers in the three-dimensional memory can be improved, and the yield and reliability of the three-dimensional memory are improved.

Description

[Technical Field]

[0001] This invention relates to the field of memory technology, specifically to a three-dimensional memory, a method for manufacturing a three-dimensional memory, and a storage system. [Background Technology]

[0002] With the development of technology, the semiconductor industry is constantly seeking new production methods to enable each memory die in a memory device to have a greater number of memory cells. Among them, 3D NAND (three-dimensional memory) has become a cutting-edge and highly promising three-dimensional memory technology due to its advantages such as high storage density and low cost.

[0003] However, how to improve the leakage current between gate layers in three-dimensional memory is a rather troubling problem in current memory technology and urgently needs to be solved. [Summary of the Invention]

[0004] This invention provides a three-dimensional memory, a method for manufacturing a three-dimensional memory, and a storage system to improve the leakage problem between gate layers in a three-dimensional memory, thereby improving the yield and reliability of the three-dimensional memory.

[0005] To address the aforementioned problems, the present invention provides a method for fabricating a three-dimensional memory. The method includes: forming a substrate; forming a first stack structure on the substrate through which a first channel hole is formed, the first stack structure including multiple alternating layers of a first gate sacrificial layer and a first insulating layer disposed in a direction perpendicular to the substrate, wherein the end of the first stack structure furthest from the substrate is the first gate sacrificial layer; forming a second stack structure on the first stack structure through which a second channel hole is formed, the second channel hole communicating with the first channel hole; and forming a channel structure in the first and second channel holes.

[0006] Before forming the second stack structure with a through-hole on the first stack structure, the method further includes: forming a sacrificial material layer in the first channel hole; aligning the sacrificial material layer with the uppermost first gate sacrificial layer in the first stack structure; forming the second stack structure with a through-hole on the first stack structure, specifically including: forming the second stack structure on the aligned sacrificial material layer and the uppermost first gate sacrificial layer; forming a second channel hole through the second stack structure, the second channel hole exposing the sacrificial material layer; and removing the sacrificial material layer through the second channel hole.

[0007] The formation of a channel structure in the first and second channel holes specifically includes: forming a first nitride layer on the inner wall of the first and second channel holes; oxidizing the first nitride layer to obtain a first oxide layer; forming a second nitride layer on the side of the first oxide layer away from the inner wall; forming a second oxide layer on the side of the second nitride layer away from the first oxide layer; and forming a channel layer on the side of the second oxide layer away from the second nitride layer, to obtain a channel structure including a first oxide layer, a second nitride layer, a second oxide layer, and a channel layer.

[0008] In this structure, a corner is formed between the inner wall of the first channel hole and the second stack structure. After the first nitride layer is oxidized, a portion of the first nitride layer at the corner is left as a residue, and the remaining portion of the first nitride layer is oxidized to form a first oxide layer.

[0009] The residue is connected to the first gate sacrificial layer, and the upper surface of the residue is flush with the upper surface of the first gate sacrificial layer.

[0010] After forming a channel structure in the first and second channel holes, the method further includes: forming a gate line gap that penetrates the first and second stacked structures; and replacing the first gate sacrificial layer in the first stacked structure and the second gate sacrificial layer in the second stacked structure with the first gate layer and the second gate layer, respectively, through the gate line gap.

[0011] The method further includes, after forming a gate line gap that runs through the first stack structure and the second stack structure, replacing the residue with a redundant gate layer through the gate line gap. The redundant gate layer is connected to the first gate layer, and the upper surface of the redundant gate layer is flush with the upper surface of the first gate layer.

[0012] The material of the first nitride layer is the same as that of the first gate sacrificial layer.

[0013] To address the aforementioned problems, the present invention provides a three-dimensional memory comprising: a first stack structure; a second stack structure located on the first stack structure; and a channel structure penetrating the first and second stack structures; wherein the first stack structure includes multiple alternating layers of a first gate layer and a first insulating layer disposed in a direction away from the second stack structure, the sidewall of the channel structure has a stepped surface, the stepped surface is flush with the surface of the first stack structure that contacts the second stack structure, and the first stack structure contacts the second stack structure through the uppermost first gate layer.

[0014] The three-dimensional memory also includes a redundant gate layer, which is located between the channel structure and the uppermost first gate layer in the first stack structure.

[0015] The redundant gate layer is connected to the first gate layer, and the upper surface of the redundant gate layer is flush with the upper surface of the first gate layer.

[0016] The redundant gate layer is made of the same material as the first gate layer.

[0017] The channel structure includes a channel layer, a second oxide layer surrounding the channel layer, a second nitride layer surrounding the second oxide layer, and a first oxide layer surrounding the second nitride layer.

[0018] To address the aforementioned problems, the present invention provides a storage system comprising a controller and a three-dimensional memory as described above, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

[0019] The beneficial effects of the present invention are as follows: The method for fabricating a three-dimensional memory provided by the present invention forms a substrate and forms a first stack structure with a first channel hole through it on the substrate. The first stack structure includes a first gate sacrificial layer and a first insulating layer that are alternately stacked in a direction perpendicular to the substrate, and the end of the first stack structure away from the substrate is the first gate sacrificial layer. Then, a second stack structure with a second channel hole through it is formed on the first stack structure. The second channel hole is connected to the first channel hole. Then, a channel structure is formed in the first channel hole and the second channel hole. This avoids the problem that the raw material layer used to form the charge blocking layer in the channel structure has a large lateral thickness at the connection between the first stack structure and the second stack structure. After the charge blocking layer is formed, there will be residue at the connection between the first stack structure and the second stack structure. This will cause the residual raw material to be located in the insulating layer of the two stack structures. As a result, after the gate sacrificial layer in the two stack structures is replaced with the corresponding gate layer, the presence of the residual raw material in the insulating layer between adjacent gate layers or the presence of a conductive structure obtained after replacing the residual raw material with the gate material will lead to leakage between adjacent gate layers. This improves the yield and reliability of the three-dimensional memory. [Attached Image Description]

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the method for fabricating a three-dimensional memory provided in an embodiment of the present invention;

[0022] Figures 2a-2lThis is a cross-sectional structural schematic diagram corresponding to the manufacturing process of the three-dimensional memory provided in the embodiments of the present invention;

[0023] Figure 3 yes Figure 2i Enlarged view of the local structure located within the rectangular dashed frame R1 and Figure 2l Enlarged view of the local structure located within the rectangular dashed frame R3;

[0024] Figure 4 yes Figure 2k Enlarged view of the local structure located within the rectangular dashed frame R2;

[0025] Figure 5 These are schematic cross-sectional views of semiconductor structures obtained after forming a channel structure in the fabrication process of three-dimensional memory provided in some embodiments.

[0026] Figure 6 yes Figure 5 Enlarged view of the local structure located within the rectangular dashed frame R4;

[0027] Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming a channel structure in the fabrication process of a three-dimensional memory provided in other embodiments;

[0028] Figure 8 yes Figure 7 An enlarged view of the local structure located within the rectangular dashed frame R5.

Detailed Implementation Methods

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Furthermore, the directional terms used in this invention, such as [up], [down], [front], [back], [left], [right], [inside], [outside], and [side], are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding this invention, and not for limiting it. In the various figures, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the figures are not drawn to scale. Additionally, some well-known parts may not be shown in the figures.

[0031] This invention can be presented in various forms, some of which will be described below.

[0032] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention. The specific process of the method for fabricating the three-dimensional memory is as follows:

[0033] Step S11: Form the substrate.

[0034] Step S12: A first stack structure with a first channel hole through it is formed on the substrate. The first stack structure includes a first gate sacrificial layer and a first insulating layer that are alternately stacked in a direction perpendicular to the substrate, and the end of the first stack structure away from the substrate is the first gate sacrificial layer.

[0035] The cross-sectional structure diagram after step S12 is shown below. Figure 2b As shown.

[0036] The material of substrate 11 may include semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). In one embodiment, the substrate 11 may specifically be a substrate. Furthermore, in another embodiment, such as... Figure 2b As shown, the substrate 11 may further include a substrate 111 and a first oxide layer 112, a sacrificial layer 113, a second oxide layer 114 and a stop layer 115 sequentially formed on the substrate 111. The substrate 111, the first oxide layer 112, the sacrificial layer 113, the second oxide layer 114 and the stop layer 115 may be made of silicon, silicon oxide, polysilicon, silicon oxide and polysilicon, respectively.

[0037] Specifically, the first oxide layer 112 and the second oxide layer 114 can be used to improve the quality of epitaxial growth on the substrate 111 and the sacrificial layer 113, respectively. The sacrificial layer 113 can be used to protect the substrate 111 from damage during the process step of forming the channel via 13. The stop layer 115 can be used to stop the grinding process when removing the substrate 111 in a subsequent process step.

[0038] In one specific embodiment, step S12 may specifically include:

[0039] Step S 121: Form a first stack structure 12 on the substrate 11.

[0040] The cross-sectional structure diagram after step S121 is shown below. Figure 2a As shown.

[0041] The first stack structure 12 includes a first gate sacrificial layer 121 and a first insulating layer 122 that are alternately stacked in a direction away from the substrate 11.

[0042] Furthermore, in the first stack structure 12, the first gate sacrificial layer 121 can be formed between adjacent first insulating layers 122. The material of the first gate sacrificial layer 121 can be, but is not limited to, silicon nitride, and the material of the first insulating layer 122 can be, but is not limited to, silicon oxide, thereby forming a silicon nitride / silicon oxide stack structure. In subsequent steps, the first gate sacrificial layer 121 will be replaced by a replacement process and a conductive material (e.g., tungsten) will be filled in the same position to form the first gate layer.

[0043] In a three-dimensional memory, the number of layers of the first stack structure 12 determines the number of memory cells it contains in the vertical direction (perpendicular to the substrate 111). For example, the number of layers of the first stack structure 12 can be 32, 64, 96, 128, etc., and the more layers the first stack structure 12 has, the higher the integration of the corresponding three-dimensional memory.

[0044] Step S 122: Form a first channel hole 13 through the first stack structure 12.

[0045] The cross-sectional structure diagram after step S121 is shown below. Figure 2b As shown.

[0046] Specifically, an anisotropic etching process can be used, for example, a dry etching process (such as plasma etching, reactive ion etching, etc.) to etch the first stack structure 12 from top to bottom, forming a first channel hole 13 that passes through the first stack structure 12 and reaches the substrate 11, thereby exposing part of the substrate 11, and thus obtaining the first stack structure 12 with the first channel hole 13 penetrating through it. In a specific embodiment, please continue to refer to... Figure 2b The aforementioned first channel hole 13 can also penetrate the first stack structure 12 and extend into the interior of the substrate 11 to form a groove 11A on the substrate 11, thereby achieving sufficient etching to ensure that the substrate 11 can be exposed through the first channel hole 13, and also to increase the support effect of the channel structure formed in the first channel hole 13 on the first stack structure 12 in subsequent processes.

[0047] For example, such as Figure 2b As shown, the first channel hole 13 can penetrate the first stack structure 12, the stop layer 115, the second oxide layer 114 and the partial sacrificial layer 113 in a direction perpendicular to the substrate 111.

[0048] Step S13: A second stack structure with a second channel hole through it is formed on the first stack structure, and the second channel hole is connected to the first channel hole.

[0049] In one embodiment, prior to step S13 above, the following may also be included:

[0050] Step S15: Form a sacrificial material layer in the first channel hole.

[0051] The cross-sectional structure diagram after step S15 is shown below. Figure 2c As shown.

[0052] Specifically, methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition can be used to deposit and fill sacrificial material in the first channel hole 13, and chemical mechanical planarization can be used to remove the sacrificial material located outside the first channel hole 13 to obtain a sacrificial material layer 14. The sacrificial material can be any one of polycrystalline silicon, carbon, and tungsten. Thus, after the sacrificial material fills the first channel hole 13, the aforementioned first stack structure 12 can obtain a complete structural surface for subsequent formation of the second stack structure.

[0053] Accordingly, step S13 above can specifically include:

[0054] Step S 131: Form a second stack structure on the first stack structure and the sacrificial material layer.

[0055] The cross-sectional structure diagram after step S131 is shown below. Figure 2d As shown.

[0056] Specifically, the second stack structure 15 may include multiple alternating layers of a second gate sacrificial layer 151 and a second insulating layer 152 disposed in a direction away from the first stack structure 12. Furthermore, the second stack structure 15 can contact the first stack structure 12 through the second insulating layer 152. That is, the bottom layer of the second stack structure 15 can be the second insulating layer 152, and it contacts the top layer of the first stack structure 12. The method of forming the second stack structure 15 is the same as the method of forming the first stack structure 12, and therefore will not be described again.

[0057] In this embodiment, the first stack structure 12 is in contact with the second stack structure 15 through the first gate sacrificial layer 121, that is, the uppermost layer of the first stack structure 12 is the first gate sacrificial layer 121. Specifically, the outermost layer of the first stack structure 12 away from the substrate 11 in the semiconductor structure obtained after step S121 can be the first gate sacrificial layer 121 (e.g., Figure 2a (As shown). Thus, without additional operations, before the second stack structure 15 is formed on the first stack structure 12 and the sacrificial material layer 14, it can be ensured that the first stack structure 12 is in contact with the subsequently formed second stack structure 15 through the first gate sacrificial layer 121.

[0058] In some alternative embodiments, such as Figure 2eAs shown, in the semiconductor structure obtained after step S121, the outermost layer of the first stack structure 12 facing away from the substrate 11 can also be a first insulating layer 122. Correspondingly, the cross-sectional structure diagram after step S131 can be shown as follows: Figure 2f As shown, and in order to ensure that the first stack structure 12 is in contact with the subsequently formed second stack structure 15 through the first gate sacrificial layer 121, before step S 131 above, the following may also be included:

[0059] Step A: Align the sacrificial material layer 14 with the uppermost first gate sacrificial layer 121 of the first stack structure 12.

[0060] The cross-sectional structural diagram after step A is completed can be as follows: Figure 2c As shown.

[0061] It is understood that the uppermost first gate sacrificial layer 121 in the first stack structure 12 is the first gate sacrificial layer 121 farthest from the substrate 11 among the several first gate sacrificial layers 121 included in the first stack structure 12. The uppermost first insulating layer 122 in the first stack structure 12 is the first insulating layer 122 farthest from the substrate 11 among the several first insulating layers 122 included in the first stack structure 12.

[0062] The alignment of the sacrificial material layer 14 with the uppermost first gate sacrificial layer 121 in the first stack structure 12 can be understood as the surface of the sacrificial material layer 14 away from the substrate 11 (i.e., the upper surface of the sacrificial material layer 14) and the surface of the uppermost first gate sacrificial layer 121 away from the substrate 11 (i.e., the upper surface of the uppermost first gate sacrificial layer 121) in the first stack structure 12 being located in the same horizontal plane.

[0063] Specifically, during the process of aligning the sacrificial material layer 14 with the uppermost first gate sacrificial layer 121 of the first stack structure 12, the uppermost first insulating layer 122 of the first stack structure 12 (that is, the outermost layer of the first stack structure 12 that is away from the substrate 11) is removed to expose the first gate sacrificial layer 121 located below the uppermost first insulating layer 122 in the first stack structure 12.

[0064] In one specific embodiment, step A above may specifically include: aligning the sacrificial material layer 14 with the uppermost first gate sacrificial layer 121 of the first stack structure 12 through chemical mechanical polishing. Specifically, the uppermost first gate sacrificial layer 121 of the first stack structure 12 can be used as a polishing stop layer to polish the surface of the first stack structure 12 away from the substrate 11 (i.e., the top surface of the first stack structure 12) to expose the top surface of the uppermost first gate sacrificial layer 121 of the first stack structure 12.

[0065] In an alternative embodiment, step A above may further include: aligning the sacrificial material layer 14 with the uppermost first gate sacrificial layer 121 of the first stack structure 12 using wet etching. Specifically, the uppermost first gate sacrificial layer 121 of the first stack structure 12 can be used as an etching stop layer, and the first stack structure 12 can be etched from top to bottom until the etching stop layer is exposed, at which point the etching stops.

[0066] Accordingly, step S 131 can be specifically defined as: forming a second stack structure 15 on the trimmed sacrificial material layer 14 and the uppermost first gate sacrificial layer 121.

[0067] Step S 132: Form a second channel hole through the second stack structure, the second channel hole exposing the sacrificial material layer.

[0068] The cross-sectional structure diagram after step S132 is shown below. Figure 2g As shown.

[0069] Specifically, a second channel hole 16 can be formed by etching the second stack structure 15 from top to bottom, extending through the second stack structure 15 to the surface of the first stack structure 12. The bottom of the second channel hole 16 exposes at least a portion of the top surface of the sacrificial material layer 14 in the first channel hole 13.

[0070] Step S 133: Remove the sacrificial material layer via the second channel hole.

[0071] The cross-sectional structure diagram after step S133 is shown below. Figure 2h As shown.

[0072] Specifically, the sacrificial material layer 14 can be removed via the second channel hole 16, and a selective etchant can be used to selectively remove the sacrificial material layer 14 relative to the second stack structure 15 and the first stack structure 12 to obtain the interconnected second channel hole 16 and the first channel hole 13.

[0073] In other embodiments, an ashing process can be used to remove the sacrificial material layer 14 to obtain the interconnected second channel hole 16 and the first channel hole 13.

[0074] Step S14: Form a channel structure in the first channel hole and the second channel hole.

[0075] The cross-sectional structure diagram after step S14 is shown below. Figure 2i As shown.

[0076] The channel structure 17 may include a storage function layer and a channel layer sequentially disposed on the inner wall away from the first channel hole 13 and the second channel hole 16. Specifically, such as... Figure 3As shown, the storage functional layer may specifically include a first oxide layer 171 serving as a charge blocking layer, a second nitride layer 172 serving as a charge trapping layer, and a second oxide layer 173 serving as a tunneling layer, sequentially disposed on the inner wall away from the first channel hole 13 and the second channel hole 16. The materials of the first oxide layer 171, the second nitride layer 172, the second oxide layer 173, and the channel layer 174 may be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively.

[0077] In one specific embodiment, step S14 above may specifically include:

[0078] Step S 141: A first nitride layer is formed on the inner wall of the first channel hole 13 and the second channel hole 16.

[0079] The cross-sectional structure diagram after step S141 is shown below. Figure 2j As shown.

[0080] Specifically, a first nitride layer 18 can be deposited on the sidewalls and bottom surfaces of the first channel hole 13 and the second channel hole 16 using methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition. The material of the first nitride layer 18 can be the same as the material of the first gate sacrificial layer 121 and / or the second gate sacrificial layer 151. For example, the material of the first nitride layer 18 can be silicon nitride.

[0081] Step S 142: Oxidize the first nitride layer to obtain the first oxide layer 171.

[0082] The cross-sectional structure diagram after step S142 is shown below. Figure 2k As shown.

[0083] Specifically, the first nitride layer 18 can be oxidized by thermal oxidation to convert the first nitride layer 18 into a first oxide layer 171.

[0084] Step S 143: A second nitride layer 172 is formed on the side of the first oxide layer 171 opposite to the inner wall of the first channel hole 13 and the second channel hole 16.

[0085] Step S 144: A second oxide layer 173 is formed on the side of the second nitride layer 172 that is opposite to the first oxide layer 171.

[0086] Step S 145: A channel layer 174 is formed on the side of the second oxide layer 173 opposite to the second nitride layer 172 to obtain a channel structure 17 including the first oxide layer 171, the second nitride layer 172, the second oxide layer 173 and the channel layer 174.

[0087] The cross-sectional structure diagram after step S145 is shown below. Figure 2i As shown.

[0088] Furthermore, in other embodiments, such as Figure 2l and Figure 3 As shown, before forming the channel structure 17 in the first channel hole 13 and the second channel hole 16, the method may further include: forming an epitaxial layer 19 at the bottom of the first channel hole 13 by selective epitaxial growth, wherein the material of the epitaxial layer 19 may be a semiconductor material such as single crystal silicon. Furthermore, in a specific implementation, a first nitride layer 18 can be deposited on the sidewalls of the first channel hole 13 and the second channel hole 16 and on the surface of the epitaxial layer 19. Then, the first nitride layer 18 is oxidized to a first oxide layer 171. After that, a second nitride layer 172 and a second oxide layer 173, which serve as storage functional layers, can be deposited sequentially on the surface of the first oxide layer 171. Then, a portion of the storage functional layer on the surface of the epitaxial layer 19 is removed to expose the epitaxial layer 19. A semiconductor layer (e.g., a polysilicon layer) serving as a channel layer 174 is formed from the surface of the storage functional layer to the bottom of the first channel hole 13. Then, an oxide layer 175 is deposited inside the channel layer 174 to fill the remaining space in the first channel hole 13 and the second channel hole 16, thereby obtaining the aforementioned channel structure 17.

[0089] It should be noted that, as Figure 2h and Figure 3 As shown, since the first channel hole 13 and the second channel hole 16 are formed through different deep-hole etching steps, their lateral dimensions gradually decrease from top to bottom, and the top lateral dimension of the first channel hole 13 is larger than the bottom lateral dimension of the second channel hole 16, thus creating a stepped surface 17A on the sidewall of the aforementioned channel structure 17. The stepped surface 17A is located at the connection between the first stack structure 12 and the second stack structure 15, and is on the same horizontal plane as the top surface of the first stack structure 12 and the bottom surface of the second stack structure 15.

[0090] Furthermore, when a charge-blocking material layer (i.e., the aforementioned first nitride layer 18) is formed on the inner walls of the first channel hole 13 and the second channel hole 16, and the charge-blocking material layer is oxidized to obtain a corresponding charge-blocking layer (i.e., the aforementioned first oxide layer 171), a corner θ is formed between the first channel hole 13 and the second stack structure 15 because the top lateral dimension of the first channel hole 13 is larger than the bottom lateral dimension of the second channel hole 16. Furthermore, due to the presence of the corner θ, as... Figure 2jAs shown, after the charge-blocking material layer (i.e., the aforementioned first nitride layer 18) is formed on the sidewalls of the first channel hole 13 and the second channel hole 16, the thickness of the first nitride layer 18 located at the corner θ between the first channel hole 13 and the second stack structure 15 is greater than the thickness of the first nitride layer 18 at other locations. This results in the following situation after the first nitride layer 18 is oxidized to the first oxide layer 171: Figure 2k and Figure 4 As shown, the portion of the first nitride layer 18 located at the corner θ between the first channel hole 13 and the second stack structure 15 is difficult to oxidize and remains, so as to form a residue 18A at the connection between the first stack structure 12 and the second stack structure 15. Correspondingly, the remaining portion of the first nitride layer 18 will be oxidized to form the aforementioned first oxide layer 171.

[0091] Specifically, such as Figure 2i and Figure 3 As shown, the aforementioned residue 18A is located between the charge blocking layer (i.e., the first oxide layer 171) of the channel structure 17 and the outermost layer (i.e., the uppermost first gate sacrificial layer 121A) of the first stack structure 12 exposed through the sidewall of the first channel hole 13. Furthermore, the residue 18A can be connected to the uppermost first gate sacrificial layer 121A, and the upper surface of the residue 18A can be flush with the upper surface of the uppermost first gate sacrificial layer 121A. Therefore, in subsequent process steps where the first gate sacrificial layer 121 in the first stack structure 12 and the second gate sacrificial layer 151 in the second stack structure 15 are replaced with the corresponding first gate layer and second gate layer, the aforementioned residue 18A will also be replaced with a conductive structure.

[0092] It should be noted that, according to one embodiment of the method for manufacturing a three-dimensional memory, such as... Figure 5 and Figure 6As shown, the first stack structure 22 can contact the second stack structure 25 through the first insulating layer 222, and the second stack structure 25 can contact the first stack structure 22 through the second insulating layer 252. That is, the uppermost layer of the first stack structure 22 and the lowermost layer of the second stack structure 25 can be the first insulating layer 222 and the second insulating layer 252, respectively, thereby forming a channel structure 27 in the first channel hole 23 and the second channel hole 26. After replacing the first gate sacrificial layer 221 in the first stack structure 22 and the second gate sacrificial layer 251 in the second stack structure 25 with the corresponding first gate layer and second gate layer, respectively, the channel structure 27 formed in the preceding process steps is located in the channel. The residue 28A of the charge blocking material layer between the charge blocking layer 271 of the channel structure 27 and the outermost layer (i.e., the uppermost first insulating layer 222A) of the first stack structure 22 away from the substrate 21 will be wrapped by the uppermost first insulating layer 222A of the first stack structure 22 and the lowermost second insulating layer 252A of the second stack structure 25. It will not be replaced by a conductive structure. However, the presence of the residue 28A in the insulating layer will cause defects in the insulating layer, which will lead to voltage breakdown or leakage problems between two adjacent gate layers (i.e., the uppermost first insulating layer 222A and the lowermost second insulating layer 252A), affecting the yield and reliability of the three-dimensional memory.

[0093] At the same time, the inventors also discovered that, according to another embodiment of the method for manufacturing a three-dimensional memory, such as Figure 7 and Figure 8As shown, the first stack structure 22 is in contact with the second stack structure 25 through the first insulating layer 222, and the second stack structure 25 is in contact with the first stack structure 22 through the second gate sacrificial layer 251. That is, the uppermost layer of the first stack structure 22 and the lowermost layer of the second stack structure 25 can be the first insulating layer 222 and the second gate sacrificial layer 251, respectively. After the channel structure 27 is formed in the first channel hole 23 and the second channel hole 26, the residue 28A of the charge blocking material layer between the charge blocking layer 271 of the channel structure 27 and the outermost layer of the first stack structure 22 away from the substrate 21 (that is, the uppermost first insulating layer 222A) will be relatively long and thin in the vertical direction, and will easily extend to the lowermost second gate sacrificial layer 251A of the second stack structure 25. After the first gate sacrificial layer 221 in the stack structure 22 and the second gate sacrificial layer 251 in the second stack structure 25 are replaced with the corresponding first gate layer and second gate layer, the residue 28A will be replaced with the first gate sacrificial layer 221 and the second gate sacrificial layer 252 together to form a conductive structure. This conductive structure is on the same layer as the uppermost first insulating layer 222A of the first stack structure 22, that is, it is located between the uppermost first gate layer of the first stack structure 22 and the lowermost second gate layer of the second stack structure 25. It is very easy to connect with the uppermost first gate layer of the first stack structure 22 and / or the lowermost second gate layer of the second stack structure 25, which will lead to the problem of tip discharge of the gate layer or leakage between adjacent gate layers in the three-dimensional memory, affecting the yield and reliability of the three-dimensional memory.

[0094] Furthermore, it is understood that in this embodiment, as Figure 2i and Figure 3 As shown, since the first stack structure 12 is in contact with the second stack structure 15 through the first sacrificial material layer 121, after the first gate sacrificial layer 121 in the first stack structure 12 and the second gate sacrificial layer 151 in the second stack structure 15 are replaced with the corresponding first gate layer and second gate layer, the residue 18A of the charge barrier material layer formed in the preceding process steps will be replaced with a conductive structure. This conductive structure is on the same layer as the uppermost first gate layer in the first stack structure 22. This avoids the problem of point discharge or leakage between adjacent gate layers caused by the conductive structure obtained by the replacement of the charge barrier material layer residue in some three-dimensional memories being located between gate layers. It also avoids the problem of defects in the insulating layer between gate layers caused by the charge barrier material layer residue being located inside the insulating layer between gate layers in other three-dimensional memories, which can easily lead to voltage breakdown or leakage between gate layers. Therefore, the yield and reliability of the three-dimensional memory are improved.

[0095] In the above embodiments, after step S14, the method for manufacturing the three-dimensional memory may further include:

[0096] Step S16: Form a gate wire gap that runs through the first stack structure and the second stack structure.

[0097] For example, the second stack structure 15 and the first stack structure 12 can be etched from top to bottom to form a grid line gap that runs through the second stack structure 15 and the first stack structure 12 (not shown in the figure because it is not a feature of this case).

[0098] Step S17: Replace the first gate sacrificial layer in the first stack structure and the second gate sacrificial layer in the second stack structure with the first gate layer and the second gate layer, respectively, through the gate line gap.

[0099] For example, the first gate sacrificial layer 121 of the first stack structure 12 and the second gate sacrificial layer 151 of the second stack structure 15 can be replaced by a replacement process, and conductive material (e.g., tungsten) can be filled in the same position to form the first gate layer of the first stack structure 12 and the second gate layer of the second stack structure 15.

[0100] In one specific embodiment, such as Figure 2i and Figure 3 As shown, the residue 18A can be connected to the uppermost first gate sacrificial layer 121A in the first stack structure 12, and the upper surface of the residue 18A (that is, the surface of the residue 18A facing away from the substrate 11) and the upper surface of the uppermost first gate sacrificial layer 121A in the first stack structure 12 (that is, the surface of the uppermost first gate sacrificial layer 121A facing away from the substrate 11) can be flush, that is, located in the same horizontal plane.

[0101] In some embodiments, after forming gate line gaps through the first stack structure 12 and the second stack structure 15, the aforementioned residue 18A can be replaced with a redundant gate layer through the gate line gaps. Specifically, the redundant gate layer can be connected to the uppermost first gate layer of the first stack structure 12, and the upper surface of the redundant gate layer can be flush with the upper surface of the uppermost first gate layer of the first stack structure 12.

[0102] Furthermore, in specific implementation, the first gate layer, the second gate layer, and the redundant gate layer can be formed through the same process steps. Accordingly, the above step S17 can specifically include: replacing the first gate sacrificial layer 121 in the first stack structure 12, the second gate sacrificial layer 151 in the second stack structure 15, and the residue 18A with the first gate layer, the second gate layer, and the redundant gate layer, respectively, through the gate line gap.

[0103] In some embodiments, after step S17, the gate layer obtained by replacement can be etched through the gate line gap to form a gap between the gate layer and the gate line gap. In subsequent processes, when the gate line gap is filled with semiconductor material and / or metal material, the gap between the gate layer and the gate line gap is also filled by the insulating layer and semiconductor material and / or metal material.

[0104] Furthermore, following step S17 above, the following may also be included:

[0105] Step S18: Fill the gate gaps with semiconductor material and / or metal material.

[0106] For example, a spacer layer (e.g., an oxide layer) as a dielectric layer and a conductive material (e.g., titanium or titanium nitride, polycrystalline silicon and / or tungsten metal) as a common source electrode can be filled into the gaps in the gate lines to obtain a common source electrode structure.

[0107] The method for fabricating a three-dimensional memory provided in this embodiment involves forming a substrate and then forming a first stack structure with a first channel hole through it. The first stack structure includes multiple alternating layers of a first gate sacrificial layer and a first insulating layer in a direction perpendicular to the substrate, with the first gate sacrificial layer located at the end of the first stack structure furthest from the substrate. A second stack structure with a second channel hole through it is then formed on the first stack structure, and the second channel hole communicates with the first channel hole. A channel structure is then formed in the first and second channel holes. This avoids the problem of residual material layers used to form the charge blocking layer in the channel structure remaining at the connection between the first and second stack structures due to the large lateral thickness at the junction of the first and second stack structures. This residual material is located in the insulating layers of the two stack structures, and after the gate sacrificial layers in the two stack structures are replaced with the corresponding gate layers, leakage can easily occur between adjacent gate layers due to the presence of this residual material in the insulating layer between adjacent gate layers or the presence of conductive structures obtained after replacing the residual material with gate material. This improves the yield and reliability of the three-dimensional memory.

[0108] The three-dimensional memory fabricated according to the above-described method embodiments of the present invention is as follows: Figure 2i and Figure 3As shown, the three-dimensional memory includes a first stack structure 12, a second stack structure 15 located on the first stack structure 12, and a channel structure 17 penetrating the first stack structure 12 and the second stack structure 15. The first stack structure 12 may include multiple alternating layers of a first gate layer 121 (with the same reference numerals as the first gate sacrificial layer 121 in the above method embodiment) and a first insulating layer 122 in a direction away from the second stack structure 15. The second stack structure 15 may include multiple alternating layers of a second gate layer 151 (with the same reference numerals as the second gate sacrificial layer 151 in the above method embodiment) and a second insulating layer 152 in a direction away from the first stack structure 12. Furthermore, the sidewall of the channel structure 17 has a stepped surface 17A, which is flush with the surface of the first stack structure 12 that contacts the second stack structure 15, and the first stack structure 12 contacts the second stack structure 15 through the uppermost first gate layer 121A.

[0109] In one embodiment, the three-dimensional memory may further include a redundant gate layer 18A (with the same reference numerals as the residue 18A in the above method embodiment), the redundant gate layer 18A being located between the channel structure 17 and the uppermost first gate layer 121A of the first stack structure 12.

[0110] In one specific embodiment, the redundant gate layer 18A may be located on top of the first stack structure 12. Specifically, the redundant gate layer 18A may also surround the channel structure 17.

[0111] In some specific embodiments, the redundant gate layer 18A can be connected to the uppermost first gate layer 121 in the first stack structure 12, and the upper surface of the redundant gate layer 18A can be flush with the upper surface of the uppermost first gate layer 121A in the first stack structure 12, that is, the upper surface of the redundant gate layer 18A can be located in the same horizontal plane as the upper surface of the first gate layer 121A.

[0112] In one specific embodiment, the material of the redundant gate layer 18A can be the same as that of the first gate layer 121, for example, it can be a conductive material such as tungsten metal.

[0113] In one embodiment, the channel structure 17 may include a channel layer 174, a second oxide layer 173 surrounding the channel layer 174, a second nitride layer 172 surrounding the second oxide layer 173, and a first oxide layer 171 surrounding the second nitride layer 172.

[0114] It should be noted that the various structures of the three-dimensional memory in this embodiment can refer to the specific implementation methods described in the above method embodiments, so they will not be repeated here.

[0115] The three-dimensional memory provided in this embodiment, by aligning the stepped surface on the inner wall of the channel structure with the top surface of the first stack structure and making the first stack structure contact the second stack structure through the uppermost first gate layer, can avoid the problem of residual material layer used to form the charge blocking layer in the channel structure due to the large lateral thickness at the connection between the first and second stack structures after the charge blocking layer is formed. This would result in residual material being located in the insulating layer of the two stack structures, and subsequently, after replacing the gate sacrificial layer in the two stack structures with the corresponding gate layer, leakage would easily occur between adjacent gate layers due to the presence of this residual material in the insulating layer between adjacent gate layers or the presence of a conductive structure obtained after replacing the residual material with gate material. This improves the yield and reliability of the three-dimensional memory.

[0116] Accordingly, embodiments of the present invention also provide a storage system, which includes a controller and a three-dimensional memory of any of the above embodiments, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

[0117] The three-dimensional memory includes a first stack structure, a second stack structure located on the first stack structure, and a channel structure penetrating both the first and second stack structures. The first stack structure includes multiple alternating layers of a first gate layer and a first insulating layer stacked in a direction away from the second stack structure. Furthermore, the sidewalls of the channel structure have stepped surfaces, which are flush with the surfaces of the first stack structure that contact the second stack structure. The first stack structure contacts the second stack structure through its uppermost first gate layer.

[0118] The storage system provided in this embodiment aligns the stepped surface on the inner wall of the channel structure with the top surface of the first stack structure, and makes the first stack structure contact the second stack structure through the uppermost first gate layer. This avoids the problem of residual raw material layers used to form the charge blocking layer in the channel structure remaining at the connection between the first and second stack structures due to the large lateral thickness at the connection. This residual raw material would be located in the insulating layer of the two stack structures, and after the gate sacrificial layer in the two stack structures is replaced with the corresponding gate layer, leakage would easily occur between adjacent gate layers because of the residual raw material in the insulating layer between adjacent gate layers or the conductive structure obtained after replacing the residual raw material with the gate material. This improves the yield and reliability of the three-dimensional memory.

[0119] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: Forming a base; A first stack structure with a first channel hole is formed on the substrate. The first stack structure includes multiple alternating layers of a first gate sacrificial layer and a first insulating layer in a direction perpendicular to the substrate, and the end of the first stack structure away from the substrate is the first gate sacrificial layer. A second stack structure with a second channel hole is formed on the first stack structure. The second channel hole communicates with the first channel hole, and the interface between the second channel hole and the first channel hole is located on the first gate sacrificial layer at the top of the first stack structure. A channel structure is formed in the first channel hole and the second channel hole, and residue is formed between the channel structure and the uppermost first gate sacrificial layer of the first stack structure; The first gate sacrificial layer in the first stack structure is replaced with the first gate layer, and the residue is replaced with a redundant gate layer.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Before forming the second stack structure with the second channel hole through the first stack structure, the method further includes: A sacrificial material layer is formed in the first channel hole; The sacrificial material layer is aligned with the first gate sacrificial layer, which is the uppermost layer in the first stack structure. The formation of a second stack structure with a second channel hole through the first stack structure specifically includes: A second stack structure is formed on the trimmed sacrificial material layer and the topmost first gate sacrificial layer; A second channel hole is formed through the second stack structure, the second channel hole exposing the sacrificial material layer; The sacrificial material layer is removed via the second channel hole.

3. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of a channel structure in the first channel hole and the second channel hole specifically includes: A first nitride layer is formed on the inner walls of the first and second channel holes; The first nitride layer is oxidized to obtain the first oxide layer; A second nitride layer is formed on the side of the first oxide layer facing away from the inner wall; A second oxide layer is formed on the side of the second nitride layer that is opposite to the first oxide layer; A channel layer is formed on the side of the second oxide layer opposite to the second nitride layer to obtain a channel structure including the first oxide layer, the second nitride layer, the second oxide layer and the channel layer.

4. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that, A corner is formed between the inner wall of the first channel hole and the second stack structure. After the first nitride layer is oxidized, a portion of the first nitride layer located at the corner is left as a residue, and the remaining portion of the first nitride layer is oxidized to form the first oxide layer.

5. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that, The residue is connected to the first gate sacrificial layer, and the upper surface of the residue is flush with the upper surface of the first gate sacrificial layer.

6. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that, After forming the channel structure in the first channel hole and the second channel hole, the method further includes: Forming a gate line gap that runs through the first stack structure and the second stack structure; Through the gate line gap, the first gate sacrificial layer in the first stack structure and the second gate sacrificial layer in the second stack structure are respectively replaced with the first gate layer and the second gate layer.

7. The method for manufacturing a three-dimensional memory according to claim 6, characterized in that, After forming the gate wire gaps through the first stack structure and the second stack structure, the method further includes: The residue is replaced with a redundant gate layer through the gate line gap. The redundant gate layer is connected to the first gate layer, and the upper surface of the redundant gate layer is flush with the upper surface of the first gate layer.

8. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that, The material of the first nitride layer is the same as that of the first gate sacrificial layer.

9. A three-dimensional memory, characterized in that, include: First stack structure; A second stack structure located on the first stack structure, wherein the first stack structure includes a first gate layer and a first insulating layer that are alternately stacked in multiple layers in a direction away from the second stack structure; A channel structure runs through the first stack structure and the second stack structure. The sidewall of the channel structure has a stepped surface. The stepped surface is flush with the surface of the first stack structure that contacts the second stack structure. The first stack structure contacts the second stack structure through the uppermost first gate layer. A redundant gate layer is located between the channel structure and the uppermost first gate layer in the first stack structure.

10. The three-dimensional memory according to claim 9, characterized in that, The redundant gate layer is connected to the first gate layer, and the upper surface of the redundant gate layer is flush with the upper surface of the first gate layer.

11. The three-dimensional memory according to claim 9, characterized in that, The material of the redundant gate layer is the same as that of the first gate layer.

12. The three-dimensional memory according to claim 9, characterized in that, The channel structure includes a channel layer, a second oxide layer surrounding the channel layer, a second nitride layer surrounding the second oxide layer, and a first oxide layer surrounding the second nitride layer.

13. A storage system, characterized in that, The storage system includes a controller and a three-dimensional memory according to any one of claims 9 to 12, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

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